1package xiangshan.backend 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util.BitPat.bitPatToUInt 6import chisel3.util._ 7import utils.BundleUtils.makeValid 8import utils.OptionWrapper 9import xiangshan._ 10import xiangshan.backend.datapath.DataConfig._ 11import xiangshan.backend.datapath.DataSource 12import xiangshan.backend.datapath.WbConfig.PregWB 13import xiangshan.backend.decode.{ImmUnion, XDecode} 14import xiangshan.backend.exu.ExeUnitParams 15import xiangshan.backend.fu.FuType 16import xiangshan.backend.fu.fpu.Bundles.Frm 17import xiangshan.backend.fu.vector.Bundles._ 18import xiangshan.backend.issue.{IssueBlockParams, IssueQueueDeqRespBundle, SchedulerType} 19import xiangshan.backend.issue.EntryBundles._ 20import xiangshan.backend.regfile.{RfReadPortWithConfig, RfWritePortWithConfig} 21import xiangshan.backend.rob.RobPtr 22import xiangshan.frontend._ 23import xiangshan.mem.{LqPtr, SqPtr} 24import yunsuan.vector.VIFuParam 25 26object Bundles { 27 /** 28 * Connect Same Name Port like bundleSource := bundleSinkBudle. 29 * 30 * There is no limit to the number of ports on both sides. 31 * 32 * Don't forget to connect the remaining ports! 33 */ 34 def connectSamePort (bundleSource: Bundle, bundleSink: Bundle):Unit = { 35 bundleSource.elements.foreach { case (name, data) => 36 if (bundleSink.elements.contains(name)) 37 data := bundleSink.elements(name) 38 } 39 } 40 // frontend -> backend 41 class StaticInst(implicit p: Parameters) extends XSBundle { 42 val instr = UInt(32.W) 43 val pc = UInt(VAddrBits.W) 44 val foldpc = UInt(MemPredPCWidth.W) 45 val exceptionVec = ExceptionVec() 46 val trigger = new TriggerCf 47 val preDecodeInfo = new PreDecodeInfo 48 val pred_taken = Bool() 49 val crossPageIPFFix = Bool() 50 val ftqPtr = new FtqPtr 51 val ftqOffset = UInt(log2Up(PredictWidth).W) 52 53 def connectCtrlFlow(source: CtrlFlow): Unit = { 54 this.instr := source.instr 55 this.pc := source.pc 56 this.foldpc := source.foldpc 57 this.exceptionVec := source.exceptionVec 58 this.trigger := source.trigger 59 this.preDecodeInfo := source.pd 60 this.pred_taken := source.pred_taken 61 this.crossPageIPFFix := source.crossPageIPFFix 62 this.ftqPtr := source.ftqPtr 63 this.ftqOffset := source.ftqOffset 64 } 65 } 66 67 // StaticInst --[Decode]--> DecodedInst 68 class DecodedInst(implicit p: Parameters) extends XSBundle { 69 def numSrc = backendParams.numSrc 70 // passed from StaticInst 71 val instr = UInt(32.W) 72 val pc = UInt(VAddrBits.W) 73 val foldpc = UInt(MemPredPCWidth.W) 74 val exceptionVec = ExceptionVec() 75 val trigger = new TriggerCf 76 val preDecodeInfo = new PreDecodeInfo 77 val pred_taken = Bool() 78 val crossPageIPFFix = Bool() 79 val ftqPtr = new FtqPtr 80 val ftqOffset = UInt(log2Up(PredictWidth).W) 81 // decoded 82 val srcType = Vec(numSrc, SrcType()) 83 val lsrc = Vec(numSrc, UInt(6.W)) 84 val ldest = UInt(6.W) 85 val fuType = FuType() 86 val fuOpType = FuOpType() 87 val rfWen = Bool() 88 val fpWen = Bool() 89 val vecWen = Bool() 90 val isXSTrap = Bool() 91 val waitForward = Bool() // no speculate execution 92 val blockBackward = Bool() 93 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 94 val canRobCompress = Bool() 95 val selImm = SelImm() 96 val imm = UInt(ImmUnion.maxLen.W) 97 val fpu = new FPUCtrlSignals 98 val vpu = new VPUCtrlSignals 99 val vlsInstr = Bool() 100 val wfflags = Bool() 101 val isMove = Bool() 102 val uopIdx = UopIdx() 103 val uopSplitType = UopSplitType() 104 val isVset = Bool() 105 val firstUop = Bool() 106 val lastUop = Bool() 107 val numUops = UInt(log2Up(MaxUopSize).W) // rob need this 108 val numWB = UInt(log2Up(MaxUopSize).W) // rob need this 109 val commitType = CommitType() // Todo: remove it 110 111 val debug_fuType = OptionWrapper(backendParams.debugEn, FuType()) 112 113 private def allSignals = srcType.take(3) ++ Seq(fuType, fuOpType, rfWen, fpWen, vecWen, 114 isXSTrap, waitForward, blockBackward, flushPipe, canRobCompress, uopSplitType, selImm) 115 116 def decode(inst: UInt, table: Iterable[(BitPat, List[BitPat])]): DecodedInst = { 117 val decoder: Seq[UInt] = ListLookup( 118 inst, XDecode.decodeDefault.map(bitPatToUInt), 119 table.map{ case (pat, pats) => (pat, pats.map(bitPatToUInt)) }.toArray 120 ) 121 allSignals zip decoder foreach { case (s, d) => s := d } 122 debug_fuType.foreach(_ := fuType) 123 this 124 } 125 126 def isSoftPrefetch: Bool = { 127 fuType === FuType.alu.U && fuOpType === ALUOpType.or && selImm === SelImm.IMM_I && ldest === 0.U 128 } 129 130 def connectStaticInst(source: StaticInst): Unit = { 131 for ((name, data) <- this.elements) { 132 if (source.elements.contains(name)) { 133 data := source.elements(name) 134 } 135 } 136 } 137 } 138 139 // DecodedInst --[Rename]--> DynInst 140 class DynInst(implicit p: Parameters) extends XSBundle { 141 def numSrc = backendParams.numSrc 142 // passed from StaticInst 143 val instr = UInt(32.W) 144 val pc = UInt(VAddrBits.W) 145 val foldpc = UInt(MemPredPCWidth.W) 146 val exceptionVec = ExceptionVec() 147 val trigger = new TriggerCf 148 val preDecodeInfo = new PreDecodeInfo 149 val pred_taken = Bool() 150 val crossPageIPFFix = Bool() 151 val ftqPtr = new FtqPtr 152 val ftqOffset = UInt(log2Up(PredictWidth).W) 153 // passed from DecodedInst 154 val srcType = Vec(numSrc, SrcType()) 155 val ldest = UInt(6.W) 156 val fuType = FuType() 157 val fuOpType = FuOpType() 158 val rfWen = Bool() 159 val fpWen = Bool() 160 val vecWen = Bool() 161 val isXSTrap = Bool() 162 val waitForward = Bool() // no speculate execution 163 val blockBackward = Bool() 164 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 165 val canRobCompress = Bool() 166 val selImm = SelImm() 167 val imm = UInt(32.W) 168 val fpu = new FPUCtrlSignals 169 val vpu = new VPUCtrlSignals 170 val vlsInstr = Bool() 171 val wfflags = Bool() 172 val isMove = Bool() 173 val uopIdx = UopIdx() 174 val isVset = Bool() 175 val firstUop = Bool() 176 val lastUop = Bool() 177 val numUops = UInt(log2Up(MaxUopSize).W) // rob need this 178 val numWB = UInt(log2Up(MaxUopSize).W) // rob need this 179 val commitType = CommitType() 180 // rename 181 val srcState = Vec(numSrc, SrcState()) 182 val srcLoadDependency = Vec(numSrc, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 183 val psrc = Vec(numSrc, UInt(PhyRegIdxWidth.W)) 184 val pdest = UInt(PhyRegIdxWidth.W) 185 val robIdx = new RobPtr 186 val instrSize = UInt(log2Ceil(RenameWidth + 1).W) 187 val dirtyFs = Bool() 188 val dirtyVs = Bool() 189 190 val eliminatedMove = Bool() 191 // Take snapshot at this CFI inst 192 val snapshot = Bool() 193 val debugInfo = new PerfDebugInfo 194 val storeSetHit = Bool() // inst has been allocated an store set 195 val waitForRobIdx = new RobPtr // store set predicted previous store robIdx 196 // Load wait is needed 197 // load inst will not be executed until former store (predicted by mdp) addr calcuated 198 val loadWaitBit = Bool() 199 // If (loadWaitBit && loadWaitStrict), strict load wait is needed 200 // load inst will not be executed until ALL former store addr calcuated 201 val loadWaitStrict = Bool() 202 val ssid = UInt(SSIDWidth.W) 203 // Todo 204 val lqIdx = new LqPtr 205 val sqIdx = new SqPtr 206 // debug module 207 val singleStep = Bool() 208 // schedule 209 val replayInst = Bool() 210 211 val debug_fuType = OptionWrapper(backendParams.debugEn, FuType()) 212 213 val numLsElem = NumLsElem() 214 215 def getDebugFuType: UInt = debug_fuType.getOrElse(fuType) 216 217 def isLUI: Bool = this.fuType === FuType.alu.U && (this.selImm === SelImm.IMM_U || this.selImm === SelImm.IMM_LUI32) 218 def isLUI32: Bool = this.selImm === SelImm.IMM_LUI32 219 def isWFI: Bool = this.fuType === FuType.csr.U && fuOpType === CSROpType.wfi 220 221 def isSvinvalBegin(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && !flush 222 def isSvinval(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.sfence && !flush 223 def isSvinvalEnd(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && flush 224 225 def isHls: Bool = { 226 fuType === FuType.ldu.U && LSUOpType.isHlv(fuOpType) || fuType === FuType.stu.U && LSUOpType.isHsv(fuOpType) 227 } 228 229 def srcIsReady: Vec[Bool] = { 230 VecInit(this.srcType.zip(this.srcState).map { 231 case (t, s) => SrcType.isNotReg(t) || SrcState.isReady(s) 232 }) 233 } 234 235 def clearExceptions( 236 exceptionBits: Seq[Int] = Seq(), 237 flushPipe : Boolean = false, 238 replayInst : Boolean = false 239 ): DynInst = { 240 this.exceptionVec.zipWithIndex.filterNot(x => exceptionBits.contains(x._2)).foreach(_._1 := false.B) 241 if (!flushPipe) { this.flushPipe := false.B } 242 if (!replayInst) { this.replayInst := false.B } 243 this 244 } 245 246 def needWriteRf: Bool = (rfWen && ldest =/= 0.U) || fpWen || vecWen 247 } 248 249 trait BundleSource { 250 var wakeupSource = "undefined" 251 var idx = 0 252 } 253 254 /** 255 * 256 * @param pregIdxWidth index width of preg 257 * @param exuIndices exu indices of wakeup bundle 258 */ 259 sealed abstract class IssueQueueWakeUpBaseBundle(pregIdxWidth: Int, val exuIndices: Seq[Int])(implicit p: Parameters) extends XSBundle { 260 val rfWen = Bool() 261 val fpWen = Bool() 262 val vecWen = Bool() 263 val pdest = UInt(pregIdxWidth.W) 264 265 /** 266 * @param successor Seq[(psrc, srcType)] 267 * @return Seq[if wakeup psrc] 268 */ 269 def wakeUp(successor: Seq[(UInt, UInt)], valid: Bool): Seq[Bool] = { 270 successor.map { case (thatPsrc, srcType) => 271 val pdestMatch = pdest === thatPsrc 272 pdestMatch && ( 273 SrcType.isFp(srcType) && this.fpWen || 274 SrcType.isXp(srcType) && this.rfWen || 275 SrcType.isVp(srcType) && this.vecWen 276 ) && valid 277 } 278 } 279 def wakeUpFromIQ(successor: Seq[(UInt, UInt)]): Seq[Bool] = { 280 successor.map { case (thatPsrc, srcType) => 281 val pdestMatch = pdest === thatPsrc 282 pdestMatch && ( 283 SrcType.isFp(srcType) && this.fpWen || 284 SrcType.isXp(srcType) && this.rfWen || 285 SrcType.isVp(srcType) && this.vecWen 286 ) 287 } 288 } 289 290 def hasOnlyOneSource: Boolean = exuIndices.size == 1 291 292 def hasMultiSources: Boolean = exuIndices.size > 1 293 294 def isWBWakeUp = this.isInstanceOf[IssueQueueWBWakeUpBundle] 295 296 def isIQWakeUp = this.isInstanceOf[IssueQueueIQWakeUpBundle] 297 298 def exuIdx: Int = { 299 require(hasOnlyOneSource) 300 this.exuIndices.head 301 } 302 } 303 304 class IssueQueueWBWakeUpBundle(exuIndices: Seq[Int], backendParams: BackendParams)(implicit p: Parameters) extends IssueQueueWakeUpBaseBundle(backendParams.pregIdxWidth, exuIndices) { 305 306 } 307 308 class IssueQueueIQWakeUpBundle( 309 exuIdx: Int, 310 backendParams: BackendParams, 311 copyWakeupOut: Boolean = false, 312 copyNum: Int = 0 313 )(implicit p: Parameters) extends IssueQueueWakeUpBaseBundle(backendParams.pregIdxWidth, Seq(exuIdx)) { 314 val loadDependency = Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W)) 315 val is0Lat = Bool() 316 val params = backendParams.allExuParams.filter(_.exuIdx == exuIdx).head 317 val pdestCopy = OptionWrapper(copyWakeupOut, Vec(copyNum, UInt(params.wbPregIdxWidth.W))) 318 val rfWenCopy = OptionWrapper(copyWakeupOut && params.needIntWen, Vec(copyNum, Bool())) 319 val fpWenCopy = OptionWrapper(copyWakeupOut && params.needFpWen, Vec(copyNum, Bool())) 320 val vecWenCopy = OptionWrapper(copyWakeupOut && params.needVecWen, Vec(copyNum, Bool())) 321 val loadDependencyCopy = OptionWrapper(copyWakeupOut && params.isIQWakeUpSink, Vec(copyNum, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W)))) 322 def fromExuInput(exuInput: ExuInput, l2ExuVecs: Vec[UInt]): Unit = { 323 this.rfWen := exuInput.rfWen.getOrElse(false.B) 324 this.fpWen := exuInput.fpWen.getOrElse(false.B) 325 this.vecWen := exuInput.vecWen.getOrElse(false.B) 326 this.pdest := exuInput.pdest 327 } 328 329 def fromExuInput(exuInput: ExuInput): Unit = { 330 this.rfWen := exuInput.rfWen.getOrElse(false.B) 331 this.fpWen := exuInput.fpWen.getOrElse(false.B) 332 this.vecWen := exuInput.vecWen.getOrElse(false.B) 333 this.pdest := exuInput.pdest 334 } 335 } 336 337 class VPUCtrlSignals(implicit p: Parameters) extends XSBundle { 338 // vtype 339 val vill = Bool() 340 val vma = Bool() // 1: agnostic, 0: undisturbed 341 val vta = Bool() // 1: agnostic, 0: undisturbed 342 val vsew = VSew() 343 val vlmul = VLmul() // 1/8~8 --> -3~3 344 345 val vm = Bool() // 0: need v0.t 346 val vstart = Vl() 347 348 // float rounding mode 349 val frm = Frm() 350 // scalar float instr and vector float reduction 351 val fpu = Fpu() 352 // vector fix int rounding mode 353 val vxrm = Vxrm() 354 // vector uop index, exclude other non-vector uop 355 val vuopIdx = UopIdx() 356 val lastUop = Bool() 357 // maybe used if data dependancy 358 val vmask = UInt(MaskSrcData().dataWidth.W) 359 val vl = Vl() 360 361 // vector load/store 362 val nf = Nf() 363 val veew = VEew() 364 365 val isReverse = Bool() // vrsub, vrdiv 366 val isExt = Bool() 367 val isNarrow = Bool() 368 val isDstMask = Bool() // vvm, vvvm, mmm 369 val isOpMask = Bool() // vmand, vmnand 370 val isMove = Bool() // vmv.s.x, vmv.v.v, vmv.v.x, vmv.v.i 371 372 val isDependOldvd = Bool() // some instruction's computation depends on oldvd 373 val isWritePartVd = Bool() // some instruction's computation writes part of vd, such as vredsum 374 375 def vtype: VType = { 376 val res = Wire(VType()) 377 res.illegal := this.vill 378 res.vma := this.vma 379 res.vta := this.vta 380 res.vsew := this.vsew 381 res.vlmul := this.vlmul 382 res 383 } 384 385 def vconfig: VConfig = { 386 val res = Wire(VConfig()) 387 res.vtype := this.vtype 388 res.vl := this.vl 389 res 390 } 391 392 def connectVType(source: VType): Unit = { 393 this.vill := source.illegal 394 this.vma := source.vma 395 this.vta := source.vta 396 this.vsew := source.vsew 397 this.vlmul := source.vlmul 398 } 399 } 400 401 // DynInst --[IssueQueue]--> DataPath 402 class IssueQueueIssueBundle( 403 iqParams: IssueBlockParams, 404 val exuParams: ExeUnitParams, 405 )(implicit 406 p: Parameters 407 ) extends Bundle { 408 private val rfReadDataCfgSet: Seq[Set[DataConfig]] = exuParams.getRfReadDataCfgSet 409 410 val rf: MixedVec[MixedVec[RfReadPortWithConfig]] = Flipped(MixedVec( 411 rfReadDataCfgSet.map((set: Set[DataConfig]) => 412 MixedVec(set.map((x: DataConfig) => new RfReadPortWithConfig(x, exuParams.rdPregIdxWidth)).toSeq) 413 ) 414 )) 415 416 val srcType = Vec(exuParams.numRegSrc, SrcType()) // used to select imm or reg data 417 val immType = SelImm() // used to select imm extractor 418 val common = new ExuInput(exuParams) 419 val addrOH = UInt(iqParams.numEntries.W) 420 421 def exuIdx = exuParams.exuIdx 422 def getSource: SchedulerType = exuParams.getWBSource 423 def getIntWbBusyBundle = common.rfWen.toSeq 424 def getVfWbBusyBundle = common.getVfWen.toSeq 425 426 def getIntRfReadValidBundle(issueValid: Bool): Seq[ValidIO[RfReadPortWithConfig]] = { 427 rf.zip(srcType).map { 428 case (rfRd: MixedVec[RfReadPortWithConfig], t: UInt) => 429 makeValid(issueValid, rfRd.head) 430 }.toSeq 431 } 432 433 def getFpRfReadValidBundle(issueValid: Bool): Seq[ValidIO[RfReadPortWithConfig]] = { 434 rf.zip(srcType).map { 435 case (rfRd: MixedVec[RfReadPortWithConfig], t: UInt) => 436 makeValid(issueValid, rfRd.head) 437 }.toSeq 438 } 439 440 def getVfRfReadValidBundle(issueValid: Bool): Seq[ValidIO[RfReadPortWithConfig]] = { 441 rf.zip(srcType).map { 442 case (rfRd: MixedVec[RfReadPortWithConfig], t: UInt) => 443 makeValid(issueValid, rfRd.head) 444 }.toSeq 445 } 446 447 def getIntRfWriteValidBundle(issueValid: Bool) = { 448 449 } 450 } 451 452 class OGRespBundle(implicit p:Parameters, params: IssueBlockParams) extends XSBundle { 453 val issueQueueParams = this.params 454 val og0resp = Valid(new EntryDeqRespBundle) 455 val og1resp = Valid(new EntryDeqRespBundle) 456 } 457 458 class fuBusyRespBundle(implicit p: Parameters, params: IssueBlockParams) extends Bundle { 459 val respType = RSFeedbackType() // update credit if needs replay 460 val rfWen = Bool() // TODO: use params to identify IntWB/VfWB 461 val fuType = FuType() 462 } 463 464 class WbFuBusyTableWriteBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 465 private val intCertainLat = params.intLatencyCertain 466 private val fpCertainLat = params.fpLatencyCertain 467 private val vfCertainLat = params.vfLatencyCertain 468 private val intLat = params.intLatencyValMax 469 private val fpLat = params.fpLatencyValMax 470 private val vfLat = params.vfLatencyValMax 471 472 val intWbBusyTable = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 473 val fpWbBusyTable = OptionWrapper(fpCertainLat, UInt((fpLat + 1).W)) 474 val vfWbBusyTable = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 475 val intDeqRespSet = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 476 val fpDeqRespSet = OptionWrapper(fpCertainLat, UInt((fpLat + 1).W)) 477 val vfDeqRespSet = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 478 } 479 480 class WbFuBusyTableReadBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 481 private val intCertainLat = params.intLatencyCertain 482 private val fpCertainLat = params.fpLatencyCertain 483 private val vfCertainLat = params.vfLatencyCertain 484 private val intLat = params.intLatencyValMax 485 private val fpLat = params.fpLatencyValMax 486 private val vfLat = params.vfLatencyValMax 487 488 val intWbBusyTable = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 489 val fpWbBusyTable = OptionWrapper(fpCertainLat, UInt((fpLat + 1).W)) 490 val vfWbBusyTable = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 491 } 492 493 class WbConflictBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 494 private val intCertainLat = params.intLatencyCertain 495 private val fpCertainLat = params.fpLatencyCertain 496 private val vfCertainLat = params.vfLatencyCertain 497 498 val intConflict = OptionWrapper(intCertainLat, Bool()) 499 val fpConflict = OptionWrapper(fpCertainLat, Bool()) 500 val vfConflict = OptionWrapper(vfCertainLat, Bool()) 501 } 502 503 class ImmInfo extends Bundle { 504 val imm = UInt(32.W) 505 val immType = SelImm() 506 } 507 508 // DataPath --[ExuInput]--> Exu 509 class ExuInput(val params: ExeUnitParams, copyWakeupOut:Boolean = false, copyNum:Int = 0)(implicit p: Parameters) extends XSBundle { 510 val fuType = FuType() 511 val fuOpType = FuOpType() 512 val src = Vec(params.numRegSrc, UInt(params.dataBitsMax.W)) 513 val imm = UInt(32.W) 514 val robIdx = new RobPtr 515 val iqIdx = UInt(log2Up(MemIQSizeMax).W)// Only used by store yet 516 val isFirstIssue = Bool() // Only used by store yet 517 val pdestCopy = OptionWrapper(copyWakeupOut, Vec(copyNum, UInt(params.wbPregIdxWidth.W))) 518 val rfWenCopy = OptionWrapper(copyWakeupOut && params.needIntWen, Vec(copyNum, Bool())) 519 val fpWenCopy = OptionWrapper(copyWakeupOut && params.needFpWen, Vec(copyNum, Bool())) 520 val vecWenCopy = OptionWrapper(copyWakeupOut && params.needVecWen, Vec(copyNum, Bool())) 521 val loadDependencyCopy = OptionWrapper(copyWakeupOut && params.isIQWakeUpSink, Vec(copyNum, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W)))) 522 val pdest = UInt(params.wbPregIdxWidth.W) 523 val rfWen = if (params.needIntWen) Some(Bool()) else None 524 val fpWen = if (params.needFpWen) Some(Bool()) else None 525 val vecWen = if (params.needVecWen) Some(Bool()) else None 526 val fpu = if (params.writeFflags) Some(new FPUCtrlSignals) else None 527 val vpu = if (params.needVPUCtrl) Some(new VPUCtrlSignals) else None 528 val flushPipe = if (params.flushPipe) Some(Bool()) else None 529 val pc = if (params.needPc) Some(UInt(VAddrData().dataWidth.W)) else None 530 val preDecode = if (params.hasPredecode) Some(new PreDecodeInfo) else None 531 val ftqIdx = if (params.needPc || params.replayInst || params.hasStoreAddrFu) 532 Some(new FtqPtr) else None 533 val ftqOffset = if (params.needPc || params.replayInst || params.hasStoreAddrFu) 534 Some(UInt(log2Up(PredictWidth).W)) else None 535 val predictInfo = if (params.needPdInfo) Some(new Bundle { 536 val target = UInt(VAddrData().dataWidth.W) 537 val taken = Bool() 538 }) else None 539 val loadWaitBit = OptionWrapper(params.hasLoadExu, Bool()) 540 val waitForRobIdx = OptionWrapper(params.hasLoadExu, new RobPtr) // store set predicted previous store robIdx 541 val storeSetHit = OptionWrapper(params.hasLoadExu, Bool()) // inst has been allocated an store set 542 val loadWaitStrict = OptionWrapper(params.hasLoadExu, Bool()) // load inst will not be executed until ALL former store addr calcuated 543 val ssid = OptionWrapper(params.hasLoadExu, UInt(SSIDWidth.W)) 544 // only vector load store need 545 val numLsElem = OptionWrapper(params.hasVecLsFu, NumLsElem()) 546 547 val sqIdx = if (params.hasMemAddrFu || params.hasStdFu) Some(new SqPtr) else None 548 val lqIdx = if (params.hasMemAddrFu) Some(new LqPtr) else None 549 val dataSources = Vec(params.numRegSrc, DataSource()) 550 val l1ExuOH = OptionWrapper(params.isIQWakeUpSink, Vec(params.numRegSrc, ExuOH())) 551 val srcTimer = OptionWrapper(params.isIQWakeUpSink, Vec(params.numRegSrc, UInt(3.W))) 552 val loadDependency = OptionWrapper(params.isIQWakeUpSink, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 553 554 val perfDebugInfo = new PerfDebugInfo() 555 556 def exuIdx = this.params.exuIdx 557 558 def needCancel(og0CancelOH: UInt, og1CancelOH: UInt) : Bool = { 559 if (params.isIQWakeUpSink) { 560 require( 561 og0CancelOH.getWidth == l1ExuOH.get.head.getWidth, 562 s"cancelVecSize: {og0: ${og0CancelOH.getWidth}, og1: ${og1CancelOH.getWidth}}" 563 ) 564 val l1Cancel: Bool = l1ExuOH.get.zip(srcTimer.get).map { 565 case(exuOH: UInt, srcTimer: UInt) => 566 (exuOH & og0CancelOH).orR && srcTimer === 1.U 567 }.reduce(_ | _) 568 l1Cancel 569 } else { 570 false.B 571 } 572 } 573 574 def getFpWen = { 575 if (params.writeFpRf) this.fpWen 576 else None 577 } 578 579 def getVfWen = { 580 if(params.writeVecRf) this.vecWen 581 else None 582 } 583 584 def fromIssueBundle(source: IssueQueueIssueBundle): Unit = { 585 // src is assigned to rfReadData 586 this.fuType := source.common.fuType 587 this.fuOpType := source.common.fuOpType 588 this.imm := source.common.imm 589 this.robIdx := source.common.robIdx 590 this.pdest := source.common.pdest 591 this.isFirstIssue := source.common.isFirstIssue // Only used by mem debug log 592 this.iqIdx := source.common.iqIdx // Only used by mem feedback 593 this.dataSources := source.common.dataSources 594 this.l1ExuOH .foreach(_ := source.common.l1ExuOH.get) 595 this.rfWen .foreach(_ := source.common.rfWen.get) 596 this.fpWen .foreach(_ := source.common.fpWen.get) 597 this.vecWen .foreach(_ := source.common.vecWen.get) 598 this.fpu .foreach(_ := source.common.fpu.get) 599 this.vpu .foreach(_ := source.common.vpu.get) 600 this.flushPipe .foreach(_ := source.common.flushPipe.get) 601 this.pc .foreach(_ := source.common.pc.get) 602 this.preDecode .foreach(_ := source.common.preDecode.get) 603 this.ftqIdx .foreach(_ := source.common.ftqIdx.get) 604 this.ftqOffset .foreach(_ := source.common.ftqOffset.get) 605 this.predictInfo .foreach(_ := source.common.predictInfo.get) 606 this.loadWaitBit .foreach(_ := source.common.loadWaitBit.get) 607 this.waitForRobIdx .foreach(_ := source.common.waitForRobIdx.get) 608 this.storeSetHit .foreach(_ := source.common.storeSetHit.get) 609 this.loadWaitStrict.foreach(_ := source.common.loadWaitStrict.get) 610 this.ssid .foreach(_ := source.common.ssid.get) 611 this.lqIdx .foreach(_ := source.common.lqIdx.get) 612 this.sqIdx .foreach(_ := source.common.sqIdx.get) 613 this.numLsElem .foreach(_ := source.common.numLsElem.get) 614 this.srcTimer .foreach(_ := source.common.srcTimer.get) 615 this.loadDependency.foreach(_ := source.common.loadDependency.get.map(_ << 1)) 616 } 617 } 618 619 // ExuInput --[FuncUnit]--> ExuOutput 620 class ExuOutput( 621 val params: ExeUnitParams, 622 )(implicit 623 val p: Parameters 624 ) extends Bundle with BundleSource with HasXSParameter { 625 val data = UInt(params.dataBitsMax.W) 626 val pdest = UInt(params.wbPregIdxWidth.W) 627 val robIdx = new RobPtr 628 val intWen = if (params.needIntWen) Some(Bool()) else None 629 val fpWen = if (params.needFpWen) Some(Bool()) else None 630 val vecWen = if (params.needVecWen) Some(Bool()) else None 631 val redirect = if (params.hasRedirect) Some(ValidIO(new Redirect)) else None 632 val fflags = if (params.writeFflags) Some(UInt(5.W)) else None 633 val wflags = if (params.writeFflags) Some(Bool()) else None 634 val vxsat = if (params.writeVxsat) Some(Bool()) else None 635 val exceptionVec = if (params.exceptionOut.nonEmpty) Some(ExceptionVec()) else None 636 val flushPipe = if (params.flushPipe) Some(Bool()) else None 637 val replay = if (params.replayInst) Some(Bool()) else None 638 val lqIdx = if (params.hasLoadFu) Some(new LqPtr()) else None 639 val sqIdx = if (params.hasStoreAddrFu || params.hasStdFu) 640 Some(new SqPtr()) else None 641 val trigger = if (params.trigger) Some(new TriggerCf) else None 642 // uop info 643 val predecodeInfo = if(params.hasPredecode) Some(new PreDecodeInfo) else None 644 // vldu used only 645 val vls = OptionWrapper(params.hasVLoadFu, new Bundle { 646 val vpu = new VPUCtrlSignals 647 val oldVdPsrc = UInt(PhyRegIdxWidth.W) 648 val vdIdx = UInt(3.W) 649 val vdIdxInField = UInt(3.W) 650 val isIndexed = Bool() 651 val isMasked = Bool() 652 }) 653 val debug = new DebugBundle 654 val debugInfo = new PerfDebugInfo 655 } 656 657 // ExuOutput + DynInst --> WriteBackBundle 658 class WriteBackBundle(val params: PregWB, backendParams: BackendParams)(implicit p: Parameters) extends Bundle with BundleSource { 659 val rfWen = Bool() 660 val fpWen = Bool() 661 val vecWen = Bool() 662 val pdest = UInt(params.pregIdxWidth(backendParams).W) 663 val data = UInt(params.dataWidth.W) 664 val robIdx = new RobPtr()(p) 665 val flushPipe = Bool() 666 val replayInst = Bool() 667 val redirect = ValidIO(new Redirect) 668 val fflags = UInt(5.W) 669 val vxsat = Bool() 670 val exceptionVec = ExceptionVec() 671 val debug = new DebugBundle 672 val debugInfo = new PerfDebugInfo 673 674 this.wakeupSource = s"WB(${params.toString})" 675 676 def fromExuOutput(source: ExuOutput) = { 677 this.rfWen := source.intWen.getOrElse(false.B) 678 this.fpWen := source.fpWen.getOrElse(false.B) 679 this.vecWen := source.vecWen.getOrElse(false.B) 680 this.pdest := source.pdest 681 this.data := source.data 682 this.robIdx := source.robIdx 683 this.flushPipe := source.flushPipe.getOrElse(false.B) 684 this.replayInst := source.replay.getOrElse(false.B) 685 this.redirect := source.redirect.getOrElse(0.U.asTypeOf(this.redirect)) 686 this.fflags := source.fflags.getOrElse(0.U.asTypeOf(this.fflags)) 687 this.vxsat := source.vxsat.getOrElse(0.U.asTypeOf(this.vxsat)) 688 this.exceptionVec := source.exceptionVec.getOrElse(0.U.asTypeOf(this.exceptionVec)) 689 this.debug := source.debug 690 this.debugInfo := source.debugInfo 691 } 692 693 def asIntRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 694 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(IntData()).addrWidth))) 695 rfWrite.wen := this.rfWen && fire 696 rfWrite.addr := this.pdest 697 rfWrite.data := this.data 698 rfWrite.intWen := this.rfWen 699 rfWrite.fpWen := false.B 700 rfWrite.vecWen := false.B 701 rfWrite 702 } 703 704 def asFpRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 705 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(FpData()).addrWidth))) 706 rfWrite.wen := this.fpWen && fire 707 rfWrite.addr := this.pdest 708 rfWrite.data := this.data 709 rfWrite.intWen := false.B 710 rfWrite.fpWen := this.fpWen 711 rfWrite.vecWen := false.B 712 rfWrite 713 } 714 715 def asVfRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 716 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(VecData()).addrWidth))) 717 rfWrite.wen := this.vecWen && fire 718 rfWrite.addr := this.pdest 719 rfWrite.data := this.data 720 rfWrite.intWen := false.B 721 rfWrite.fpWen := false.B 722 rfWrite.vecWen := this.vecWen 723 rfWrite 724 } 725 } 726 727 // ExuOutput --> ExuBypassBundle --[DataPath]-->ExuInput 728 // / 729 // [IssueQueue]--> ExuInput -- 730 class ExuBypassBundle( 731 val params: ExeUnitParams, 732 )(implicit 733 val p: Parameters 734 ) extends Bundle { 735 val data = UInt(params.dataBitsMax.W) 736 val pdest = UInt(params.wbPregIdxWidth.W) 737 } 738 739 class ExceptionInfo(implicit p: Parameters) extends XSBundle { 740 val pc = UInt(VAddrData().dataWidth.W) 741 val instr = UInt(32.W) 742 val commitType = CommitType() 743 val exceptionVec = ExceptionVec() 744 val gpaddr = UInt(GPAddrBits.W) 745 val singleStep = Bool() 746 val crossPageIPFFix = Bool() 747 val isInterrupt = Bool() 748 val isHls = Bool() 749 val vls = Bool() 750 val trigger = new TriggerCf 751 } 752 753 object UopIdx { 754 def apply()(implicit p: Parameters): UInt = UInt(log2Up(p(XSCoreParamsKey).MaxUopSize + 1).W) 755 } 756 757 object FuLatency { 758 def apply(): UInt = UInt(width.W) 759 760 def width = 4 // 0~15 // Todo: assosiate it with FuConfig 761 } 762 763 object ExuOH { 764 def apply(exuNum: Int): UInt = UInt(exuNum.W) 765 766 def apply()(implicit p: Parameters): UInt = UInt(width.W) 767 768 def width(implicit p: Parameters): Int = p(XSCoreParamsKey).backendParams.numExu 769 } 770 771 object ExuVec { 772 def apply(exuNum: Int): Vec[Bool] = Vec(exuNum, Bool()) 773 774 def apply()(implicit p: Parameters): Vec[Bool] = Vec(width, Bool()) 775 776 def width(implicit p: Parameters): Int = p(XSCoreParamsKey).backendParams.numExu 777 } 778 779 class CancelSignal(implicit p: Parameters) extends XSBundle { 780 val rfWen = Bool() 781 val fpWen = Bool() 782 val vecWen = Bool() 783 val pdest = UInt(PhyRegIdxWidth.W) 784 785 def needCancel(srcType: UInt, psrc: UInt, valid: Bool): Bool = { 786 val pdestMatch = pdest === psrc 787 pdestMatch && ( 788 SrcType.isFp(srcType) && !this.rfWen || 789 SrcType.isXp(srcType) && this.rfWen || 790 SrcType.isVp(srcType) && !this.rfWen 791 ) && valid 792 } 793 } 794 795 class MemExuInput(isVector: Boolean = false)(implicit p: Parameters) extends XSBundle { 796 val uop = new DynInst 797 val src = if (isVector) Vec(5, UInt(VLEN.W)) else Vec(3, UInt(XLEN.W)) 798 val iqIdx = UInt(log2Up(MemIQSizeMax).W) 799 val isFirstIssue = Bool() 800 val flowNum = OptionWrapper(isVector, NumLsElem()) 801 802 def src_rs1 = src(0) 803 def src_stride = src(1) 804 def src_vs3 = src(2) 805 def src_mask = if (isVector) src(3) else 0.U 806 def src_vl = if (isVector) src(4) else 0.U 807 } 808 809 class MemExuOutput(isVector: Boolean = false)(implicit p: Parameters) extends XSBundle { 810 val uop = new DynInst 811 val data = if (isVector) UInt(VLEN.W) else UInt(XLEN.W) 812 val mask = if (isVector) Some(UInt(VLEN.W)) else None 813 val vdIdx = if (isVector) Some(UInt(3.W)) else None // TODO: parameterize width 814 val vdIdxInField = if (isVector) Some(UInt(3.W)) else None 815 val debug = new DebugBundle 816 817 def isVls = FuType.isVls(uop.fuType) 818 } 819 820 class MemMicroOpRbExt(implicit p: Parameters) extends XSBundle { 821 val uop = new DynInst 822 val flag = UInt(1.W) 823 } 824 825 object LoadShouldCancel { 826 def apply(loadDependency: Option[Seq[UInt]], ldCancel: Seq[LoadCancelIO]): Bool = { 827 val ld1Cancel = loadDependency.map(_.zip(ldCancel.map(_.ld1Cancel)).map { case (dep, cancel) => cancel && dep(0)}.reduce(_ || _)) 828 val ld2Cancel = loadDependency.map(_.zip(ldCancel.map(_.ld2Cancel)).map { case (dep, cancel) => cancel && dep(1)}.reduce(_ || _)) 829 ld1Cancel.map(_ || ld2Cancel.get).getOrElse(false.B) 830 } 831 } 832} 833