1package xiangshan.backend 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util.BitPat.bitPatToUInt 6import chisel3.util._ 7import xiangshan._ 8import xiangshan.backend.datapath.DataConfig._ 9import xiangshan.backend.datapath.WbConfig.WbConfig 10import xiangshan.backend.decode.{ImmUnion, XDecode} 11import xiangshan.backend.exu.ExeUnitParams 12import xiangshan.backend.fu.FuType 13import xiangshan.backend.fu.fpu.Bundles.Frm 14import xiangshan.backend.fu.vector.Bundles.{Category, Nf, VConfig, VLmul, VSew, VType, Vl, Vxrm} 15import xiangshan.backend.issue.{IssueBlockParams, IssueQueueJumpBundle, SchedulerType, StatusArrayDeqRespBundle, IssueQueueDeqRespBundle} 16import xiangshan.backend.regfile.{RfReadPortWithConfig, RfWritePortWithConfig} 17import xiangshan.backend.rob.RobPtr 18import xiangshan.frontend._ 19import xiangshan.mem.{LqPtr, SqPtr} 20 21object Bundles { 22 23 // frontend -> backend 24 class StaticInst(implicit p: Parameters) extends XSBundle { 25 val instr = UInt(32.W) 26 val pc = UInt(VAddrBits.W) 27 val foldpc = UInt(MemPredPCWidth.W) 28 val exceptionVec = ExceptionVec() 29 val trigger = new TriggerCf 30 val preDecodeInfo = new PreDecodeInfo 31 val pred_taken = Bool() 32 val crossPageIPFFix = Bool() 33 val ftqPtr = new FtqPtr 34 val ftqOffset = UInt(log2Up(PredictWidth).W) 35 36 def connectCtrlFlow(source: CtrlFlow): Unit = { 37 this.instr := source.instr 38 this.pc := source.pc 39 this.foldpc := source.foldpc 40 this.exceptionVec := source.exceptionVec 41 this.trigger := source.trigger 42 this.preDecodeInfo := source.pd 43 this.pred_taken := source.pred_taken 44 this.crossPageIPFFix := source.crossPageIPFFix 45 this.ftqPtr := source.ftqPtr 46 this.ftqOffset := source.ftqOffset 47 } 48 } 49 50 // StaticInst --[Decode]--> DecodedInst 51 class DecodedInst(implicit p: Parameters) extends XSBundle { 52 def numSrc = backendParams.numSrc 53 // passed from StaticInst 54 val instr = UInt(32.W) 55 val pc = UInt(VAddrBits.W) 56 val foldpc = UInt(MemPredPCWidth.W) 57 val exceptionVec = ExceptionVec() 58 val trigger = new TriggerCf 59 val preDecodeInfo = new PreDecodeInfo 60 val pred_taken = Bool() 61 val crossPageIPFFix = Bool() 62 val ftqPtr = new FtqPtr 63 val ftqOffset = UInt(log2Up(PredictWidth).W) 64 // decoded 65 val srcType = Vec(numSrc, SrcType()) 66 val lsrc = Vec(numSrc, UInt(6.W)) 67 val ldest = UInt(6.W) 68 val fuType = FuType() 69 val fuOpType = FuOpType() 70 val rfWen = Bool() 71 val fpWen = Bool() 72 val vecWen = Bool() 73 val isXSTrap = Bool() 74 val waitForward = Bool() // no speculate execution 75 val blockBackward = Bool() 76 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 77 val selImm = SelImm() 78 val imm = UInt(ImmUnion.maxLen.W) 79 val fpu = new FPUCtrlSignals 80 val vpu = new VPUCtrlSignals 81 val isMove = Bool() 82 val uopIdx = UInt(5.W) 83 val uopSplitType = UopSplitType() 84 val isVset = Bool() 85 val firstUop = Bool() 86 val lastUop = Bool() 87 val numUops = UInt(log2Up(MaxUopSize).W) // rob need this 88 val commitType = CommitType() // Todo: remove it 89 90 private def allSignals = srcType.take(3) ++ Seq(fuType, fuOpType, rfWen, fpWen, vecWen, 91 isXSTrap, waitForward, blockBackward, flushPipe, uopSplitType, selImm) 92 93 def decode(inst: UInt, table: Iterable[(BitPat, List[BitPat])]): DecodedInst = { 94 val decoder: Seq[UInt] = ListLookup( 95 inst, XDecode.decodeDefault.map(bitPatToUInt), 96 table.map{ case (pat, pats) => (pat, pats.map(bitPatToUInt)) }.toArray 97 ) 98 allSignals zip decoder foreach { case (s, d) => s := d } 99 this 100 } 101 102 def isSoftPrefetch: Bool = { 103 fuType === FuType.alu.U && fuOpType === ALUOpType.or && selImm === SelImm.IMM_I && ldest === 0.U 104 } 105 106 def connectStaticInst(source: StaticInst): Unit = { 107 for ((name, data) <- this.elements) { 108 if (source.elements.contains(name)) { 109 data := source.elements(name) 110 } 111 } 112 } 113 } 114 115 // DecodedInst --[Rename]--> DynInst 116 class DynInst(implicit p: Parameters) extends XSBundle { 117 def numSrc = backendParams.numSrc 118 // passed from StaticInst 119 val instr = UInt(32.W) 120 val pc = UInt(VAddrBits.W) 121 val foldpc = UInt(MemPredPCWidth.W) 122 val exceptionVec = ExceptionVec() 123 val trigger = new TriggerCf 124 val preDecodeInfo = new PreDecodeInfo 125 val pred_taken = Bool() 126 val crossPageIPFFix = Bool() 127 val ftqPtr = new FtqPtr 128 val ftqOffset = UInt(log2Up(PredictWidth).W) 129 // passed from DecodedInst 130 val srcType = Vec(numSrc, SrcType()) 131 val lsrc = Vec(numSrc, UInt(6.W)) 132 val ldest = UInt(6.W) 133 val fuType = FuType() 134 val fuOpType = FuOpType() 135 val rfWen = Bool() 136 val fpWen = Bool() 137 val vecWen = Bool() 138 val isXSTrap = Bool() 139 val waitForward = Bool() // no speculate execution 140 val blockBackward = Bool() 141 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 142 val selImm = SelImm() 143 val imm = UInt(XLEN.W) // Todo: check if it need minimized 144 val fpu = new FPUCtrlSignals 145 val vpu = new VPUCtrlSignals 146 val isMove = Bool() 147 val uopIdx = UInt(5.W) 148 val isVset = Bool() 149 val firstUop = Bool() 150 val lastUop = Bool() 151 val numUops = UInt(log2Up(MaxUopSize).W) // rob need this 152 val commitType = CommitType() 153 // rename 154 val srcState = Vec(numSrc, SrcState()) 155 val psrc = Vec(numSrc, UInt(PhyRegIdxWidth.W)) 156 val pdest = UInt(PhyRegIdxWidth.W) 157 val oldPdest = UInt(PhyRegIdxWidth.W) 158 val robIdx = new RobPtr 159 160 val eliminatedMove = Bool() 161 val debugInfo = new PerfDebugInfo 162 val storeSetHit = Bool() // inst has been allocated an store set 163 val waitForRobIdx = new RobPtr // store set predicted previous store robIdx 164 // Load wait is needed 165 // load inst will not be executed until former store (predicted by mdp) addr calcuated 166 val loadWaitBit = Bool() 167 // If (loadWaitBit && loadWaitStrict), strict load wait is needed 168 // load inst will not be executed until ALL former store addr calcuated 169 val loadWaitStrict = Bool() 170 val ssid = UInt(SSIDWidth.W) 171 // Todo 172 val lqIdx = new LqPtr 173 val sqIdx = new SqPtr 174 // debug module 175 val singleStep = Bool() 176 // schedule 177 val replayInst = Bool() 178 179 def isLUI: Bool = this.fuType === FuType.alu.U && this.selImm === SelImm.IMM_U 180 def isWFI: Bool = this.fuType === FuType.csr.U && fuOpType === CSROpType.wfi 181 182 def isSvinvalBegin(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && !flush 183 def isSvinval(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.sfence && !flush 184 def isSvinvalEnd(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && flush 185 186 def srcIsReady: Vec[Bool] = { 187 VecInit(this.srcType.zip(this.srcState).map { 188 case (t, s) => SrcType.isNotReg(t) || SrcState.isReady(s) 189 }) 190 } 191 192 def clearExceptions( 193 exceptionBits: Seq[Int] = Seq(), 194 flushPipe : Boolean = false, 195 replayInst : Boolean = false 196 ): DynInst = { 197 this.exceptionVec.zipWithIndex.filterNot(x => exceptionBits.contains(x._2)).foreach(_._1 := false.B) 198 if (!flushPipe) { this.flushPipe := false.B } 199 if (!replayInst) { this.replayInst := false.B } 200 this 201 } 202 203 def asWakeUpBundle: IssueQueueWakeUpBundle = { 204 val wakeup = Output(new IssueQueueWakeUpBundle(pdest.getWidth)) 205 wakeup.rfWen := this.rfWen 206 wakeup.fpWen := this.fpWen 207 wakeup.vecWen := this.vecWen 208 wakeup.pdest := this.pdest 209 wakeup 210 } 211 212 def needWriteRf: Bool = (rfWen && ldest =/= 0.U) || fpWen || vecWen 213 } 214 215 trait BundleSource { 216 var source = "not exist" 217 } 218 219 class IssueQueueWakeUpBundle(PregIdxWidth: Int) extends Bundle with BundleSource { 220 val rfWen = Bool() 221 val fpWen = Bool() 222 val vecWen = Bool() 223 val pdest = UInt(PregIdxWidth.W) 224 225 /** 226 * @param successor Seq[(psrc, srcType)] 227 * @return Seq[if wakeup psrc] 228 */ 229 def wakeUp(successor: Seq[(UInt, UInt)], valid: Bool): Seq[Bool]= { 230 successor.map { case (thatPsrc, srcType) => 231 val pdestMatch = pdest === thatPsrc 232 pdestMatch && ( 233 SrcType.isFp(srcType) && this.fpWen || 234 SrcType.isXp(srcType) && this.rfWen || 235 SrcType.isVp(srcType) && this.vecWen 236 ) && valid 237 } 238 } 239 } 240 241 class VPUCtrlSignals(implicit p: Parameters) extends XSBundle { 242 // vtype 243 val vill = Bool() 244 val vma = Bool() // 1: agnostic, 0: undisturbed 245 val vta = Bool() // 1: agnostic, 0: undisturbed 246 val vsew = VSew() 247 val vlmul = VLmul() // 1/8~8 --> -3~3 248 249 val vm = Bool() // 0: need v0.t 250 val vstart = Vl() 251 252 // float rounding mode 253 val frm = Frm() 254 // vector fix int rounding mode 255 val vxrm = Vxrm() 256 // vector uop index, exclude other non-vector uop 257 val vuopIdx = UopIdx() 258 // maybe used if data dependancy 259 val vmask = UInt(MaskSrcData().dataWidth.W) 260 val vl = Vl() 261 262 // vector load/store 263 val nf = Nf() 264 265 val needScalaSrc = Bool() 266 267 val isReverse = Bool() // vrsub, vrdiv 268 val isExt = Bool() 269 val isNarrow = Bool() 270 val isDstMask = Bool() // vvm, vvvm, mmm 271 val isMove = Bool() // vmv.s.x, vmv.v.v, vmv.v.x, vmv.v.i 272 273 def vtype: VType = { 274 val res = Wire(VType()) 275 res.illegal := this.vill 276 res.vma := this.vma 277 res.vta := this.vta 278 res.vsew := this.vsew 279 res.vlmul := this.vlmul 280 res 281 } 282 283 def vconfig: VConfig = { 284 val res = Wire(VConfig()) 285 res.vtype := this.vtype 286 res.vl := this.vl 287 res 288 } 289 } 290 291 // DynInst --[IssueQueue]--> DataPath 292 class IssueQueueIssueBundle( 293 iqParams: IssueBlockParams, 294 exuParams: ExeUnitParams, 295 addrWidth: Int, 296 vaddrBits: Int 297 )(implicit 298 p: Parameters 299 ) extends Bundle { 300 private val rfReadDataCfgSet: Seq[Set[DataConfig]] = exuParams.getRfReadDataCfgSet 301 302 val rf: MixedVec[MixedVec[RfReadPortWithConfig]] = Flipped(MixedVec( 303 rfReadDataCfgSet.map((set: Set[DataConfig]) => 304 MixedVec(set.map((x: DataConfig) => new RfReadPortWithConfig(x, addrWidth)).toSeq) 305 ) 306 )) 307 val srcType = Vec(exuParams.numRegSrc, SrcType()) // used to select imm or reg data 308 val immType = SelImm() // used to select imm extractor 309 val common = new ExuInput(exuParams) 310 val jmp = if (exuParams.needPc) Some(Flipped(new IssueQueueJumpBundle)) else None 311 val addrOH = UInt(iqParams.numEntries.W) 312 313 def getSource: SchedulerType = exuParams.getWBSource 314 def getIntWbBusyBundle = common.rfWen.toSeq 315 def getVfWbBusyBundle = common.getVfWen.toSeq 316 def getIntRfReadBundle: Seq[RfReadPortWithConfig] = rf.flatten.filter(_.readInt) 317 def getVfRfReadBundle: Seq[RfReadPortWithConfig] = rf.flatten.filter(_.readVf) 318 } 319 320 class OGRespBundle(implicit p:Parameters, params: IssueBlockParams) extends XSBundle { 321 val og0resp = Valid(new StatusArrayDeqRespBundle) 322 val og1resp = Valid(new StatusArrayDeqRespBundle) 323 } 324 325 class fuBusyRespBundle(implicit p: Parameters, params: IssueBlockParams) extends Bundle { 326 val respType = RSFeedbackType() // update credit if needs replay 327 val rfWen = Bool() // TODO: use params to identify IntWB/VfWB 328 val fuType = FuType() 329 } 330 331 class WbFuBusyTableWriteBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 332 val deqResp = Valid(new fuBusyRespBundle) 333 val og0Resp = Valid(new fuBusyRespBundle) 334 val og1Resp = Valid(new fuBusyRespBundle) 335 } 336 337 class WbFuBusyTableReadBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 338 val intWbBusyTable = params.intLatencyValMax match { 339 case Some(latency) => Some(UInt((latency + 1).W)) 340 case None => None 341 } 342 val vfWbBusyTable = params.vfLatencyValMax match { 343 case Some(latency) => Some(UInt((latency + 1).W)) 344 case None => None 345 } 346 } 347 348 class WbConflictBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 349 val intConflict = params.intLatencyValMax match { 350 case Some(latency) => Some(Bool()) 351 case None => None 352 } 353 val vfConflict = params.vfLatencyValMax match { 354 case Some(latency) => Some(Bool()) 355 case None => None 356 } 357 } 358 359 // DataPath --[ExuInput]--> Exu 360 class ExuInput(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 361 val fuType = FuType() 362 val fuOpType = FuOpType() 363 val src = Vec(params.numRegSrc, UInt(params.dataBitsMax.W)) 364 val imm = UInt(XLEN.W) 365 val robIdx = new RobPtr 366 val iqIdx = UInt(log2Up(MemIQSizeMax).W)// Only used by store yet 367 val isFirstIssue = Bool() // Only used by store yet 368 val pdest = UInt(params.wbPregIdxWidth.W) 369 val rfWen = if (params.writeIntRf) Some(Bool()) else None 370 val fpWen = if (params.writeFpRf) Some(Bool()) else None 371 val vecWen = if (params.writeVecRf) Some(Bool()) else None 372 val fpu = if (params.needFPUCtrl) Some(new FPUCtrlSignals) else None 373 val vpu = if (params.needVPUCtrl) Some(new VPUCtrlSignals) else None 374 val flushPipe = if (params.flushPipe) Some(Bool()) else None 375 val pc = if (params.needPc) Some(UInt(VAddrData().dataWidth.W)) else None 376 val jalrTarget = if (params.hasJmpFu) Some(UInt(VAddrData().dataWidth.W)) else None 377 val preDecode = if (params.hasPredecode) Some(new PreDecodeInfo) else None 378 val ftqIdx = if (params.needPc || params.replayInst) 379 Some(new FtqPtr) else None 380 val ftqOffset = if (params.needPc || params.replayInst) 381 Some(UInt(log2Up(PredictWidth).W)) else None 382 val predictInfo = if (params.hasPredecode) Some(new Bundle { 383 val target = UInt(VAddrData().dataWidth.W) 384 val taken = Bool() 385 }) else None 386 val sqIdx = if (params.hasMemAddrFu || params.hasStdFu) Some(new SqPtr) else None 387 val lqIdx = if (params.hasMemAddrFu) Some(new LqPtr) else None 388 389 def getVfWen = { 390 if (params.writeFpRf) this.fpWen 391 else if(params.writeVecRf) this.vecWen 392 else None 393 } 394 395 def fromIssueBundle(source: IssueQueueIssueBundle): Unit = { 396 // src is assigned to rfReadData 397 this.fuType := source.common.fuType 398 this.fuOpType := source.common.fuOpType 399 this.imm := source.common.imm 400 this.robIdx := source.common.robIdx 401 this.pdest := source.common.pdest 402 this.isFirstIssue := source.common.isFirstIssue // Only used by mem debug log 403 this.iqIdx := source.common.iqIdx // Only used by mem feedback 404 this.rfWen .foreach(_ := source.common.rfWen.get) 405 this.fpWen .foreach(_ := source.common.fpWen.get) 406 this.vecWen .foreach(_ := source.common.vecWen.get) 407 this.fpu .foreach(_ := source.common.fpu.get) 408 this.vpu .foreach(_ := source.common.vpu.get) 409 this.flushPipe .foreach(_ := source.common.flushPipe.get) 410 this.pc .foreach(_ := source.jmp.get.pc) 411 this.jalrTarget .foreach(_ := source.jmp.get.target) 412 this.preDecode .foreach(_ := source.common.preDecode.get) 413 this.ftqIdx .foreach(_ := source.common.ftqIdx.get) 414 this.ftqOffset .foreach(_ := source.common.ftqOffset.get) 415 this.predictInfo .foreach(_ := source.common.predictInfo.get) 416 this.lqIdx .foreach(_ := source.common.lqIdx.get) 417 this.sqIdx .foreach(_ := source.common.sqIdx.get) 418 } 419 } 420 421 // ExuInput --[FuncUnit]--> ExuOutput 422 class ExuOutput( 423 val params: ExeUnitParams, 424 )(implicit 425 val p: Parameters 426 ) extends Bundle with BundleSource with HasXSParameter { 427 val data = UInt(params.dataBitsMax.W) 428 val pdest = UInt(params.wbPregIdxWidth.W) 429 val robIdx = new RobPtr 430 val intWen = if (params.writeIntRf) Some(Bool()) else None 431 val fpWen = if (params.writeFpRf) Some(Bool()) else None 432 val vecWen = if (params.writeVecRf) Some(Bool()) else None 433 val redirect = if (params.hasRedirect) Some(ValidIO(new Redirect)) else None 434 val fflags = if (params.writeFflags) Some(UInt(5.W)) else None 435 val vxsat = if (params.writeVxsat) Some(Bool()) else None 436 val exceptionVec = if (params.exceptionOut.nonEmpty) Some(ExceptionVec()) else None 437 val flushPipe = if (params.flushPipe) Some(Bool()) else None 438 val replay = if (params.replayInst) Some(Bool()) else None 439 val lqIdx = if (params.hasLoadFu) Some(new LqPtr()) else None 440 val sqIdx = if (params.hasStoreAddrFu || params.hasStdFu) 441 Some(new SqPtr()) else None 442 val ftqIdx = if (params.needPc || params.replayInst) 443 Some(new FtqPtr) else None 444 val ftqOffset = if (params.needPc || params.replayInst) 445 Some(UInt(log2Up(PredictWidth).W)) else None 446 // uop info 447 val predecodeInfo = if(params.hasPredecode) Some(new PreDecodeInfo) else None 448 val debug = new DebugBundle 449 val debugInfo = new PerfDebugInfo 450 } 451 452 // ExuOutput + DynInst --> WriteBackBundle 453 class WriteBackBundle(val params: WbConfig)(implicit p: Parameters) extends Bundle with BundleSource { 454 val rfWen = Bool() 455 val fpWen = Bool() 456 val vecWen = Bool() 457 val pdest = UInt(params.pregIdxWidth.W) 458 val data = UInt(params.dataWidth.W) 459 val robIdx = new RobPtr()(p) 460 val flushPipe = Bool() 461 val replayInst = Bool() 462 val redirect = ValidIO(new Redirect) 463 val fflags = UInt(5.W) 464 val vxsat = Bool() 465 val exceptionVec = ExceptionVec() 466 val debug = new DebugBundle 467 val debugInfo = new PerfDebugInfo 468 469 def fromExuOutput(source: ExuOutput) = { 470 this.rfWen := source.intWen.getOrElse(false.B) 471 this.fpWen := source.fpWen.getOrElse(false.B) 472 this.vecWen := source.vecWen.getOrElse(false.B) 473 this.pdest := source.pdest 474 this.data := source.data 475 this.robIdx := source.robIdx 476 this.flushPipe := source.flushPipe.getOrElse(false.B) 477 this.replayInst := source.replay.getOrElse(false.B) 478 this.redirect := source.redirect.getOrElse(0.U.asTypeOf(this.redirect)) 479 this.fflags := source.fflags.getOrElse(0.U.asTypeOf(this.fflags)) 480 this.vxsat := source.vxsat.getOrElse(0.U.asTypeOf(this.vxsat)) 481 this.exceptionVec := source.exceptionVec.getOrElse(0.U.asTypeOf(this.exceptionVec)) 482 this.debug := source.debug 483 this.debugInfo := source.debugInfo 484 } 485 486 def asWakeUpBundle: IssueQueueWakeUpBundle = { 487 val wakeup = Output(new IssueQueueWakeUpBundle(params.pregIdxWidth)) 488 wakeup.rfWen := this.rfWen 489 wakeup.fpWen := this.fpWen 490 wakeup.vecWen := this.vecWen 491 wakeup.pdest := this.pdest 492 wakeup.source = this.source 493 wakeup 494 } 495 496 def asIntRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 497 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, this.params.pregIdxWidth))) 498 rfWrite.wen := this.rfWen && fire 499 rfWrite.addr := this.pdest 500 rfWrite.data := this.data 501 rfWrite.intWen := this.rfWen 502 rfWrite.fpWen := false.B 503 rfWrite.vecWen := false.B 504 rfWrite 505 } 506 507 def asVfRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 508 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, this.params.pregIdxWidth))) 509 rfWrite.wen := (this.fpWen || this.vecWen) && fire 510 rfWrite.addr := this.pdest 511 rfWrite.data := this.data 512 rfWrite.intWen := false.B 513 rfWrite.fpWen := this.fpWen 514 rfWrite.vecWen := this.vecWen 515 rfWrite 516 } 517 } 518 519 class ExceptionInfo extends Bundle { 520 val pc = UInt(VAddrData().dataWidth.W) 521 val instr = UInt(32.W) 522 val commitType = CommitType() 523 val exceptionVec = ExceptionVec() 524 val singleStep = Bool() 525 val crossPageIPFFix = Bool() 526 val isInterrupt = Bool() 527 } 528 529 object UopIdx { 530 def apply()(implicit p: Parameters): UInt = UInt(log2Up(p(XSCoreParamsKey).MaxUopSize + 1).W) 531 } 532 533 class MemExuInput(isVector: Boolean = false)(implicit p: Parameters) extends XSBundle { 534 val uop = new DynInst 535 val src = if (isVector) Vec(5, UInt(VLEN.W)) else Vec(3, UInt(XLEN.W)) 536 val iqIdx = UInt(log2Up(MemIQSizeMax).W) 537 val isFirstIssue = Bool() 538 } 539 540 class MemExuOutput(isVector: Boolean = false)(implicit p: Parameters) extends XSBundle { 541 val uop = new DynInst 542 val data = if (isVector) UInt(VLEN.W) else UInt(XLEN.W) 543 val debug = new DebugBundle 544 } 545 546 class MemMicroOpRbExt(implicit p: Parameters) extends XSBundle { 547 val uop = new DynInst 548 val flag = UInt(1.W) 549 } 550} 551