1package xiangshan.backend 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util.BitPat.bitPatToUInt 6import chisel3.util._ 7import xiangshan._ 8import xiangshan.backend.datapath.DataConfig._ 9import xiangshan.backend.datapath.WbConfig.WbConfig 10import xiangshan.backend.decode.{ImmUnion, XDecode} 11import xiangshan.backend.exu.ExeUnitParams 12import xiangshan.backend.fu.FuType 13import xiangshan.backend.issue.{IssueBlockParams, IssueQueueJumpBundle, SchedulerType, StatusArrayDeqRespBundle} 14import xiangshan.backend.regfile.{RfReadPortWithConfig, RfWritePortWithConfig} 15import xiangshan.backend.rob.RobPtr 16import xiangshan.frontend._ 17import xiangshan.mem.{LqPtr, SqPtr} 18 19object Bundles { 20 21 // frontend -> backend 22 class StaticInst(implicit p: Parameters) extends XSBundle { 23 val instr = UInt(32.W) 24 val pc = UInt(VAddrBits.W) 25 val foldpc = UInt(MemPredPCWidth.W) 26 val exceptionVec = ExceptionVec() 27 val trigger = new TriggerCf 28 val preDecodeInfo = new PreDecodeInfo 29 val pred_taken = Bool() 30 val crossPageIPFFix = Bool() 31 val ftqPtr = new FtqPtr 32 val ftqOffset = UInt(log2Up(PredictWidth).W) 33 34 def connectCtrlFlow(source: CtrlFlow): Unit = { 35 this.instr := source.instr 36 this.pc := source.pc 37 this.foldpc := source.foldpc 38 this.exceptionVec := source.exceptionVec 39 this.trigger := source.trigger 40 this.preDecodeInfo := source.pd 41 this.pred_taken := source.pred_taken 42 this.crossPageIPFFix := source.crossPageIPFFix 43 this.ftqPtr := source.ftqPtr 44 this.ftqOffset := source.ftqOffset 45 } 46 } 47 48 // StaticInst --[Decode]--> DecodedInst 49 class DecodedInst(implicit p: Parameters) extends XSBundle { 50 def numPSrc = 5 51 def numLSrc = 3 52 // passed from StaticInst 53 val instr = UInt(32.W) 54 val pc = UInt(VAddrBits.W) 55 val foldpc = UInt(MemPredPCWidth.W) 56 val exceptionVec = ExceptionVec() 57 val trigger = new TriggerCf 58 val preDecodeInfo = new PreDecodeInfo 59 val pred_taken = Bool() 60 val crossPageIPFFix = Bool() 61 val ftqPtr = new FtqPtr 62 val ftqOffset = UInt(log2Up(PredictWidth).W) 63 // decoded 64 val srcType = Vec(numLSrc, SrcType()) 65 val lsrc = Vec(numLSrc, UInt(6.W)) 66 val ldest = UInt(6.W) 67 val fuType = FuType() 68 val fuOpType = FuOpType() 69 val rfWen = Bool() 70 val fpWen = Bool() 71 val vecWen = Bool() 72 val isXSTrap = Bool() 73 val waitForward = Bool() // no speculate execution 74 val blockBackward = Bool() 75 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 76 val selImm = SelImm() 77 val imm = UInt(ImmUnion.maxLen.W) 78 val fpu = new FPUCtrlSignals 79 val vpu = new VPUCtrlSignals 80 val isMove = Bool() 81 val uopIdx = UInt(5.W) 82 // val vconfig = UInt(16.W) 83 val isVset = Bool() 84 val commitType = CommitType() // Todo: remove it 85 86 val debug_globalID = UInt(XLEN.W) // Todo: rename it 87 private def allSignals = srcType.take(3) ++ Seq(fuType, fuOpType, rfWen, fpWen, vecWen, 88 isXSTrap, waitForward, blockBackward, flushPipe, selImm) 89 90 def decode(inst: UInt, table: Iterable[(BitPat, List[BitPat])]): DecodedInst = { 91 val decoder: Seq[UInt] = ListLookup( 92 inst, XDecode.decodeDefault.map(bitPatToUInt), 93 table.map{ case (pat, pats) => (pat, pats.map(bitPatToUInt)) }.toArray 94 ) 95 allSignals zip decoder foreach { case (s, d) => s := d } 96 this 97 } 98 99 def isSoftPrefetch: Bool = { 100 fuType === FuType.alu.U && fuOpType === ALUOpType.or && selImm === SelImm.IMM_I && ldest === 0.U 101 } 102 103 def connectStaticInst(source: StaticInst): Unit = { 104 for ((name, data) <- this.elements) { 105 if (source.elements.contains(name)) { 106 data := source.elements(name) 107 } 108 } 109 } 110 } 111 112 // DecodedInst --[Rename]--> DynInst 113 class DynInst(implicit p: Parameters) extends XSBundle { 114 def numLSrc = 3 115 // vector inst need vs1, vs2, vd, v0, vl&vtype, 5 psrcs 116 def numPSrc = 5 117 // passed from StaticInst 118 val instr = UInt(32.W) 119 val pc = UInt(VAddrBits.W) 120 val foldpc = UInt(MemPredPCWidth.W) 121 val exceptionVec = ExceptionVec() 122 val trigger = new TriggerCf 123 val preDecodeInfo = new PreDecodeInfo 124 val pred_taken = Bool() 125 val crossPageIPFFix = Bool() 126 val ftqPtr = new FtqPtr 127 val ftqOffset = UInt(log2Up(PredictWidth).W) 128 // passed from DecodedInst 129 val srcType = Vec(numLSrc, SrcType()) 130 val lsrc = Vec(numLSrc, UInt(6.W)) 131 val ldest = UInt(6.W) 132 val fuType = FuType() 133 val fuOpType = FuOpType() 134 val rfWen = Bool() 135 val fpWen = Bool() 136 val vecWen = Bool() 137 val isXSTrap = Bool() 138 val waitForward = Bool() // no speculate execution 139 val blockBackward = Bool() 140 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 141 val selImm = SelImm() 142 val imm = UInt(XLEN.W) // Todo: check if it need minimized 143 val fpu = new FPUCtrlSignals 144 val vpu = new VPUCtrlSignals 145 val isMove = Bool() 146 val uopIdx = UInt(5.W) 147 // val vconfig = UInt(16.W) 148 val isVset = Bool() 149 val commitType = CommitType() 150 // rename 151 val srcState = Vec(numPSrc, SrcState()) 152 val psrc = Vec(numPSrc, UInt(PhyRegIdxWidth.W)) 153 val pdest = UInt(PhyRegIdxWidth.W) 154 val oldPdest = UInt(PhyRegIdxWidth.W) 155 val robIdx = new RobPtr 156 157 val eliminatedMove = Bool() 158 val debugInfo = new PerfDebugInfo 159 val storeSetHit = Bool() // inst has been allocated an store set 160 val waitForRobIdx = new RobPtr // store set predicted previous store robIdx 161 // Load wait is needed 162 // load inst will not be executed until former store (predicted by mdp) addr calcuated 163 val loadWaitBit = Bool() 164 // If (loadWaitBit && loadWaitStrict), strict load wait is needed 165 // load inst will not be executed until ALL former store addr calcuated 166 val loadWaitStrict = Bool() 167 val ssid = UInt(SSIDWidth.W) 168 // Todo 169 val lqIdx = new LqPtr 170 val sqIdx = new SqPtr 171 // debug module 172 val singleStep = Bool() 173 // schedule 174 val replayInst = Bool() 175 176 def isLUI: Bool = this.fuType === FuType.alu.U && this.selImm === SelImm.IMM_U 177 def isWFI: Bool = this.fuType === FuType.csr.U && fuOpType === CSROpType.wfi 178 179 def isSvinvalBegin(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && !flush 180 def isSvinval(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.sfence && !flush 181 def isSvinvalEnd(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && flush 182 183 def srcIsReady: Vec[Bool] = { 184 VecInit(this.srcType.zip(this.srcState).map { 185 case (t, s) => SrcType.isNotReg(t) || SrcState.isReady(s) 186 }) 187 } 188 189 def clearExceptions( 190 exceptionBits: Seq[Int] = Seq(), 191 flushPipe : Boolean = false, 192 replayInst : Boolean = false 193 ): DynInst = { 194 this.exceptionVec.zipWithIndex.filterNot(x => exceptionBits.contains(x._2)).foreach(_._1 := false.B) 195 if (!flushPipe) { this.flushPipe := false.B } 196 if (!replayInst) { this.replayInst := false.B } 197 this 198 } 199 200 def asWakeUpBundle: IssueQueueWakeUpBundle = { 201 val wakeup = Output(new IssueQueueWakeUpBundle(pdest.getWidth)) 202 wakeup.rfWen := this.rfWen 203 wakeup.fpWen := this.fpWen 204 wakeup.vecWen := this.vecWen 205 wakeup.pdest := this.pdest 206 wakeup 207 } 208 } 209 210 trait BundleSource { 211 var source = "not exist" 212 } 213 214 class IssueQueueWakeUpBundle(PregIdxWidth: Int) extends Bundle with BundleSource { 215 val rfWen = Bool() 216 val fpWen = Bool() 217 val vecWen = Bool() 218 val pdest = UInt(PregIdxWidth.W) 219 220 /** 221 * @param successor Seq[(psrc, srcType)] 222 * @return Seq[if wakeup psrc] 223 */ 224 def wakeUp(successor: Seq[(UInt, UInt)], valid: Bool): Seq[Bool]= { 225 successor.map { case (thatPsrc, srcType) => 226 val pdestMatch = pdest === thatPsrc 227 pdestMatch && ( 228 SrcType.isFp(srcType) && this.fpWen || 229 SrcType.isXp(srcType) && this.rfWen || 230 SrcType.isVp(srcType) && this.vecWen 231 ) && valid 232 } 233 } 234 } 235 236 object VsewBundle { 237 def apply() = UInt(2.W) // 8/16/32/64 --> 0/1/2/3 238 } 239 240 class VPUCtrlSignals(implicit p: Parameters) extends XSBundle { 241 val vlmul = SInt(3.W) // 1/8~8 --> -3~3 242 val vsew = VsewBundle() 243 val vta = Bool() // 1: agnostic, 0: undisturbed 244 val vma = Bool() // 1: agnostic, 0: undisturbed 245 val vm = Bool() // 0: need v0.t 246 val vill = Bool() 247 // vector load/store 248 val nf = UInt(3.W) 249 val lsumop = UInt(5.W) // lumop or sumop 250 // used for vector index load/store and vrgatherei16.vv 251 val idxEmul = UInt(3.W) 252 } 253 254 // DynInst --[IssueQueue]--> DataPath 255 class IssueQueueIssueBundle( 256 iqParams: IssueBlockParams, 257 exuParams: ExeUnitParams, 258 addrWidth: Int, 259 vaddrBits: Int 260 )(implicit 261 p: Parameters 262 ) extends Bundle { 263 private val rfReadDataCfgSet: Seq[Set[DataConfig]] = exuParams.getRfReadDataCfgSet 264 265 val rf: MixedVec[MixedVec[RfReadPortWithConfig]] = Flipped(MixedVec( 266 rfReadDataCfgSet.map((set: Set[DataConfig]) => 267 MixedVec(set.map((x: DataConfig) => new RfReadPortWithConfig(x, addrWidth)).toSeq) 268 ) 269 )) 270 val srcType = Vec(exuParams.numRegSrc, SrcType()) // used to select imm or reg data 271 val immType = SelImm() // used to select imm extractor 272 val common = new ExuInput(exuParams) 273 val jmp = if (exuParams.needPc) Some(Flipped(new IssueQueueJumpBundle)) else None 274 val addrOH = UInt(iqParams.numEntries.W) 275 276 def getSource: SchedulerType = exuParams.getWBSource 277 def getIntRfReadBundle: Seq[RfReadPortWithConfig] = rf.flatten.filter(_.readInt) 278 def getFpRfReadBundle: Seq[RfReadPortWithConfig] = rf.flatten.filter(_.readFp) 279 } 280 281 class OGRespBundle(implicit p:Parameters, params: IssueBlockParams) extends XSBundle { 282 val og0resp = Valid(new StatusArrayDeqRespBundle) 283 val og1resp = Valid(new StatusArrayDeqRespBundle) 284 } 285 286 // DataPath --[ExuInput]--> Exu 287 class ExuInput(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 288 val fuType = FuType() 289 val fuOpType = FuOpType() 290 val src = Vec(params.numRegSrc, UInt(params.dataBitsMax.W)) 291 val imm = UInt(XLEN.W) 292 val robIdx = new RobPtr 293 val iqIdx = UInt(log2Up(MemIQSizeMax).W)// Only used by store yet 294 val isFirstIssue = Bool() // Only used by store yet 295 val pdest = UInt(params.wbPregIdxWidth.W) 296 val rfWen = if (params.writeIntRf) Some(Bool()) else None 297 val fpWen = if (params.writeFpRf) Some(Bool()) else None 298 val vecWen = if (params.writeVecRf) Some(Bool()) else None 299 val fpu = if (params.needFPUCtrl) Some(new FPUCtrlSignals) else None 300 val flushPipe = if (params.flushPipe) Some(Bool()) else None 301 val pc = if (params.needPc) Some(UInt(VAddrData().dataWidth.W)) else None 302 val jalrTarget = if (params.hasJmpFu) Some(UInt(VAddrData().dataWidth.W)) else None 303 val preDecode = if (params.hasPredecode) Some(new PreDecodeInfo) else None 304 val ftqIdx = if (params.needPc || params.replayInst) 305 Some(new FtqPtr) else None 306 val ftqOffset = if (params.needPc || params.replayInst) 307 Some(UInt(log2Up(PredictWidth).W)) else None 308 val predictInfo = if (params.hasPredecode) Some(new Bundle { 309 val target = UInt(VAddrData().dataWidth.W) 310 val taken = Bool() 311 }) else None 312 val sqIdx = if (params.hasMemAddrFu || params.hasStdFu) Some(new SqPtr) else None 313 val lqIdx = if (params.hasMemAddrFu) Some(new LqPtr) else None 314 315 def fromIssueBundle(source: IssueQueueIssueBundle): Unit = { 316 // src is assigned to rfReadData 317 this.fuType := source.common.fuType 318 this.fuOpType := source.common.fuOpType 319 this.imm := source.common.imm 320 this.robIdx := source.common.robIdx 321 this.pdest := source.common.pdest 322 this.isFirstIssue := source.common.isFirstIssue // Only used by mem debug log 323 this.iqIdx := source.common.iqIdx // Only used by mem feedback 324 this.rfWen .foreach(_ := source.common.rfWen.get) 325 this.fpWen .foreach(_ := source.common.fpWen.get) 326 this.vecWen .foreach(_ := source.common.vecWen.get) 327 this.fpu .foreach(_ := source.common.fpu.get) 328 this.flushPipe .foreach(_ := source.common.flushPipe.get) 329 this.pc .foreach(_ := source.jmp.get.pc) 330 this.jalrTarget .foreach(_ := source.jmp.get.target) 331 this.preDecode .foreach(_ := source.common.preDecode.get) 332 this.ftqIdx .foreach(_ := source.common.ftqIdx.get) 333 this.ftqOffset .foreach(_ := source.common.ftqOffset.get) 334 this.predictInfo .foreach(_ := source.common.predictInfo.get) 335 this.lqIdx .foreach(_ := source.common.lqIdx.get) 336 this.sqIdx .foreach(_ := source.common.sqIdx.get) 337 } 338 } 339 340 // ExuInput --[FuncUnit]--> ExuOutput 341 class ExuOutput( 342 val params: ExeUnitParams, 343 )(implicit 344 val p: Parameters 345 ) extends Bundle with BundleSource with HasXSParameter { 346 val data = UInt(params.dataBitsMax.W) 347 val pdest = UInt(params.wbPregIdxWidth.W) 348 val robIdx = new RobPtr 349 val intWen = if (params.writeIntRf) Some(Bool()) else None 350 val fpWen = if (params.writeFpRf) Some(Bool()) else None 351 val vecWen = if (params.writeVecRf) Some(Bool()) else None 352 val redirect = if (params.hasRedirect) Some(ValidIO(new Redirect)) else None 353 val fflags = if (params.writeFflags) Some(UInt(5.W)) else None 354 val exceptionVec = if (params.exceptionOut.nonEmpty) Some(ExceptionVec()) else None 355 val flushPipe = if (params.flushPipe) Some(Bool()) else None 356 val replay = if (params.replayInst) Some(Bool()) else None 357 val lqIdx = if (params.hasLoadFu) Some(new LqPtr()) else None 358 val sqIdx = if (params.hasStoreAddrFu || params.hasStdFu) 359 Some(new SqPtr()) else None 360 val ftqIdx = if (params.needPc || params.replayInst) 361 Some(new FtqPtr) else None 362 val ftqOffset = if (params.needPc || params.replayInst) 363 Some(UInt(log2Up(PredictWidth).W)) else None 364 // uop info 365 val predecodeInfo = if(params.hasPredecode) Some(new PreDecodeInfo) else None 366 val debug = new DebugBundle 367 val debugInfo = new PerfDebugInfo 368 } 369 370 // ExuOutput + DynInst --> WriteBackBundle 371 class WriteBackBundle(val params: WbConfig)(implicit p: Parameters) extends Bundle with BundleSource { 372 val rfWen = Bool() 373 val fpWen = Bool() 374 val vecWen = Bool() 375 val pdest = UInt(params.pregIdxWidth.W) 376 val data = UInt(params.dataWidth.W) 377 val robIdx = new RobPtr()(p) 378 val flushPipe = Bool() 379 val replayInst = Bool() 380 val redirect = ValidIO(new Redirect) 381 val fflags = UInt(5.W) 382 val exceptionVec = ExceptionVec() 383 val debug = new DebugBundle 384 val debugInfo = new PerfDebugInfo 385 386 def fromExuOutput(source: ExuOutput) = { 387 this.rfWen := source.intWen.getOrElse(false.B) 388 this.fpWen := source.fpWen.getOrElse(false.B) 389 this.vecWen := source.vecWen.getOrElse(false.B) 390 this.pdest := source.pdest 391 this.data := source.data 392 this.robIdx := source.robIdx 393 this.flushPipe := source.flushPipe.getOrElse(false.B) 394 this.replayInst := source.replay.getOrElse(false.B) 395 this.redirect := source.redirect.getOrElse(0.U.asTypeOf(this.redirect)) 396 this.fflags := source.fflags.getOrElse(0.U.asTypeOf(this.fflags)) 397 this.exceptionVec := source.exceptionVec.getOrElse(0.U.asTypeOf(this.exceptionVec)) 398 this.debug := source.debug 399 this.debugInfo := source.debugInfo 400 } 401 402 def asWakeUpBundle: IssueQueueWakeUpBundle = { 403 val wakeup = Output(new IssueQueueWakeUpBundle(params.pregIdxWidth)) 404 wakeup.rfWen := this.rfWen 405 wakeup.fpWen := this.fpWen 406 wakeup.vecWen := this.vecWen 407 wakeup.pdest := this.pdest 408 wakeup.source = this.source 409 wakeup 410 } 411 412 def asIntRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 413 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, this.params.pregIdxWidth))) 414 rfWrite.wen := this.rfWen && fire 415 rfWrite.addr := this.pdest 416 rfWrite.data := this.data 417 rfWrite.intWen := this.rfWen 418 rfWrite.fpWen := false.B 419 rfWrite.vecWen := false.B 420 rfWrite 421 } 422 423 def asVfRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 424 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, this.params.pregIdxWidth))) 425 rfWrite.wen := (this.fpWen || this.vecWen) && fire 426 rfWrite.addr := this.pdest 427 rfWrite.data := this.data 428 rfWrite.intWen := false.B 429 rfWrite.fpWen := this.fpWen 430 rfWrite.vecWen := this.vecWen 431 rfWrite 432 } 433 } 434 435 class ExceptionInfo extends Bundle { 436 val pc = UInt(VAddrData().dataWidth.W) 437 val instr = UInt(32.W) 438 val commitType = CommitType() 439 val exceptionVec = ExceptionVec() 440 val singleStep = Bool() 441 val crossPageIPFFix = Bool() 442 val isInterrupt = Bool() 443 } 444 445 class MemExuInput(implicit p: Parameters) extends XSBundle { 446 val uop = new DynInst 447 val src = Vec(3, UInt(XLEN.W)) 448 val iqIdx = UInt(log2Up(MemIQSizeMax).W) 449 val isFirstIssue = Bool() 450 } 451 452 class MemExuOutput(implicit p: Parameters) extends XSBundle { 453 val uop = new DynInst 454 val data = UInt(XLEN.W) 455 val debug = new DebugBundle 456 } 457 458 class MemMicroOpRbExt(implicit p: Parameters) extends XSBundle { 459 val uop = new DynInst 460 val flag = UInt(1.W) 461 } 462} 463