1package xiangshan.backend 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util.BitPat.bitPatToUInt 6import chisel3.util._ 7import utils.BundleUtils.makeValid 8import utils.OptionWrapper 9import xiangshan._ 10import xiangshan.backend.datapath.DataConfig._ 11import xiangshan.backend.datapath.DataSource 12import xiangshan.backend.datapath.WbConfig.PregWB 13import xiangshan.backend.decode.{ImmUnion, XDecode} 14import xiangshan.backend.exu.ExeUnitParams 15import xiangshan.backend.fu.FuType 16import xiangshan.backend.fu.fpu.Bundles.Frm 17import xiangshan.backend.fu.vector.Bundles._ 18import xiangshan.backend.issue.{IssueBlockParams, IssueQueueDeqRespBundle, SchedulerType} 19import xiangshan.backend.issue.EntryBundles._ 20import xiangshan.backend.regfile.{RfReadPortWithConfig, RfWritePortWithConfig} 21import xiangshan.backend.rob.RobPtr 22import xiangshan.frontend._ 23import xiangshan.mem.{LqPtr, SqPtr} 24import yunsuan.vector.VIFuParam 25 26object Bundles { 27 /** 28 * Connect Same Name Port like bundleSource := bundleSinkBudle. 29 * 30 * There is no limit to the number of ports on both sides. 31 * 32 * Don't forget to connect the remaining ports! 33 */ 34 def connectSamePort (bundleSource: Bundle, bundleSink: Bundle):Unit = { 35 bundleSource.elements.foreach { case (name, data) => 36 if (bundleSink.elements.contains(name)) 37 data := bundleSink.elements(name) 38 } 39 } 40 // frontend -> backend 41 class StaticInst(implicit p: Parameters) extends XSBundle { 42 val instr = UInt(32.W) 43 val pc = UInt(VAddrBits.W) 44 val foldpc = UInt(MemPredPCWidth.W) 45 val exceptionVec = ExceptionVec() 46 val trigger = new TriggerCf 47 val preDecodeInfo = new PreDecodeInfo 48 val pred_taken = Bool() 49 val crossPageIPFFix = Bool() 50 val ftqPtr = new FtqPtr 51 val ftqOffset = UInt(log2Up(PredictWidth).W) 52 53 def connectCtrlFlow(source: CtrlFlow): Unit = { 54 this.instr := source.instr 55 this.pc := source.pc 56 this.foldpc := source.foldpc 57 this.exceptionVec := source.exceptionVec 58 this.trigger := source.trigger 59 this.preDecodeInfo := source.pd 60 this.pred_taken := source.pred_taken 61 this.crossPageIPFFix := source.crossPageIPFFix 62 this.ftqPtr := source.ftqPtr 63 this.ftqOffset := source.ftqOffset 64 } 65 } 66 67 // StaticInst --[Decode]--> DecodedInst 68 class DecodedInst(implicit p: Parameters) extends XSBundle { 69 def numSrc = backendParams.numSrc 70 // passed from StaticInst 71 val instr = UInt(32.W) 72 val pc = UInt(VAddrBits.W) 73 val foldpc = UInt(MemPredPCWidth.W) 74 val exceptionVec = ExceptionVec() 75 val trigger = new TriggerCf 76 val preDecodeInfo = new PreDecodeInfo 77 val pred_taken = Bool() 78 val crossPageIPFFix = Bool() 79 val ftqPtr = new FtqPtr 80 val ftqOffset = UInt(log2Up(PredictWidth).W) 81 // decoded 82 val srcType = Vec(numSrc, SrcType()) 83 val lsrc = Vec(numSrc, UInt(LogicRegsWidth.W)) 84 val ldest = UInt(LogicRegsWidth.W) 85 val fuType = FuType() 86 val fuOpType = FuOpType() 87 val rfWen = Bool() 88 val fpWen = Bool() 89 val vecWen = Bool() 90 val v0Wen = Bool() 91 val vlWen = Bool() 92 val isXSTrap = Bool() 93 val waitForward = Bool() // no speculate execution 94 val blockBackward = Bool() 95 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 96 val canRobCompress = Bool() 97 val selImm = SelImm() 98 val imm = UInt(ImmUnion.maxLen.W) 99 val fpu = new FPUCtrlSignals 100 val vpu = new VPUCtrlSignals 101 val vlsInstr = Bool() 102 val wfflags = Bool() 103 val isMove = Bool() 104 val uopIdx = UopIdx() 105 val uopSplitType = UopSplitType() 106 val isVset = Bool() 107 val firstUop = Bool() 108 val lastUop = Bool() 109 val numUops = UInt(log2Up(MaxUopSize).W) // rob need this 110 val numWB = UInt(log2Up(MaxUopSize).W) // rob need this 111 val commitType = CommitType() // Todo: remove it 112 113 val debug_fuType = OptionWrapper(backendParams.debugEn, FuType()) 114 115 private def allSignals = srcType.take(3) ++ Seq(fuType, fuOpType, rfWen, fpWen, vecWen, 116 isXSTrap, waitForward, blockBackward, flushPipe, canRobCompress, uopSplitType, selImm) 117 118 def decode(inst: UInt, table: Iterable[(BitPat, List[BitPat])]): DecodedInst = { 119 val decoder: Seq[UInt] = ListLookup( 120 inst, XDecode.decodeDefault.map(bitPatToUInt), 121 table.map{ case (pat, pats) => (pat, pats.map(bitPatToUInt)) }.toArray 122 ) 123 allSignals zip decoder foreach { case (s, d) => s := d } 124 debug_fuType.foreach(_ := fuType) 125 this 126 } 127 128 def isSoftPrefetch: Bool = { 129 fuType === FuType.alu.U && fuOpType === ALUOpType.or && selImm === SelImm.IMM_I && ldest === 0.U 130 } 131 132 def connectStaticInst(source: StaticInst): Unit = { 133 for ((name, data) <- this.elements) { 134 if (source.elements.contains(name)) { 135 data := source.elements(name) 136 } 137 } 138 } 139 } 140 141 // DecodedInst --[Rename]--> DynInst 142 class DynInst(implicit p: Parameters) extends XSBundle { 143 def numSrc = backendParams.numSrc 144 // passed from StaticInst 145 val instr = UInt(32.W) 146 val pc = UInt(VAddrBits.W) 147 val foldpc = UInt(MemPredPCWidth.W) 148 val exceptionVec = ExceptionVec() 149 val hasException = Bool() 150 val trigger = new TriggerCf 151 val preDecodeInfo = new PreDecodeInfo 152 val pred_taken = Bool() 153 val crossPageIPFFix = Bool() 154 val ftqPtr = new FtqPtr 155 val ftqOffset = UInt(log2Up(PredictWidth).W) 156 // passed from DecodedInst 157 val srcType = Vec(numSrc, SrcType()) 158 val ldest = UInt(LogicRegsWidth.W) 159 val fuType = FuType() 160 val fuOpType = FuOpType() 161 val rfWen = Bool() 162 val fpWen = Bool() 163 val vecWen = Bool() 164 val v0Wen = Bool() 165 val vlWen = Bool() 166 val isXSTrap = Bool() 167 val waitForward = Bool() // no speculate execution 168 val blockBackward = Bool() 169 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 170 val canRobCompress = Bool() 171 val selImm = SelImm() 172 val imm = UInt(32.W) 173 val fpu = new FPUCtrlSignals 174 val vpu = new VPUCtrlSignals 175 val vlsInstr = Bool() 176 val wfflags = Bool() 177 val isMove = Bool() 178 val uopIdx = UopIdx() 179 val isVset = Bool() 180 val firstUop = Bool() 181 val lastUop = Bool() 182 val numUops = UInt(log2Up(MaxUopSize).W) // rob need this 183 val numWB = UInt(log2Up(MaxUopSize).W) // rob need this 184 val commitType = CommitType() 185 // rename 186 val srcState = Vec(numSrc, SrcState()) 187 val srcLoadDependency = Vec(numSrc, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 188 val psrc = Vec(numSrc, UInt(PhyRegIdxWidth.W)) 189 val pdest = UInt(PhyRegIdxWidth.W) 190 val robIdx = new RobPtr 191 val instrSize = UInt(log2Ceil(RenameWidth + 1).W) 192 val dirtyFs = Bool() 193 val dirtyVs = Bool() 194 195 val eliminatedMove = Bool() 196 // Take snapshot at this CFI inst 197 val snapshot = Bool() 198 val debugInfo = new PerfDebugInfo 199 val storeSetHit = Bool() // inst has been allocated an store set 200 val waitForRobIdx = new RobPtr // store set predicted previous store robIdx 201 // Load wait is needed 202 // load inst will not be executed until former store (predicted by mdp) addr calcuated 203 val loadWaitBit = Bool() 204 // If (loadWaitBit && loadWaitStrict), strict load wait is needed 205 // load inst will not be executed until ALL former store addr calcuated 206 val loadWaitStrict = Bool() 207 val ssid = UInt(SSIDWidth.W) 208 // Todo 209 val lqIdx = new LqPtr 210 val sqIdx = new SqPtr 211 // debug module 212 val singleStep = Bool() 213 // schedule 214 val replayInst = Bool() 215 216 val debug_fuType = OptionWrapper(backendParams.debugEn, FuType()) 217 218 val numLsElem = NumLsElem() 219 220 def getDebugFuType: UInt = debug_fuType.getOrElse(fuType) 221 222 def isLUI: Bool = this.fuType === FuType.alu.U && (this.selImm === SelImm.IMM_U || this.selImm === SelImm.IMM_LUI32) 223 def isLUI32: Bool = this.selImm === SelImm.IMM_LUI32 224 def isWFI: Bool = this.fuType === FuType.csr.U && fuOpType === CSROpType.wfi 225 226 def isSvinvalBegin(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && !flush 227 def isSvinval(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.sfence && !flush 228 def isSvinvalEnd(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && flush 229 def isNotSvinval = !FuType.isFence(fuType) 230 231 def isHls: Bool = { 232 fuType === FuType.ldu.U && LSUOpType.isHlv(fuOpType) || fuType === FuType.stu.U && LSUOpType.isHsv(fuOpType) 233 } 234 235 def isVecOPF: Bool = { 236 FuType.isVecOPF(fuType) 237 } 238 239 def srcIsReady: Vec[Bool] = { 240 VecInit(this.srcType.zip(this.srcState).map { 241 case (t, s) => SrcType.isNotReg(t) || SrcState.isReady(s) 242 }) 243 } 244 245 def clearExceptions( 246 exceptionBits: Seq[Int] = Seq(), 247 flushPipe : Boolean = false, 248 replayInst : Boolean = false 249 ): DynInst = { 250 this.exceptionVec.zipWithIndex.filterNot(x => exceptionBits.contains(x._2)).foreach(_._1 := false.B) 251 if (!flushPipe) { this.flushPipe := false.B } 252 if (!replayInst) { this.replayInst := false.B } 253 this 254 } 255 256 def needWriteRf: Bool = (rfWen && ldest =/= 0.U) || fpWen || vecWen || v0Wen || vlWen 257 } 258 259 trait BundleSource { 260 var wakeupSource = "undefined" 261 var idx = 0 262 } 263 264 /** 265 * 266 * @param pregIdxWidth index width of preg 267 * @param exuIndices exu indices of wakeup bundle 268 */ 269 sealed abstract class IssueQueueWakeUpBaseBundle(pregIdxWidth: Int, val exuIndices: Seq[Int])(implicit p: Parameters) extends XSBundle { 270 val rfWen = Bool() 271 val fpWen = Bool() 272 val vecWen = Bool() 273 val v0Wen = Bool() 274 val vlWen = Bool() 275 val pdest = UInt(pregIdxWidth.W) 276 277 /** 278 * @param successor Seq[(psrc, srcType)] 279 * @return Seq[if wakeup psrc] 280 */ 281 def wakeUp(successor: Seq[(UInt, UInt)], valid: Bool): Seq[Bool] = { 282 successor.map { case (thatPsrc, srcType) => 283 val pdestMatch = pdest === thatPsrc 284 pdestMatch && ( 285 SrcType.isFp(srcType) && this.fpWen || 286 SrcType.isXp(srcType) && this.rfWen || 287 SrcType.isVp(srcType) && this.vecWen 288 ) && valid 289 } 290 } 291 def wakeUpV0(successor: (UInt, UInt), valid: Bool): Bool = { 292 val (thatPsrc, srcType) = successor 293 val pdestMatch = pdest === thatPsrc 294 pdestMatch && ( 295 SrcType.isV0(srcType) && this.v0Wen 296 ) && valid 297 } 298 def wakeUpVl(successor: (UInt, UInt), valid: Bool): Bool = { 299 val (thatPsrc, srcType) = successor 300 val pdestMatch = pdest === thatPsrc 301 pdestMatch && ( 302 SrcType.isVp(srcType) && this.vlWen 303 ) && valid 304 } 305 def wakeUpFromIQ(successor: Seq[(UInt, UInt)]): Seq[Bool] = { 306 successor.map { case (thatPsrc, srcType) => 307 val pdestMatch = pdest === thatPsrc 308 pdestMatch && ( 309 SrcType.isFp(srcType) && this.fpWen || 310 SrcType.isXp(srcType) && this.rfWen || 311 SrcType.isVp(srcType) && this.vecWen 312 ) 313 } 314 } 315 def wakeUpV0FromIQ(successor: (UInt, UInt)): Bool = { 316 val (thatPsrc, srcType) = successor 317 val pdestMatch = pdest === thatPsrc 318 pdestMatch && ( 319 SrcType.isV0(srcType) && this.v0Wen 320 ) 321 } 322 def wakeUpVlFromIQ(successor: (UInt, UInt)): Bool = { 323 val (thatPsrc, srcType) = successor 324 val pdestMatch = pdest === thatPsrc 325 pdestMatch && ( 326 SrcType.isVp(srcType) && this.vlWen 327 ) 328 } 329 330 def hasOnlyOneSource: Boolean = exuIndices.size == 1 331 332 def hasMultiSources: Boolean = exuIndices.size > 1 333 334 def isWBWakeUp = this.isInstanceOf[IssueQueueWBWakeUpBundle] 335 336 def isIQWakeUp = this.isInstanceOf[IssueQueueIQWakeUpBundle] 337 338 def exuIdx: Int = { 339 require(hasOnlyOneSource) 340 this.exuIndices.head 341 } 342 } 343 344 class IssueQueueWBWakeUpBundle(exuIndices: Seq[Int], backendParams: BackendParams)(implicit p: Parameters) extends IssueQueueWakeUpBaseBundle(backendParams.pregIdxWidth, exuIndices) { 345 346 } 347 348 class IssueQueueIQWakeUpBundle( 349 exuIdx: Int, 350 backendParams: BackendParams, 351 copyWakeupOut: Boolean = false, 352 copyNum: Int = 0 353 )(implicit p: Parameters) extends IssueQueueWakeUpBaseBundle(backendParams.pregIdxWidth, Seq(exuIdx)) { 354 val loadDependency = Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W)) 355 val is0Lat = Bool() 356 val params = backendParams.allExuParams.filter(_.exuIdx == exuIdx).head 357 val pdestCopy = OptionWrapper(copyWakeupOut, Vec(copyNum, UInt(params.wbPregIdxWidth.W))) 358 val rfWenCopy = OptionWrapper(copyWakeupOut && params.needIntWen, Vec(copyNum, Bool())) 359 val fpWenCopy = OptionWrapper(copyWakeupOut && params.needFpWen, Vec(copyNum, Bool())) 360 val vecWenCopy = OptionWrapper(copyWakeupOut && params.needVecWen, Vec(copyNum, Bool())) 361 val v0WenCopy = OptionWrapper(copyWakeupOut && params.needV0Wen, Vec(copyNum, Bool())) 362 val vlWenCopy = OptionWrapper(copyWakeupOut && params.needVlWen, Vec(copyNum, Bool())) 363 val loadDependencyCopy = OptionWrapper(copyWakeupOut && params.isIQWakeUpSink, Vec(copyNum, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W)))) 364 def fromExuInput(exuInput: ExuInput, l2ExuVecs: Vec[Vec[Bool]]): Unit = { 365 this.rfWen := exuInput.rfWen.getOrElse(false.B) 366 this.fpWen := exuInput.fpWen.getOrElse(false.B) 367 this.vecWen := exuInput.vecWen.getOrElse(false.B) 368 this.v0Wen := exuInput.v0Wen.getOrElse(false.B) 369 this.vlWen := exuInput.vlWen.getOrElse(false.B) 370 this.pdest := exuInput.pdest 371 } 372 373 def fromExuInput(exuInput: ExuInput): Unit = { 374 this.rfWen := exuInput.rfWen.getOrElse(false.B) 375 this.fpWen := exuInput.fpWen.getOrElse(false.B) 376 this.vecWen := exuInput.vecWen.getOrElse(false.B) 377 this.v0Wen := exuInput.v0Wen.getOrElse(false.B) 378 this.vlWen := exuInput.vlWen.getOrElse(false.B) 379 this.pdest := exuInput.pdest 380 } 381 } 382 383 class VPUCtrlSignals(implicit p: Parameters) extends XSBundle { 384 // vtype 385 val vill = Bool() 386 val vma = Bool() // 1: agnostic, 0: undisturbed 387 val vta = Bool() // 1: agnostic, 0: undisturbed 388 val vsew = VSew() 389 val vlmul = VLmul() // 1/8~8 --> -3~3 390 391 // spec vtype 392 val specVill = Bool() 393 val specVma = Bool() // 1: agnostic, 0: undisturbed 394 val specVta = Bool() // 1: agnostic, 0: undisturbed 395 val specVsew = VSew() 396 val specVlmul = VLmul() // 1/8~8 --> -3~3 397 398 val vm = Bool() // 0: need v0.t 399 val vstart = Vl() 400 401 // float rounding mode 402 val frm = Frm() 403 // scalar float instr and vector float reduction 404 val fpu = Fpu() 405 // vector fix int rounding mode 406 val vxrm = Vxrm() 407 // vector uop index, exclude other non-vector uop 408 val vuopIdx = UopIdx() 409 val lastUop = Bool() 410 // maybe used if data dependancy 411 val vmask = UInt(V0Data().dataWidth.W) 412 val vl = Vl() 413 414 // vector load/store 415 val nf = Nf() 416 val veew = VEew() 417 418 val isReverse = Bool() // vrsub, vrdiv 419 val isExt = Bool() 420 val isNarrow = Bool() 421 val isDstMask = Bool() // vvm, vvvm, mmm 422 val isOpMask = Bool() // vmand, vmnand 423 val isMove = Bool() // vmv.s.x, vmv.v.v, vmv.v.x, vmv.v.i 424 425 val isDependOldvd = Bool() // some instruction's computation depends on oldvd 426 val isWritePartVd = Bool() // some instruction's computation writes part of vd, such as vredsum 427 428 def vtype: VType = { 429 val res = Wire(VType()) 430 res.illegal := this.vill 431 res.vma := this.vma 432 res.vta := this.vta 433 res.vsew := this.vsew 434 res.vlmul := this.vlmul 435 res 436 } 437 438 def specVType: VType = { 439 val res = Wire(VType()) 440 res.illegal := this.specVill 441 res.vma := this.specVma 442 res.vta := this.specVta 443 res.vsew := this.specVsew 444 res.vlmul := this.specVlmul 445 res 446 } 447 448 def vconfig: VConfig = { 449 val res = Wire(VConfig()) 450 res.vtype := this.vtype 451 res.vl := this.vl 452 res 453 } 454 455 def connectVType(source: VType): Unit = { 456 this.vill := source.illegal 457 this.vma := source.vma 458 this.vta := source.vta 459 this.vsew := source.vsew 460 this.vlmul := source.vlmul 461 } 462 } 463 464 // DynInst --[IssueQueue]--> DataPath 465 class IssueQueueIssueBundle( 466 iqParams: IssueBlockParams, 467 val exuParams: ExeUnitParams, 468 )(implicit 469 p: Parameters 470 ) extends XSBundle { 471 private val rfReadDataCfgSet: Seq[Set[DataConfig]] = exuParams.getRfReadDataCfgSet 472 473 val rf: MixedVec[MixedVec[RfReadPortWithConfig]] = Flipped(MixedVec( 474 rfReadDataCfgSet.map((set: Set[DataConfig]) => 475 MixedVec(set.map((x: DataConfig) => new RfReadPortWithConfig(x, exuParams.rdPregIdxWidth)).toSeq) 476 ) 477 )) 478 479 val srcType = Vec(exuParams.numRegSrc, SrcType()) // used to select imm or reg data 480 val rcIdx = OptionWrapper(exuParams.needReadRegCache, Vec(exuParams.numRegSrc, UInt(RegCacheIdxWidth.W))) // used to select regcache data 481 val immType = SelImm() // used to select imm extractor 482 val common = new ExuInput(exuParams) 483 val addrOH = UInt(iqParams.numEntries.W) 484 485 def exuIdx = exuParams.exuIdx 486 def getSource: SchedulerType = exuParams.getWBSource 487 488 def getRfReadValidBundle(issueValid: Bool): Seq[ValidIO[RfReadPortWithConfig]] = { 489 rf.zip(srcType).map { 490 case (rfRd: MixedVec[RfReadPortWithConfig], t: UInt) => 491 makeValid(issueValid, rfRd.head) 492 }.toSeq 493 } 494 } 495 496 class OGRespBundle(implicit p:Parameters, params: IssueBlockParams) extends XSBundle { 497 val issueQueueParams = this.params 498 val og0resp = Valid(new EntryDeqRespBundle) 499 val og1resp = Valid(new EntryDeqRespBundle) 500 } 501 502 class WbFuBusyTableWriteBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 503 private val intCertainLat = params.intLatencyCertain 504 private val fpCertainLat = params.fpLatencyCertain 505 private val vfCertainLat = params.vfLatencyCertain 506 private val v0CertainLat = params.v0LatencyCertain 507 private val vlCertainLat = params.vlLatencyCertain 508 private val intLat = params.intLatencyValMax 509 private val fpLat = params.fpLatencyValMax 510 private val vfLat = params.vfLatencyValMax 511 private val v0Lat = params.v0LatencyValMax 512 private val vlLat = params.vlLatencyValMax 513 514 val intWbBusyTable = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 515 val fpWbBusyTable = OptionWrapper(fpCertainLat, UInt((fpLat + 1).W)) 516 val vfWbBusyTable = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 517 val v0WbBusyTable = OptionWrapper(v0CertainLat, UInt((v0Lat + 1).W)) 518 val vlWbBusyTable = OptionWrapper(vlCertainLat, UInt((vlLat + 1).W)) 519 val intDeqRespSet = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 520 val fpDeqRespSet = OptionWrapper(fpCertainLat, UInt((fpLat + 1).W)) 521 val vfDeqRespSet = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 522 val v0DeqRespSet = OptionWrapper(v0CertainLat, UInt((v0Lat + 1).W)) 523 val vlDeqRespSet = OptionWrapper(vlCertainLat, UInt((vlLat + 1).W)) 524 } 525 526 class WbFuBusyTableReadBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 527 private val intCertainLat = params.intLatencyCertain 528 private val fpCertainLat = params.fpLatencyCertain 529 private val vfCertainLat = params.vfLatencyCertain 530 private val v0CertainLat = params.v0LatencyCertain 531 private val vlCertainLat = params.vlLatencyCertain 532 private val intLat = params.intLatencyValMax 533 private val fpLat = params.fpLatencyValMax 534 private val vfLat = params.vfLatencyValMax 535 private val v0Lat = params.v0LatencyValMax 536 private val vlLat = params.vlLatencyValMax 537 538 val intWbBusyTable = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 539 val fpWbBusyTable = OptionWrapper(fpCertainLat, UInt((fpLat + 1).W)) 540 val vfWbBusyTable = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 541 val v0WbBusyTable = OptionWrapper(v0CertainLat, UInt((v0Lat + 1).W)) 542 val vlWbBusyTable = OptionWrapper(vlCertainLat, UInt((vlLat + 1).W)) 543 } 544 545 class WbConflictBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 546 private val intCertainLat = params.intLatencyCertain 547 private val fpCertainLat = params.fpLatencyCertain 548 private val vfCertainLat = params.vfLatencyCertain 549 private val v0CertainLat = params.v0LatencyCertain 550 private val vlCertainLat = params.vlLatencyCertain 551 552 val intConflict = OptionWrapper(intCertainLat, Bool()) 553 val fpConflict = OptionWrapper(fpCertainLat, Bool()) 554 val vfConflict = OptionWrapper(vfCertainLat, Bool()) 555 val v0Conflict = OptionWrapper(v0CertainLat, Bool()) 556 val vlConflict = OptionWrapper(vlCertainLat, Bool()) 557 } 558 559 class ImmInfo extends Bundle { 560 val imm = UInt(32.W) 561 val immType = SelImm() 562 } 563 564 // DataPath --[ExuInput]--> Exu 565 class ExuInput(val params: ExeUnitParams, copyWakeupOut:Boolean = false, copyNum:Int = 0)(implicit p: Parameters) extends XSBundle { 566 val fuType = FuType() 567 val fuOpType = FuOpType() 568 val src = Vec(params.numRegSrc, UInt(params.srcDataBitsMax.W)) 569 val imm = UInt(32.W) 570 val robIdx = new RobPtr 571 val iqIdx = UInt(log2Up(MemIQSizeMax).W)// Only used by store yet 572 val isFirstIssue = Bool() // Only used by store yet 573 val pdestCopy = OptionWrapper(copyWakeupOut, Vec(copyNum, UInt(params.wbPregIdxWidth.W))) 574 val rfWenCopy = OptionWrapper(copyWakeupOut && params.needIntWen, Vec(copyNum, Bool())) 575 val fpWenCopy = OptionWrapper(copyWakeupOut && params.needFpWen, Vec(copyNum, Bool())) 576 val vecWenCopy = OptionWrapper(copyWakeupOut && params.needVecWen, Vec(copyNum, Bool())) 577 val v0WenCopy = OptionWrapper(copyWakeupOut && params.needV0Wen, Vec(copyNum, Bool())) 578 val vlWenCopy = OptionWrapper(copyWakeupOut && params.needVlWen, Vec(copyNum, Bool())) 579 val loadDependencyCopy = OptionWrapper(copyWakeupOut && params.isIQWakeUpSink, Vec(copyNum, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W)))) 580 val pdest = UInt(params.wbPregIdxWidth.W) 581 val rfWen = if (params.needIntWen) Some(Bool()) else None 582 val fpWen = if (params.needFpWen) Some(Bool()) else None 583 val vecWen = if (params.needVecWen) Some(Bool()) else None 584 val v0Wen = if (params.needV0Wen) Some(Bool()) else None 585 val vlWen = if (params.needVlWen) Some(Bool()) else None 586 val fpu = if (params.writeFflags) Some(new FPUCtrlSignals) else None 587 val vpu = if (params.needVPUCtrl) Some(new VPUCtrlSignals) else None 588 val flushPipe = if (params.flushPipe) Some(Bool()) else None 589 val pc = if (params.needPc) Some(UInt(VAddrData().dataWidth.W)) else None 590 val preDecode = if (params.hasPredecode) Some(new PreDecodeInfo) else None 591 val ftqIdx = if (params.needPc || params.replayInst || params.hasStoreAddrFu || params.hasCSR) 592 Some(new FtqPtr) else None 593 val ftqOffset = if (params.needPc || params.replayInst || params.hasStoreAddrFu || params.hasCSR) 594 Some(UInt(log2Up(PredictWidth).W)) else None 595 val predictInfo = if (params.needPdInfo) Some(new Bundle { 596 val target = UInt(VAddrData().dataWidth.W) 597 val taken = Bool() 598 }) else None 599 val loadWaitBit = OptionWrapper(params.hasLoadExu, Bool()) 600 val waitForRobIdx = OptionWrapper(params.hasLoadExu, new RobPtr) // store set predicted previous store robIdx 601 val storeSetHit = OptionWrapper(params.hasLoadExu, Bool()) // inst has been allocated an store set 602 val loadWaitStrict = OptionWrapper(params.hasLoadExu, Bool()) // load inst will not be executed until ALL former store addr calcuated 603 val ssid = OptionWrapper(params.hasLoadExu, UInt(SSIDWidth.W)) 604 // only vector load store need 605 val numLsElem = OptionWrapper(params.hasVecLsFu, NumLsElem()) 606 607 val sqIdx = if (params.hasMemAddrFu || params.hasStdFu) Some(new SqPtr) else None 608 val lqIdx = if (params.hasMemAddrFu) Some(new LqPtr) else None 609 val dataSources = Vec(params.numRegSrc, DataSource()) 610 val l1ExuOH = OptionWrapper(params.isIQWakeUpSink, Vec(params.numRegSrc, ExuVec())) 611 val srcTimer = OptionWrapper(params.isIQWakeUpSink, Vec(params.numRegSrc, UInt(3.W))) 612 val loadDependency = OptionWrapper(params.isIQWakeUpSink, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 613 614 val perfDebugInfo = new PerfDebugInfo() 615 616 def exuIdx = this.params.exuIdx 617 618 def needCancel(og0CancelOH: UInt, og1CancelOH: UInt) : Bool = { 619 if (params.isIQWakeUpSink) { 620 require( 621 og0CancelOH.getWidth == l1ExuOH.get.head.getWidth, 622 s"cancelVecSize: {og0: ${og0CancelOH.getWidth}, og1: ${og1CancelOH.getWidth}}" 623 ) 624 val l1Cancel: Bool = l1ExuOH.get.zip(srcTimer.get).map { 625 case(exuOH: Vec[Bool], srcTimer: UInt) => 626 (exuOH.asUInt & og0CancelOH).orR && srcTimer === 1.U 627 }.reduce(_ | _) 628 l1Cancel 629 } else { 630 false.B 631 } 632 } 633 634 def fromIssueBundle(source: IssueQueueIssueBundle): Unit = { 635 // src is assigned to rfReadData 636 this.fuType := source.common.fuType 637 this.fuOpType := source.common.fuOpType 638 this.imm := source.common.imm 639 this.robIdx := source.common.robIdx 640 this.pdest := source.common.pdest 641 this.isFirstIssue := source.common.isFirstIssue // Only used by mem debug log 642 this.iqIdx := source.common.iqIdx // Only used by mem feedback 643 this.dataSources := source.common.dataSources 644 this.l1ExuOH .foreach(_ := source.common.l1ExuOH.get) 645 this.rfWen .foreach(_ := source.common.rfWen.get) 646 this.fpWen .foreach(_ := source.common.fpWen.get) 647 this.vecWen .foreach(_ := source.common.vecWen.get) 648 this.v0Wen .foreach(_ := source.common.v0Wen.get) 649 this.vlWen .foreach(_ := source.common.vlWen.get) 650 this.fpu .foreach(_ := source.common.fpu.get) 651 this.vpu .foreach(_ := source.common.vpu.get) 652 this.flushPipe .foreach(_ := source.common.flushPipe.get) 653 this.pc .foreach(_ := source.common.pc.get) 654 this.preDecode .foreach(_ := source.common.preDecode.get) 655 this.ftqIdx .foreach(_ := source.common.ftqIdx.get) 656 this.ftqOffset .foreach(_ := source.common.ftqOffset.get) 657 this.predictInfo .foreach(_ := source.common.predictInfo.get) 658 this.loadWaitBit .foreach(_ := source.common.loadWaitBit.get) 659 this.waitForRobIdx .foreach(_ := source.common.waitForRobIdx.get) 660 this.storeSetHit .foreach(_ := source.common.storeSetHit.get) 661 this.loadWaitStrict.foreach(_ := source.common.loadWaitStrict.get) 662 this.ssid .foreach(_ := source.common.ssid.get) 663 this.lqIdx .foreach(_ := source.common.lqIdx.get) 664 this.sqIdx .foreach(_ := source.common.sqIdx.get) 665 this.numLsElem .foreach(_ := source.common.numLsElem.get) 666 this.srcTimer .foreach(_ := source.common.srcTimer.get) 667 this.loadDependency.foreach(_ := source.common.loadDependency.get.map(_ << 1)) 668 } 669 } 670 671 // ExuInput --[FuncUnit]--> ExuOutput 672 class ExuOutput( 673 val params: ExeUnitParams, 674 )(implicit 675 val p: Parameters 676 ) extends Bundle with BundleSource with HasXSParameter { 677 val data = Vec(params.wbPathNum, UInt(params.destDataBitsMax.W)) 678 val pdest = UInt(params.wbPregIdxWidth.W) 679 val robIdx = new RobPtr 680 val intWen = if (params.needIntWen) Some(Bool()) else None 681 val fpWen = if (params.needFpWen) Some(Bool()) else None 682 val vecWen = if (params.needVecWen) Some(Bool()) else None 683 val v0Wen = if (params.needV0Wen) Some(Bool()) else None 684 val vlWen = if (params.needVlWen) Some(Bool()) else None 685 val redirect = if (params.hasRedirect) Some(ValidIO(new Redirect)) else None 686 val fflags = if (params.writeFflags) Some(UInt(5.W)) else None 687 val wflags = if (params.writeFflags) Some(Bool()) else None 688 val vxsat = if (params.writeVxsat) Some(Bool()) else None 689 val exceptionVec = if (params.exceptionOut.nonEmpty) Some(ExceptionVec()) else None 690 val flushPipe = if (params.flushPipe) Some(Bool()) else None 691 val replay = if (params.replayInst) Some(Bool()) else None 692 val lqIdx = if (params.hasLoadFu) Some(new LqPtr()) else None 693 val sqIdx = if (params.hasStoreAddrFu || params.hasStdFu) 694 Some(new SqPtr()) else None 695 val trigger = if (params.trigger) Some(new TriggerCf) else None 696 // uop info 697 val predecodeInfo = if(params.hasPredecode) Some(new PreDecodeInfo) else None 698 // vldu used only 699 val vls = OptionWrapper(params.hasVLoadFu, new Bundle { 700 val vpu = new VPUCtrlSignals 701 val oldVdPsrc = UInt(PhyRegIdxWidth.W) 702 val vdIdx = UInt(3.W) 703 val vdIdxInField = UInt(3.W) 704 val isIndexed = Bool() 705 val isMasked = Bool() 706 }) 707 val debug = new DebugBundle 708 val debugInfo = new PerfDebugInfo 709 } 710 711 // ExuOutput + DynInst --> WriteBackBundle 712 class WriteBackBundle(val params: PregWB, backendParams: BackendParams)(implicit p: Parameters) extends Bundle with BundleSource { 713 val rfWen = Bool() 714 val fpWen = Bool() 715 val vecWen = Bool() 716 val v0Wen = Bool() 717 val vlWen = Bool() 718 val pdest = UInt(params.pregIdxWidth(backendParams).W) 719 val data = UInt(params.dataWidth.W) 720 val robIdx = new RobPtr()(p) 721 val flushPipe = Bool() 722 val replayInst = Bool() 723 val redirect = ValidIO(new Redirect) 724 val fflags = UInt(5.W) 725 val vxsat = Bool() 726 val exceptionVec = ExceptionVec() 727 val debug = new DebugBundle 728 val debugInfo = new PerfDebugInfo 729 730 this.wakeupSource = s"WB(${params.toString})" 731 732 def fromExuOutput(source: ExuOutput, wbType: String) = { 733 val typeMap = Map("int" -> 0, "fp" -> 1, "vf" -> 2, "v0" -> 3, "vl" -> 4) 734 this.rfWen := source.intWen.getOrElse(false.B) 735 this.fpWen := source.fpWen.getOrElse(false.B) 736 this.vecWen := source.vecWen.getOrElse(false.B) 737 this.v0Wen := source.v0Wen.getOrElse(false.B) 738 this.vlWen := source.vlWen.getOrElse(false.B) 739 this.pdest := source.pdest 740 this.data := source.data(source.params.wbIndex(typeMap(wbType))) 741 this.robIdx := source.robIdx 742 this.flushPipe := source.flushPipe.getOrElse(false.B) 743 this.replayInst := source.replay.getOrElse(false.B) 744 this.redirect := source.redirect.getOrElse(0.U.asTypeOf(this.redirect)) 745 this.fflags := source.fflags.getOrElse(0.U.asTypeOf(this.fflags)) 746 this.vxsat := source.vxsat.getOrElse(0.U.asTypeOf(this.vxsat)) 747 this.exceptionVec := source.exceptionVec.getOrElse(0.U.asTypeOf(this.exceptionVec)) 748 this.debug := source.debug 749 this.debugInfo := source.debugInfo 750 } 751 752 def asIntRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 753 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(IntData()).addrWidth))) 754 rfWrite.wen := this.rfWen && fire 755 rfWrite.addr := this.pdest 756 rfWrite.data := this.data 757 rfWrite.intWen := this.rfWen 758 rfWrite.fpWen := false.B 759 rfWrite.vecWen := false.B 760 rfWrite.v0Wen := false.B 761 rfWrite.vlWen := false.B 762 rfWrite 763 } 764 765 def asFpRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 766 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(FpData()).addrWidth))) 767 rfWrite.wen := this.fpWen && fire 768 rfWrite.addr := this.pdest 769 rfWrite.data := this.data 770 rfWrite.intWen := false.B 771 rfWrite.fpWen := this.fpWen 772 rfWrite.vecWen := false.B 773 rfWrite.v0Wen := false.B 774 rfWrite.vlWen := false.B 775 rfWrite 776 } 777 778 def asVfRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 779 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(VecData()).addrWidth))) 780 rfWrite.wen := this.vecWen && fire 781 rfWrite.addr := this.pdest 782 rfWrite.data := this.data 783 rfWrite.intWen := false.B 784 rfWrite.fpWen := false.B 785 rfWrite.vecWen := this.vecWen 786 rfWrite.v0Wen := false.B 787 rfWrite.vlWen := false.B 788 rfWrite 789 } 790 791 def asV0RfWriteBundle(fire: Bool): RfWritePortWithConfig = { 792 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(V0Data()).addrWidth))) 793 rfWrite.wen := this.v0Wen && fire 794 rfWrite.addr := this.pdest 795 rfWrite.data := this.data 796 rfWrite.intWen := false.B 797 rfWrite.fpWen := false.B 798 rfWrite.vecWen := false.B 799 rfWrite.v0Wen := this.v0Wen 800 rfWrite.vlWen := false.B 801 rfWrite 802 } 803 804 def asVlRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 805 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(VlData()).addrWidth))) 806 rfWrite.wen := this.vlWen && fire 807 rfWrite.addr := this.pdest 808 rfWrite.data := this.data 809 rfWrite.intWen := false.B 810 rfWrite.fpWen := false.B 811 rfWrite.vecWen := false.B 812 rfWrite.v0Wen := false.B 813 rfWrite.vlWen := this.vlWen 814 rfWrite 815 } 816 } 817 818 // ExuOutput --> ExuBypassBundle --[DataPath]-->ExuInput 819 // / 820 // [IssueQueue]--> ExuInput -- 821 class ExuBypassBundle( 822 val params: ExeUnitParams, 823 )(implicit 824 val p: Parameters 825 ) extends Bundle { 826 val data = UInt(params.destDataBitsMax.W) 827 val pdest = UInt(params.wbPregIdxWidth.W) 828 } 829 830 class ExceptionInfo(implicit p: Parameters) extends XSBundle { 831 val pc = UInt(VAddrData().dataWidth.W) 832 val instr = UInt(32.W) 833 val commitType = CommitType() 834 val exceptionVec = ExceptionVec() 835 val gpaddr = UInt(GPAddrBits.W) 836 val singleStep = Bool() 837 val crossPageIPFFix = Bool() 838 val isInterrupt = Bool() 839 val isHls = Bool() 840 val vls = Bool() 841 val trigger = new TriggerCf 842 } 843 844 object UopIdx { 845 def apply()(implicit p: Parameters): UInt = UInt(log2Up(p(XSCoreParamsKey).MaxUopSize + 1).W) 846 } 847 848 object FuLatency { 849 def apply(): UInt = UInt(width.W) 850 851 def width = 4 // 0~15 // Todo: assosiate it with FuConfig 852 } 853 854 object ExuOH { 855 def apply(exuNum: Int): UInt = UInt(exuNum.W) 856 857 def apply()(implicit p: Parameters): UInt = UInt(width.W) 858 859 def width(implicit p: Parameters): Int = p(XSCoreParamsKey).backendParams.numExu 860 } 861 862 object ExuVec { 863 def apply(exuNum: Int): Vec[Bool] = Vec(exuNum, Bool()) 864 865 def apply()(implicit p: Parameters): Vec[Bool] = Vec(width, Bool()) 866 867 def width(implicit p: Parameters): Int = p(XSCoreParamsKey).backendParams.numExu 868 } 869 870 class CancelSignal(implicit p: Parameters) extends XSBundle { 871 val rfWen = Bool() 872 val fpWen = Bool() 873 val vecWen = Bool() 874 val v0Wen = Bool() 875 val vlWen = Bool() 876 val pdest = UInt(PhyRegIdxWidth.W) 877 } 878 879 class MemExuInput(isVector: Boolean = false)(implicit p: Parameters) extends XSBundle { 880 val uop = new DynInst 881 val src = if (isVector) Vec(5, UInt(VLEN.W)) else Vec(3, UInt(XLEN.W)) 882 val iqIdx = UInt(log2Up(MemIQSizeMax).W) 883 val isFirstIssue = Bool() 884 val flowNum = OptionWrapper(isVector, NumLsElem()) 885 886 def src_rs1 = src(0) 887 def src_stride = src(1) 888 def src_vs3 = src(2) 889 def src_mask = if (isVector) src(3) else 0.U 890 def src_vl = if (isVector) src(4) else 0.U 891 } 892 893 class MemExuOutput(isVector: Boolean = false)(implicit p: Parameters) extends XSBundle { 894 val uop = new DynInst 895 val data = if (isVector) UInt(VLEN.W) else UInt(XLEN.W) 896 val mask = if (isVector) Some(UInt(VLEN.W)) else None 897 val vdIdx = if (isVector) Some(UInt(3.W)) else None // TODO: parameterize width 898 val vdIdxInField = if (isVector) Some(UInt(3.W)) else None 899 val debug = new DebugBundle 900 901 def isVls = FuType.isVls(uop.fuType) 902 } 903 904 class MemMicroOpRbExt(implicit p: Parameters) extends XSBundle { 905 val uop = new DynInst 906 val flag = UInt(1.W) 907 } 908 909 object LoadShouldCancel { 910 def apply(loadDependency: Option[Seq[UInt]], ldCancel: Seq[LoadCancelIO]): Bool = { 911 val ld1Cancel = loadDependency.map(_.zip(ldCancel.map(_.ld1Cancel)).map { case (dep, cancel) => cancel && dep(0)}.reduce(_ || _)) 912 val ld2Cancel = loadDependency.map(_.zip(ldCancel.map(_.ld2Cancel)).map { case (dep, cancel) => cancel && dep(1)}.reduce(_ || _)) 913 ld1Cancel.map(_ || ld2Cancel.get).getOrElse(false.B) 914 } 915 } 916} 917