1package xiangshan.backend 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util.BitPat.bitPatToUInt 6import chisel3.util._ 7import utils.BundleUtils.makeValid 8import utils.OptionWrapper 9import xiangshan._ 10import xiangshan.backend.datapath.DataConfig._ 11import xiangshan.backend.datapath.DataSource 12import xiangshan.backend.datapath.WbConfig.PregWB 13import xiangshan.backend.decode.{ImmUnion, XDecode} 14import xiangshan.backend.exu.ExeUnitParams 15import xiangshan.backend.fu.FuType 16import xiangshan.backend.fu.fpu.Bundles.Frm 17import xiangshan.backend.fu.vector.Bundles._ 18import xiangshan.backend.issue.{IssueBlockParams, IssueQueueDeqRespBundle, SchedulerType} 19import xiangshan.backend.issue.EntryBundles._ 20import xiangshan.backend.regfile.{RfReadPortWithConfig, RfWritePortWithConfig} 21import xiangshan.backend.rob.RobPtr 22import xiangshan.frontend._ 23import xiangshan.mem.{LqPtr, SqPtr} 24import yunsuan.vector.VIFuParam 25import xiangshan.backend.trace._ 26 27object Bundles { 28 /** 29 * Connect Same Name Port like bundleSource := bundleSinkBudle. 30 * 31 * There is no limit to the number of ports on both sides. 32 * 33 * Don't forget to connect the remaining ports! 34 */ 35 def connectSamePort (bundleSource: Bundle, bundleSink: Bundle):Unit = { 36 bundleSource.elements.foreach { case (name, data) => 37 if (bundleSink.elements.contains(name)) 38 data := bundleSink.elements(name) 39 } 40 } 41 // frontend -> backend 42 class StaticInst(implicit p: Parameters) extends XSBundle { 43 val instr = UInt(32.W) 44 val pc = UInt(VAddrBits.W) 45 val foldpc = UInt(MemPredPCWidth.W) 46 val exceptionVec = ExceptionVec() 47 val trigger = TriggerAction() 48 val preDecodeInfo = new PreDecodeInfo 49 val pred_taken = Bool() 50 val crossPageIPFFix = Bool() 51 val ftqPtr = new FtqPtr 52 val ftqOffset = UInt(log2Up(PredictWidth).W) 53 54 def connectCtrlFlow(source: CtrlFlow): Unit = { 55 this.instr := source.instr 56 this.pc := source.pc 57 this.foldpc := source.foldpc 58 this.exceptionVec := source.exceptionVec 59 this.trigger := source.trigger 60 this.preDecodeInfo := source.pd 61 this.pred_taken := source.pred_taken 62 this.crossPageIPFFix := source.crossPageIPFFix 63 this.ftqPtr := source.ftqPtr 64 this.ftqOffset := source.ftqOffset 65 } 66 } 67 68 // StaticInst --[Decode]--> DecodedInst 69 class DecodedInst(implicit p: Parameters) extends XSBundle { 70 def numSrc = backendParams.numSrc 71 // passed from StaticInst 72 val instr = UInt(32.W) 73 val pc = UInt(VAddrBits.W) 74 val foldpc = UInt(MemPredPCWidth.W) 75 val exceptionVec = ExceptionVec() 76 val trigger = TriggerAction() 77 val preDecodeInfo = new PreDecodeInfo 78 val pred_taken = Bool() 79 val crossPageIPFFix = Bool() 80 val ftqPtr = new FtqPtr 81 val ftqOffset = UInt(log2Up(PredictWidth).W) 82 // decoded 83 val srcType = Vec(numSrc, SrcType()) 84 val lsrc = Vec(numSrc, UInt(LogicRegsWidth.W)) 85 val ldest = UInt(LogicRegsWidth.W) 86 val fuType = FuType() 87 val fuOpType = FuOpType() 88 val rfWen = Bool() 89 val fpWen = Bool() 90 val vecWen = Bool() 91 val v0Wen = Bool() 92 val vlWen = Bool() 93 val isXSTrap = Bool() 94 val waitForward = Bool() // no speculate execution 95 val blockBackward = Bool() 96 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 97 val canRobCompress = Bool() 98 val selImm = SelImm() 99 val imm = UInt(ImmUnion.maxLen.W) 100 val fpu = new FPUCtrlSignals 101 val vpu = new VPUCtrlSignals 102 val vlsInstr = Bool() 103 val wfflags = Bool() 104 val isMove = Bool() 105 val uopIdx = UopIdx() 106 val uopSplitType = UopSplitType() 107 val isVset = Bool() 108 val firstUop = Bool() 109 val lastUop = Bool() 110 val numUops = UInt(log2Up(MaxUopSize).W) // rob need this 111 val numWB = UInt(log2Up(MaxUopSize).W) // rob need this 112 val commitType = CommitType() // Todo: remove it 113 val needFrm = new NeedFrmBundle 114 115 val debug_fuType = OptionWrapper(backendParams.debugEn, FuType()) 116 117 private def allSignals = srcType.take(3) ++ Seq(fuType, fuOpType, rfWen, fpWen, vecWen, 118 isXSTrap, waitForward, blockBackward, flushPipe, canRobCompress, uopSplitType, selImm) 119 120 def decode(inst: UInt, table: Iterable[(BitPat, List[BitPat])]): DecodedInst = { 121 val decoder: Seq[UInt] = ListLookup( 122 inst, XDecode.decodeDefault.map(bitPatToUInt), 123 table.map{ case (pat, pats) => (pat, pats.map(bitPatToUInt)) }.toArray 124 ) 125 allSignals zip decoder foreach { case (s, d) => s := d } 126 debug_fuType.foreach(_ := fuType) 127 this 128 } 129 130 def isSoftPrefetch: Bool = { 131 fuType === FuType.alu.U && fuOpType === ALUOpType.or && selImm === SelImm.IMM_I && ldest === 0.U 132 } 133 134 def connectStaticInst(source: StaticInst): Unit = { 135 for ((name, data) <- this.elements) { 136 if (source.elements.contains(name)) { 137 data := source.elements(name) 138 } 139 } 140 } 141 } 142 143 // DecodedInst --[Rename]--> DynInst 144 class DynInst(implicit p: Parameters) extends XSBundle { 145 def numSrc = backendParams.numSrc 146 // passed from StaticInst 147 val instr = UInt(32.W) 148 val pc = UInt(VAddrBits.W) 149 val foldpc = UInt(MemPredPCWidth.W) 150 val exceptionVec = ExceptionVec() 151 val hasException = Bool() 152 val trigger = TriggerAction() 153 val preDecodeInfo = new PreDecodeInfo 154 val pred_taken = Bool() 155 val crossPageIPFFix = Bool() 156 val ftqPtr = new FtqPtr 157 val ftqOffset = UInt(log2Up(PredictWidth).W) 158 // passed from DecodedInst 159 val srcType = Vec(numSrc, SrcType()) 160 val ldest = UInt(LogicRegsWidth.W) 161 val fuType = FuType() 162 val fuOpType = FuOpType() 163 val rfWen = Bool() 164 val fpWen = Bool() 165 val vecWen = Bool() 166 val v0Wen = Bool() 167 val vlWen = Bool() 168 val isXSTrap = Bool() 169 val waitForward = Bool() // no speculate execution 170 val blockBackward = Bool() 171 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 172 val canRobCompress = Bool() 173 val selImm = SelImm() 174 val imm = UInt(32.W) 175 val fpu = new FPUCtrlSignals 176 val vpu = new VPUCtrlSignals 177 val vlsInstr = Bool() 178 val wfflags = Bool() 179 val isMove = Bool() 180 val uopIdx = UopIdx() 181 val isVset = Bool() 182 val firstUop = Bool() 183 val lastUop = Bool() 184 val numUops = UInt(log2Up(MaxUopSize).W) // rob need this 185 val numWB = UInt(log2Up(MaxUopSize).W) // rob need this 186 val commitType = CommitType() 187 // rename 188 val srcState = Vec(numSrc, SrcState()) 189 val srcLoadDependency = Vec(numSrc, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 190 val psrc = Vec(numSrc, UInt(PhyRegIdxWidth.W)) 191 val pdest = UInt(PhyRegIdxWidth.W) 192 // reg cache 193 val useRegCache = Vec(backendParams.numIntRegSrc, Bool()) 194 val regCacheIdx = Vec(backendParams.numIntRegSrc, UInt(RegCacheIdxWidth.W)) 195 val robIdx = new RobPtr 196 val instrSize = UInt(log2Ceil(RenameWidth + 1).W) 197 val dirtyFs = Bool() 198 val dirtyVs = Bool() 199 val traceBlockInPipe = new TracePipe(log2Up(RenameWidth * 2)) 200 201 val eliminatedMove = Bool() 202 // Take snapshot at this CFI inst 203 val snapshot = Bool() 204 val debugInfo = new PerfDebugInfo 205 val storeSetHit = Bool() // inst has been allocated an store set 206 val waitForRobIdx = new RobPtr // store set predicted previous store robIdx 207 // Load wait is needed 208 // load inst will not be executed until former store (predicted by mdp) addr calcuated 209 val loadWaitBit = Bool() 210 // If (loadWaitBit && loadWaitStrict), strict load wait is needed 211 // load inst will not be executed until ALL former store addr calcuated 212 val loadWaitStrict = Bool() 213 val ssid = UInt(SSIDWidth.W) 214 // Todo 215 val lqIdx = new LqPtr 216 val sqIdx = new SqPtr 217 // debug module 218 val singleStep = Bool() 219 // schedule 220 val replayInst = Bool() 221 222 val debug_fuType = OptionWrapper(backendParams.debugEn, FuType()) 223 224 val numLsElem = NumLsElem() 225 226 def getDebugFuType: UInt = debug_fuType.getOrElse(fuType) 227 228 def isLUI: Bool = this.fuType === FuType.alu.U && (this.selImm === SelImm.IMM_U || this.selImm === SelImm.IMM_LUI32) 229 def isLUI32: Bool = this.selImm === SelImm.IMM_LUI32 230 def isWFI: Bool = this.fuType === FuType.csr.U && fuOpType === CSROpType.wfi 231 232 def isSvinvalBegin(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && !flush 233 def isSvinval(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.sfence && !flush 234 def isSvinvalEnd(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && flush 235 def isNotSvinval = !FuType.isFence(fuType) 236 237 def isHls: Bool = { 238 fuType === FuType.ldu.U && LSUOpType.isHlv(fuOpType) || fuType === FuType.stu.U && LSUOpType.isHsv(fuOpType) 239 } 240 241 def srcIsReady: Vec[Bool] = { 242 VecInit(this.srcType.zip(this.srcState).map { 243 case (t, s) => SrcType.isNotReg(t) || SrcState.isReady(s) 244 }) 245 } 246 247 def clearExceptions( 248 exceptionBits: Seq[Int] = Seq(), 249 flushPipe : Boolean = false, 250 replayInst : Boolean = false 251 ): DynInst = { 252 this.exceptionVec.zipWithIndex.filterNot(x => exceptionBits.contains(x._2)).foreach(_._1 := false.B) 253 if (!flushPipe) { this.flushPipe := false.B } 254 if (!replayInst) { this.replayInst := false.B } 255 this 256 } 257 258 def needWriteRf: Bool = (rfWen && ldest =/= 0.U) || fpWen || vecWen || v0Wen || vlWen 259 } 260 261 trait BundleSource { 262 var wakeupSource = "undefined" 263 var idx = 0 264 } 265 266 /** 267 * 268 * @param pregIdxWidth index width of preg 269 * @param exuIndices exu indices of wakeup bundle 270 */ 271 sealed abstract class IssueQueueWakeUpBaseBundle(pregIdxWidth: Int, val exuIndices: Seq[Int])(implicit p: Parameters) extends XSBundle { 272 val rfWen = Bool() 273 val fpWen = Bool() 274 val vecWen = Bool() 275 val v0Wen = Bool() 276 val vlWen = Bool() 277 val pdest = UInt(pregIdxWidth.W) 278 279 /** 280 * @param successor Seq[(psrc, srcType)] 281 * @return Seq[if wakeup psrc] 282 */ 283 def wakeUp(successor: Seq[(UInt, UInt)], valid: Bool): Seq[Bool] = { 284 successor.map { case (thatPsrc, srcType) => 285 val pdestMatch = pdest === thatPsrc 286 pdestMatch && ( 287 SrcType.isFp(srcType) && this.fpWen || 288 SrcType.isXp(srcType) && this.rfWen || 289 SrcType.isVp(srcType) && this.vecWen 290 ) && valid 291 } 292 } 293 def wakeUpV0(successor: (UInt, UInt), valid: Bool): Bool = { 294 val (thatPsrc, srcType) = successor 295 val pdestMatch = pdest === thatPsrc 296 pdestMatch && ( 297 SrcType.isV0(srcType) && this.v0Wen 298 ) && valid 299 } 300 def wakeUpVl(successor: (UInt, UInt), valid: Bool): Bool = { 301 val (thatPsrc, srcType) = successor 302 val pdestMatch = pdest === thatPsrc 303 pdestMatch && ( 304 SrcType.isVp(srcType) && this.vlWen 305 ) && valid 306 } 307 def wakeUpFromIQ(successor: Seq[(UInt, UInt)]): Seq[Bool] = { 308 successor.map { case (thatPsrc, srcType) => 309 val pdestMatch = pdest === thatPsrc 310 pdestMatch && ( 311 SrcType.isFp(srcType) && this.fpWen || 312 SrcType.isXp(srcType) && this.rfWen || 313 SrcType.isVp(srcType) && this.vecWen 314 ) 315 } 316 } 317 def wakeUpV0FromIQ(successor: (UInt, UInt)): Bool = { 318 val (thatPsrc, srcType) = successor 319 val pdestMatch = pdest === thatPsrc 320 pdestMatch && ( 321 SrcType.isV0(srcType) && this.v0Wen 322 ) 323 } 324 def wakeUpVlFromIQ(successor: (UInt, UInt)): Bool = { 325 val (thatPsrc, srcType) = successor 326 val pdestMatch = pdest === thatPsrc 327 pdestMatch && ( 328 SrcType.isVp(srcType) && this.vlWen 329 ) 330 } 331 332 def hasOnlyOneSource: Boolean = exuIndices.size == 1 333 334 def hasMultiSources: Boolean = exuIndices.size > 1 335 336 def isWBWakeUp = this.isInstanceOf[IssueQueueWBWakeUpBundle] 337 338 def isIQWakeUp = this.isInstanceOf[IssueQueueIQWakeUpBundle] 339 340 def exuIdx: Int = { 341 require(hasOnlyOneSource) 342 this.exuIndices.head 343 } 344 } 345 346 class IssueQueueWBWakeUpBundle(exuIndices: Seq[Int], backendParams: BackendParams)(implicit p: Parameters) extends IssueQueueWakeUpBaseBundle(backendParams.pregIdxWidth, exuIndices) { 347 348 } 349 350 class IssueQueueIQWakeUpBundle( 351 exuIdx: Int, 352 backendParams: BackendParams, 353 copyWakeupOut: Boolean = false, 354 copyNum: Int = 0 355 )(implicit p: Parameters) extends IssueQueueWakeUpBaseBundle(backendParams.pregIdxWidth, Seq(exuIdx)) { 356 val loadDependency = Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W)) 357 val is0Lat = Bool() 358 val params = backendParams.allExuParams.filter(_.exuIdx == exuIdx).head 359 val rcDest = OptionWrapper(params.needWriteRegCache, UInt(RegCacheIdxWidth.W)) 360 val pdestCopy = OptionWrapper(copyWakeupOut, Vec(copyNum, UInt(params.wbPregIdxWidth.W))) 361 val rfWenCopy = OptionWrapper(copyWakeupOut && params.needIntWen, Vec(copyNum, Bool())) 362 val fpWenCopy = OptionWrapper(copyWakeupOut && params.needFpWen, Vec(copyNum, Bool())) 363 val vecWenCopy = OptionWrapper(copyWakeupOut && params.needVecWen, Vec(copyNum, Bool())) 364 val v0WenCopy = OptionWrapper(copyWakeupOut && params.needV0Wen, Vec(copyNum, Bool())) 365 val vlWenCopy = OptionWrapper(copyWakeupOut && params.needVlWen, Vec(copyNum, Bool())) 366 val loadDependencyCopy = OptionWrapper(copyWakeupOut && params.isIQWakeUpSink, Vec(copyNum, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W)))) 367 368 def fromExuInput(exuInput: ExuInput): Unit = { 369 this.rfWen := exuInput.rfWen.getOrElse(false.B) 370 this.fpWen := exuInput.fpWen.getOrElse(false.B) 371 this.vecWen := exuInput.vecWen.getOrElse(false.B) 372 this.v0Wen := exuInput.v0Wen.getOrElse(false.B) 373 this.vlWen := exuInput.vlWen.getOrElse(false.B) 374 this.pdest := exuInput.pdest 375 } 376 } 377 378 class VPUCtrlSignals(implicit p: Parameters) extends XSBundle { 379 // vtype 380 val vill = Bool() 381 val vma = Bool() // 1: agnostic, 0: undisturbed 382 val vta = Bool() // 1: agnostic, 0: undisturbed 383 val vsew = VSew() 384 val vlmul = VLmul() // 1/8~8 --> -3~3 385 386 // spec vtype 387 val specVill = Bool() 388 val specVma = Bool() // 1: agnostic, 0: undisturbed 389 val specVta = Bool() // 1: agnostic, 0: undisturbed 390 val specVsew = VSew() 391 val specVlmul = VLmul() // 1/8~8 --> -3~3 392 393 val vm = Bool() // 0: need v0.t 394 val vstart = Vl() 395 396 // float rounding mode 397 val frm = Frm() 398 // scalar float instr and vector float reduction 399 val fpu = Fpu() 400 // vector fix int rounding mode 401 val vxrm = Vxrm() 402 // vector uop index, exclude other non-vector uop 403 val vuopIdx = UopIdx() 404 val lastUop = Bool() 405 // maybe used if data dependancy 406 val vmask = UInt(V0Data().dataWidth.W) 407 val vl = Vl() 408 409 // vector load/store 410 val nf = Nf() 411 val veew = VEew() 412 413 val isReverse = Bool() // vrsub, vrdiv 414 val isExt = Bool() 415 val isNarrow = Bool() 416 val isDstMask = Bool() // vvm, vvvm, mmm 417 val isOpMask = Bool() // vmand, vmnand 418 val isMove = Bool() // vmv.s.x, vmv.v.v, vmv.v.x, vmv.v.i 419 420 val isDependOldvd = Bool() // some instruction's computation depends on oldvd 421 val isWritePartVd = Bool() // some instruction's computation writes part of vd, such as vredsum 422 423 def vtype: VType = { 424 val res = Wire(VType()) 425 res.illegal := this.vill 426 res.vma := this.vma 427 res.vta := this.vta 428 res.vsew := this.vsew 429 res.vlmul := this.vlmul 430 res 431 } 432 433 def specVType: VType = { 434 val res = Wire(VType()) 435 res.illegal := this.specVill 436 res.vma := this.specVma 437 res.vta := this.specVta 438 res.vsew := this.specVsew 439 res.vlmul := this.specVlmul 440 res 441 } 442 443 def vconfig: VConfig = { 444 val res = Wire(VConfig()) 445 res.vtype := this.vtype 446 res.vl := this.vl 447 res 448 } 449 450 def connectVType(source: VType): Unit = { 451 this.vill := source.illegal 452 this.vma := source.vma 453 this.vta := source.vta 454 this.vsew := source.vsew 455 this.vlmul := source.vlmul 456 } 457 } 458 459 class NeedFrmBundle(implicit p: Parameters) extends XSBundle { 460 val scalaNeedFrm = Bool() 461 val vectorNeedFrm = Bool() 462 } 463 464 // DynInst --[IssueQueue]--> DataPath 465 class IssueQueueIssueBundle( 466 iqParams: IssueBlockParams, 467 val exuParams: ExeUnitParams, 468 )(implicit 469 p: Parameters 470 ) extends XSBundle { 471 private val rfReadDataCfgSet: Seq[Set[DataConfig]] = exuParams.getRfReadDataCfgSet 472 473 val rf: MixedVec[MixedVec[RfReadPortWithConfig]] = Flipped(MixedVec( 474 rfReadDataCfgSet.map((set: Set[DataConfig]) => 475 MixedVec(set.map((x: DataConfig) => new RfReadPortWithConfig(x, exuParams.rdPregIdxWidth)).toSeq) 476 ) 477 )) 478 479 val srcType = Vec(exuParams.numRegSrc, SrcType()) // used to select imm or reg data 480 val rcIdx = OptionWrapper(exuParams.needReadRegCache, Vec(exuParams.numRegSrc, UInt(RegCacheIdxWidth.W))) // used to select regcache data 481 val immType = SelImm() // used to select imm extractor 482 val common = new ExuInput(exuParams) 483 val addrOH = UInt(iqParams.numEntries.W) 484 485 def exuIdx = exuParams.exuIdx 486 def getSource: SchedulerType = exuParams.getWBSource 487 488 def getRfReadValidBundle(issueValid: Bool): Seq[ValidIO[RfReadPortWithConfig]] = { 489 rf.zip(srcType).map { 490 case (rfRd: MixedVec[RfReadPortWithConfig], t: UInt) => 491 makeValid(issueValid, rfRd.head) 492 }.toSeq 493 } 494 } 495 496 class OGRespBundle(implicit p:Parameters, params: IssueBlockParams) extends XSBundle { 497 val issueQueueParams = this.params 498 val og0resp = Valid(new EntryDeqRespBundle) 499 val og1resp = Valid(new EntryDeqRespBundle) 500 } 501 502 class WbFuBusyTableWriteBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 503 private val intCertainLat = params.intLatencyCertain 504 private val fpCertainLat = params.fpLatencyCertain 505 private val vfCertainLat = params.vfLatencyCertain 506 private val v0CertainLat = params.v0LatencyCertain 507 private val vlCertainLat = params.vlLatencyCertain 508 private val intLat = params.intLatencyValMax 509 private val fpLat = params.fpLatencyValMax 510 private val vfLat = params.vfLatencyValMax 511 private val v0Lat = params.v0LatencyValMax 512 private val vlLat = params.vlLatencyValMax 513 514 val intWbBusyTable = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 515 val fpWbBusyTable = OptionWrapper(fpCertainLat, UInt((fpLat + 1).W)) 516 val vfWbBusyTable = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 517 val v0WbBusyTable = OptionWrapper(v0CertainLat, UInt((v0Lat + 1).W)) 518 val vlWbBusyTable = OptionWrapper(vlCertainLat, UInt((vlLat + 1).W)) 519 val intDeqRespSet = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 520 val fpDeqRespSet = OptionWrapper(fpCertainLat, UInt((fpLat + 1).W)) 521 val vfDeqRespSet = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 522 val v0DeqRespSet = OptionWrapper(v0CertainLat, UInt((v0Lat + 1).W)) 523 val vlDeqRespSet = OptionWrapper(vlCertainLat, UInt((vlLat + 1).W)) 524 } 525 526 class WbFuBusyTableReadBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 527 private val intCertainLat = params.intLatencyCertain 528 private val fpCertainLat = params.fpLatencyCertain 529 private val vfCertainLat = params.vfLatencyCertain 530 private val v0CertainLat = params.v0LatencyCertain 531 private val vlCertainLat = params.vlLatencyCertain 532 private val intLat = params.intLatencyValMax 533 private val fpLat = params.fpLatencyValMax 534 private val vfLat = params.vfLatencyValMax 535 private val v0Lat = params.v0LatencyValMax 536 private val vlLat = params.vlLatencyValMax 537 538 val intWbBusyTable = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 539 val fpWbBusyTable = OptionWrapper(fpCertainLat, UInt((fpLat + 1).W)) 540 val vfWbBusyTable = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 541 val v0WbBusyTable = OptionWrapper(v0CertainLat, UInt((v0Lat + 1).W)) 542 val vlWbBusyTable = OptionWrapper(vlCertainLat, UInt((vlLat + 1).W)) 543 } 544 545 class WbConflictBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 546 private val intCertainLat = params.intLatencyCertain 547 private val fpCertainLat = params.fpLatencyCertain 548 private val vfCertainLat = params.vfLatencyCertain 549 private val v0CertainLat = params.v0LatencyCertain 550 private val vlCertainLat = params.vlLatencyCertain 551 552 val intConflict = OptionWrapper(intCertainLat, Bool()) 553 val fpConflict = OptionWrapper(fpCertainLat, Bool()) 554 val vfConflict = OptionWrapper(vfCertainLat, Bool()) 555 val v0Conflict = OptionWrapper(v0CertainLat, Bool()) 556 val vlConflict = OptionWrapper(vlCertainLat, Bool()) 557 } 558 559 class ImmInfo extends Bundle { 560 val imm = UInt(32.W) 561 val immType = SelImm() 562 } 563 564 // DataPath --[ExuInput]--> Exu 565 class ExuInput(val params: ExeUnitParams, copyWakeupOut:Boolean = false, copyNum:Int = 0)(implicit p: Parameters) extends XSBundle { 566 val fuType = FuType() 567 val fuOpType = FuOpType() 568 val src = Vec(params.numRegSrc, UInt(params.srcDataBitsMax.W)) 569 val imm = UInt(32.W) 570 val robIdx = new RobPtr 571 val iqIdx = UInt(log2Up(MemIQSizeMax).W)// Only used by store yet 572 val isFirstIssue = Bool() // Only used by store yet 573 val pdestCopy = OptionWrapper(copyWakeupOut, Vec(copyNum, UInt(params.wbPregIdxWidth.W))) 574 val rfWenCopy = OptionWrapper(copyWakeupOut && params.needIntWen, Vec(copyNum, Bool())) 575 val fpWenCopy = OptionWrapper(copyWakeupOut && params.needFpWen, Vec(copyNum, Bool())) 576 val vecWenCopy = OptionWrapper(copyWakeupOut && params.needVecWen, Vec(copyNum, Bool())) 577 val v0WenCopy = OptionWrapper(copyWakeupOut && params.needV0Wen, Vec(copyNum, Bool())) 578 val vlWenCopy = OptionWrapper(copyWakeupOut && params.needVlWen, Vec(copyNum, Bool())) 579 val loadDependencyCopy = OptionWrapper(copyWakeupOut && params.isIQWakeUpSink, Vec(copyNum, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W)))) 580 val pdest = UInt(params.wbPregIdxWidth.W) 581 val rfWen = if (params.needIntWen) Some(Bool()) else None 582 val fpWen = if (params.needFpWen) Some(Bool()) else None 583 val vecWen = if (params.needVecWen) Some(Bool()) else None 584 val v0Wen = if (params.needV0Wen) Some(Bool()) else None 585 val vlWen = if (params.needVlWen) Some(Bool()) else None 586 val fpu = if (params.writeFflags) Some(new FPUCtrlSignals) else None 587 val vpu = if (params.needVPUCtrl) Some(new VPUCtrlSignals) else None 588 val flushPipe = if (params.flushPipe) Some(Bool()) else None 589 val pc = if (params.needPc) Some(UInt(VAddrData().dataWidth.W)) else None 590 val preDecode = if (params.hasPredecode) Some(new PreDecodeInfo) else None 591 val ftqIdx = if (params.needPc || params.replayInst || params.hasStoreAddrFu || params.hasCSR) 592 Some(new FtqPtr) else None 593 val ftqOffset = if (params.needPc || params.replayInst || params.hasStoreAddrFu || params.hasCSR) 594 Some(UInt(log2Up(PredictWidth).W)) else None 595 val predictInfo = if (params.needPdInfo) Some(new Bundle { 596 val target = UInt(VAddrData().dataWidth.W) 597 val taken = Bool() 598 }) else None 599 val loadWaitBit = OptionWrapper(params.hasLoadExu, Bool()) 600 val waitForRobIdx = OptionWrapper(params.hasLoadExu, new RobPtr) // store set predicted previous store robIdx 601 val storeSetHit = OptionWrapper(params.hasLoadExu, Bool()) // inst has been allocated an store set 602 val loadWaitStrict = OptionWrapper(params.hasLoadExu, Bool()) // load inst will not be executed until ALL former store addr calcuated 603 val ssid = OptionWrapper(params.hasLoadExu, UInt(SSIDWidth.W)) 604 // only vector load store need 605 val numLsElem = OptionWrapper(params.hasVecLsFu, NumLsElem()) 606 607 val sqIdx = if (params.hasMemAddrFu || params.hasStdFu) Some(new SqPtr) else None 608 val lqIdx = if (params.hasMemAddrFu) Some(new LqPtr) else None 609 val dataSources = Vec(params.numRegSrc, DataSource()) 610 val l1ExuOH = OptionWrapper(params.isIQWakeUpSink, Vec(params.numRegSrc, ExuVec())) 611 val srcTimer = OptionWrapper(params.isIQWakeUpSink, Vec(params.numRegSrc, UInt(3.W))) 612 val loadDependency = OptionWrapper(params.needLoadDependency, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 613 614 val perfDebugInfo = new PerfDebugInfo() 615 616 def exuIdx = this.params.exuIdx 617 618 def needCancel(og0CancelOH: UInt, og1CancelOH: UInt) : Bool = { 619 if (params.isIQWakeUpSink) { 620 require( 621 og0CancelOH.getWidth == l1ExuOH.get.head.getWidth, 622 s"cancelVecSize: {og0: ${og0CancelOH.getWidth}, og1: ${og1CancelOH.getWidth}}" 623 ) 624 val l1Cancel: Bool = l1ExuOH.get.zip(srcTimer.get).map { 625 case(exuOH: Vec[Bool], srcTimer: UInt) => 626 (exuOH.asUInt & og0CancelOH).orR && srcTimer === 1.U 627 }.reduce(_ | _) 628 l1Cancel 629 } else { 630 false.B 631 } 632 } 633 634 def fromIssueBundle(source: IssueQueueIssueBundle): Unit = { 635 // src is assigned to rfReadData 636 this.fuType := source.common.fuType 637 this.fuOpType := source.common.fuOpType 638 this.imm := source.common.imm 639 this.robIdx := source.common.robIdx 640 this.pdest := source.common.pdest 641 this.isFirstIssue := source.common.isFirstIssue // Only used by mem debug log 642 this.iqIdx := source.common.iqIdx // Only used by mem feedback 643 this.dataSources := source.common.dataSources 644 this.l1ExuOH .foreach(_ := source.common.l1ExuOH.get) 645 this.rfWen .foreach(_ := source.common.rfWen.get) 646 this.fpWen .foreach(_ := source.common.fpWen.get) 647 this.vecWen .foreach(_ := source.common.vecWen.get) 648 this.v0Wen .foreach(_ := source.common.v0Wen.get) 649 this.vlWen .foreach(_ := source.common.vlWen.get) 650 this.fpu .foreach(_ := source.common.fpu.get) 651 this.vpu .foreach(_ := source.common.vpu.get) 652 this.flushPipe .foreach(_ := source.common.flushPipe.get) 653 this.pc .foreach(_ := source.common.pc.get) 654 this.preDecode .foreach(_ := source.common.preDecode.get) 655 this.ftqIdx .foreach(_ := source.common.ftqIdx.get) 656 this.ftqOffset .foreach(_ := source.common.ftqOffset.get) 657 this.predictInfo .foreach(_ := source.common.predictInfo.get) 658 this.loadWaitBit .foreach(_ := source.common.loadWaitBit.get) 659 this.waitForRobIdx .foreach(_ := source.common.waitForRobIdx.get) 660 this.storeSetHit .foreach(_ := source.common.storeSetHit.get) 661 this.loadWaitStrict.foreach(_ := source.common.loadWaitStrict.get) 662 this.ssid .foreach(_ := source.common.ssid.get) 663 this.lqIdx .foreach(_ := source.common.lqIdx.get) 664 this.sqIdx .foreach(_ := source.common.sqIdx.get) 665 this.numLsElem .foreach(_ := source.common.numLsElem.get) 666 this.srcTimer .foreach(_ := source.common.srcTimer.get) 667 this.loadDependency.foreach(_ := source.common.loadDependency.get.map(_ << 1)) 668 } 669 } 670 671 // ExuInput --[FuncUnit]--> ExuOutput 672 class ExuOutput( 673 val params: ExeUnitParams, 674 )(implicit 675 val p: Parameters 676 ) extends Bundle with BundleSource with HasXSParameter { 677 val data = Vec(params.wbPathNum, UInt(params.destDataBitsMax.W)) 678 val pdest = UInt(params.wbPregIdxWidth.W) 679 val robIdx = new RobPtr 680 val intWen = if (params.needIntWen) Some(Bool()) else None 681 val fpWen = if (params.needFpWen) Some(Bool()) else None 682 val vecWen = if (params.needVecWen) Some(Bool()) else None 683 val v0Wen = if (params.needV0Wen) Some(Bool()) else None 684 val vlWen = if (params.needVlWen) Some(Bool()) else None 685 val redirect = if (params.hasRedirect) Some(ValidIO(new Redirect)) else None 686 val fflags = if (params.writeFflags) Some(UInt(5.W)) else None 687 val wflags = if (params.writeFflags) Some(Bool()) else None 688 val vxsat = if (params.writeVxsat) Some(Bool()) else None 689 val exceptionVec = if (params.exceptionOut.nonEmpty) Some(ExceptionVec()) else None 690 val flushPipe = if (params.flushPipe) Some(Bool()) else None 691 val replay = if (params.replayInst) Some(Bool()) else None 692 val lqIdx = if (params.hasLoadFu) Some(new LqPtr()) else None 693 val sqIdx = if (params.hasStoreAddrFu || params.hasStdFu) 694 Some(new SqPtr()) else None 695 val trigger = if (params.trigger) Some(TriggerAction()) else None 696 // uop info 697 val predecodeInfo = if(params.hasPredecode) Some(new PreDecodeInfo) else None 698 // vldu used only 699 val vls = OptionWrapper(params.hasVLoadFu, new Bundle { 700 val vpu = new VPUCtrlSignals 701 val oldVdPsrc = UInt(PhyRegIdxWidth.W) 702 val vdIdx = UInt(3.W) 703 val vdIdxInField = UInt(3.W) 704 val isIndexed = Bool() 705 val isMasked = Bool() 706 }) 707 val debug = new DebugBundle 708 val debugInfo = new PerfDebugInfo 709 } 710 711 // ExuOutput + DynInst --> WriteBackBundle 712 class WriteBackBundle(val params: PregWB, backendParams: BackendParams)(implicit p: Parameters) extends Bundle with BundleSource { 713 val rfWen = Bool() 714 val fpWen = Bool() 715 val vecWen = Bool() 716 val v0Wen = Bool() 717 val vlWen = Bool() 718 val pdest = UInt(params.pregIdxWidth(backendParams).W) 719 val data = UInt(params.dataWidth.W) 720 val robIdx = new RobPtr()(p) 721 val flushPipe = Bool() 722 val replayInst = Bool() 723 val redirect = ValidIO(new Redirect) 724 val fflags = UInt(5.W) 725 val vxsat = Bool() 726 val exceptionVec = ExceptionVec() 727 val debug = new DebugBundle 728 val debugInfo = new PerfDebugInfo 729 730 this.wakeupSource = s"WB(${params.toString})" 731 732 def fromExuOutput(source: ExuOutput, wbType: String) = { 733 val typeMap = Map("int" -> 0, "fp" -> 1, "vf" -> 2, "v0" -> 3, "vl" -> 4) 734 this.rfWen := source.intWen.getOrElse(false.B) 735 this.fpWen := source.fpWen.getOrElse(false.B) 736 this.vecWen := source.vecWen.getOrElse(false.B) 737 this.v0Wen := source.v0Wen.getOrElse(false.B) 738 this.vlWen := source.vlWen.getOrElse(false.B) 739 this.pdest := source.pdest 740 this.data := source.data(source.params.wbIndex(typeMap(wbType))) 741 this.robIdx := source.robIdx 742 this.flushPipe := source.flushPipe.getOrElse(false.B) 743 this.replayInst := source.replay.getOrElse(false.B) 744 this.redirect := source.redirect.getOrElse(0.U.asTypeOf(this.redirect)) 745 this.fflags := source.fflags.getOrElse(0.U.asTypeOf(this.fflags)) 746 this.vxsat := source.vxsat.getOrElse(0.U.asTypeOf(this.vxsat)) 747 this.exceptionVec := source.exceptionVec.getOrElse(0.U.asTypeOf(this.exceptionVec)) 748 this.debug := source.debug 749 this.debugInfo := source.debugInfo 750 } 751 752 def asIntRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 753 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(IntData()).addrWidth))) 754 rfWrite.wen := this.rfWen && fire 755 rfWrite.addr := this.pdest 756 rfWrite.data := this.data 757 rfWrite.intWen := this.rfWen 758 rfWrite.fpWen := false.B 759 rfWrite.vecWen := false.B 760 rfWrite.v0Wen := false.B 761 rfWrite.vlWen := false.B 762 rfWrite 763 } 764 765 def asFpRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 766 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(FpData()).addrWidth))) 767 rfWrite.wen := this.fpWen && fire 768 rfWrite.addr := this.pdest 769 rfWrite.data := this.data 770 rfWrite.intWen := false.B 771 rfWrite.fpWen := this.fpWen 772 rfWrite.vecWen := false.B 773 rfWrite.v0Wen := false.B 774 rfWrite.vlWen := false.B 775 rfWrite 776 } 777 778 def asVfRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 779 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(VecData()).addrWidth))) 780 rfWrite.wen := this.vecWen && fire 781 rfWrite.addr := this.pdest 782 rfWrite.data := this.data 783 rfWrite.intWen := false.B 784 rfWrite.fpWen := false.B 785 rfWrite.vecWen := this.vecWen 786 rfWrite.v0Wen := false.B 787 rfWrite.vlWen := false.B 788 rfWrite 789 } 790 791 def asV0RfWriteBundle(fire: Bool): RfWritePortWithConfig = { 792 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(V0Data()).addrWidth))) 793 rfWrite.wen := this.v0Wen && fire 794 rfWrite.addr := this.pdest 795 rfWrite.data := this.data 796 rfWrite.intWen := false.B 797 rfWrite.fpWen := false.B 798 rfWrite.vecWen := false.B 799 rfWrite.v0Wen := this.v0Wen 800 rfWrite.vlWen := false.B 801 rfWrite 802 } 803 804 def asVlRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 805 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(VlData()).addrWidth))) 806 rfWrite.wen := this.vlWen && fire 807 rfWrite.addr := this.pdest 808 rfWrite.data := this.data 809 rfWrite.intWen := false.B 810 rfWrite.fpWen := false.B 811 rfWrite.vecWen := false.B 812 rfWrite.v0Wen := false.B 813 rfWrite.vlWen := this.vlWen 814 rfWrite 815 } 816 } 817 818 // ExuOutput --> ExuBypassBundle --[DataPath]-->ExuInput 819 // / 820 // [IssueQueue]--> ExuInput -- 821 class ExuBypassBundle( 822 val params: ExeUnitParams, 823 )(implicit p: Parameters) extends XSBundle { 824 val intWen = Bool() 825 val data = UInt(params.destDataBitsMax.W) 826 val pdest = UInt(params.wbPregIdxWidth.W) 827 } 828 829 class ExceptionInfo(implicit p: Parameters) extends XSBundle { 830 val pc = UInt(VAddrData().dataWidth.W) 831 val instr = UInt(32.W) 832 val commitType = CommitType() 833 val exceptionVec = ExceptionVec() 834 val gpaddr = UInt(GPAddrBits.W) 835 val singleStep = Bool() 836 val crossPageIPFFix = Bool() 837 val isInterrupt = Bool() 838 val isHls = Bool() 839 val vls = Bool() 840 val trigger = TriggerAction() 841 } 842 843 object UopIdx { 844 def apply()(implicit p: Parameters): UInt = UInt(log2Up(p(XSCoreParamsKey).MaxUopSize + 1).W) 845 } 846 847 object FuLatency { 848 def apply(): UInt = UInt(width.W) 849 850 def width = 4 // 0~15 // Todo: assosiate it with FuConfig 851 } 852 853 object ExuOH { 854 def apply(exuNum: Int): UInt = UInt(exuNum.W) 855 856 def apply()(implicit p: Parameters): UInt = UInt(width.W) 857 858 def width(implicit p: Parameters): Int = p(XSCoreParamsKey).backendParams.numExu 859 } 860 861 object ExuVec { 862 def apply(exuNum: Int): Vec[Bool] = Vec(exuNum, Bool()) 863 864 def apply()(implicit p: Parameters): Vec[Bool] = Vec(width, Bool()) 865 866 def width(implicit p: Parameters): Int = p(XSCoreParamsKey).backendParams.numExu 867 } 868 869 class CancelSignal(implicit p: Parameters) extends XSBundle { 870 val rfWen = Bool() 871 val fpWen = Bool() 872 val vecWen = Bool() 873 val v0Wen = Bool() 874 val vlWen = Bool() 875 val pdest = UInt(PhyRegIdxWidth.W) 876 } 877 878 class MemExuInput(isVector: Boolean = false)(implicit p: Parameters) extends XSBundle { 879 val uop = new DynInst 880 val src = if (isVector) Vec(5, UInt(VLEN.W)) else Vec(3, UInt(XLEN.W)) 881 val iqIdx = UInt(log2Up(MemIQSizeMax).W) 882 val isFirstIssue = Bool() 883 val flowNum = OptionWrapper(isVector, NumLsElem()) 884 885 def src_rs1 = src(0) 886 def src_stride = src(1) 887 def src_vs3 = src(2) 888 def src_mask = if (isVector) src(3) else 0.U 889 def src_vl = if (isVector) src(4) else 0.U 890 } 891 892 class MemExuOutput(isVector: Boolean = false)(implicit p: Parameters) extends XSBundle { 893 val uop = new DynInst 894 val data = if (isVector) UInt(VLEN.W) else UInt(XLEN.W) 895 val mask = if (isVector) Some(UInt(VLEN.W)) else None 896 val vdIdx = if (isVector) Some(UInt(3.W)) else None // TODO: parameterize width 897 val vdIdxInField = if (isVector) Some(UInt(3.W)) else None 898 val debug = new DebugBundle 899 900 def isVls = FuType.isVls(uop.fuType) 901 } 902 903 class MemMicroOpRbExt(implicit p: Parameters) extends XSBundle { 904 val uop = new DynInst 905 val flag = UInt(1.W) 906 } 907 908 object LoadShouldCancel { 909 def apply(loadDependency: Option[Seq[UInt]], ldCancel: Seq[LoadCancelIO]): Bool = { 910 val ld1Cancel = loadDependency.map(_.zip(ldCancel.map(_.ld1Cancel)).map { case (dep, cancel) => cancel && dep(0)}.reduce(_ || _)) 911 val ld2Cancel = loadDependency.map(_.zip(ldCancel.map(_.ld2Cancel)).map { case (dep, cancel) => cancel && dep(1)}.reduce(_ || _)) 912 ld1Cancel.map(_ || ld2Cancel.get).getOrElse(false.B) 913 } 914 } 915} 916