1package xiangshan.backend 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util.BitPat.bitPatToUInt 6import chisel3.util._ 7import xiangshan._ 8import xiangshan.backend.datapath.DataConfig._ 9import xiangshan.backend.datapath.WbConfig.WbConfig 10import xiangshan.backend.decode.{ImmUnion, XDecode} 11import xiangshan.backend.exu.ExeUnitParams 12import xiangshan.backend.fu.FuType 13import xiangshan.backend.fu.fpu.Bundles.Frm 14import xiangshan.backend.fu.vector.Bundles.{Category, Nf, VConfig, VLmul, VSew, VType, Vl, Vxrm} 15import xiangshan.backend.issue.{IssueBlockParams, IssueQueueJumpBundle, SchedulerType, StatusArrayDeqRespBundle} 16import xiangshan.backend.regfile.{RfReadPortWithConfig, RfWritePortWithConfig} 17import xiangshan.backend.rob.RobPtr 18import xiangshan.frontend._ 19import xiangshan.mem.{LqPtr, SqPtr} 20 21object Bundles { 22 23 // frontend -> backend 24 class StaticInst(implicit p: Parameters) extends XSBundle { 25 val instr = UInt(32.W) 26 val pc = UInt(VAddrBits.W) 27 val foldpc = UInt(MemPredPCWidth.W) 28 val exceptionVec = ExceptionVec() 29 val trigger = new TriggerCf 30 val preDecodeInfo = new PreDecodeInfo 31 val pred_taken = Bool() 32 val crossPageIPFFix = Bool() 33 val ftqPtr = new FtqPtr 34 val ftqOffset = UInt(log2Up(PredictWidth).W) 35 36 def connectCtrlFlow(source: CtrlFlow): Unit = { 37 this.instr := source.instr 38 this.pc := source.pc 39 this.foldpc := source.foldpc 40 this.exceptionVec := source.exceptionVec 41 this.trigger := source.trigger 42 this.preDecodeInfo := source.pd 43 this.pred_taken := source.pred_taken 44 this.crossPageIPFFix := source.crossPageIPFFix 45 this.ftqPtr := source.ftqPtr 46 this.ftqOffset := source.ftqOffset 47 } 48 } 49 50 // StaticInst --[Decode]--> DecodedInst 51 class DecodedInst(implicit p: Parameters) extends XSBundle { 52 def numSrc = backendParams.numSrc 53 // passed from StaticInst 54 val instr = UInt(32.W) 55 val pc = UInt(VAddrBits.W) 56 val foldpc = UInt(MemPredPCWidth.W) 57 val exceptionVec = ExceptionVec() 58 val trigger = new TriggerCf 59 val preDecodeInfo = new PreDecodeInfo 60 val pred_taken = Bool() 61 val crossPageIPFFix = Bool() 62 val ftqPtr = new FtqPtr 63 val ftqOffset = UInt(log2Up(PredictWidth).W) 64 // decoded 65 val srcType = Vec(numSrc, SrcType()) 66 val lsrc = Vec(numSrc, UInt(6.W)) 67 val ldest = UInt(6.W) 68 val fuType = FuType() 69 val fuOpType = FuOpType() 70 val rfWen = Bool() 71 val fpWen = Bool() 72 val vecWen = Bool() 73 val isXSTrap = Bool() 74 val waitForward = Bool() // no speculate execution 75 val blockBackward = Bool() 76 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 77 val selImm = SelImm() 78 val imm = UInt(ImmUnion.maxLen.W) 79 val fpu = new FPUCtrlSignals 80 val vpu = new VPUCtrlSignals 81 val isMove = Bool() 82 val uopIdx = UInt(5.W) 83 val uopSplitType = UopSplitType() 84 val isVset = Bool() 85 val firstUop = Bool() 86 val lastUop = Bool() 87 val commitType = CommitType() // Todo: remove it 88 89 private def allSignals = srcType.take(3) ++ Seq(fuType, fuOpType, rfWen, fpWen, vecWen, 90 isXSTrap, waitForward, blockBackward, flushPipe, uopSplitType, selImm) 91 92 def decode(inst: UInt, table: Iterable[(BitPat, List[BitPat])]): DecodedInst = { 93 val decoder: Seq[UInt] = ListLookup( 94 inst, XDecode.decodeDefault.map(bitPatToUInt), 95 table.map{ case (pat, pats) => (pat, pats.map(bitPatToUInt)) }.toArray 96 ) 97 allSignals zip decoder foreach { case (s, d) => s := d } 98 this 99 } 100 101 def isSoftPrefetch: Bool = { 102 fuType === FuType.alu.U && fuOpType === ALUOpType.or && selImm === SelImm.IMM_I && ldest === 0.U 103 } 104 105 def connectStaticInst(source: StaticInst): Unit = { 106 for ((name, data) <- this.elements) { 107 if (source.elements.contains(name)) { 108 data := source.elements(name) 109 } 110 } 111 } 112 } 113 114 // DecodedInst --[Rename]--> DynInst 115 class DynInst(implicit p: Parameters) extends XSBundle { 116 def numSrc = backendParams.numSrc 117 // passed from StaticInst 118 val instr = UInt(32.W) 119 val pc = UInt(VAddrBits.W) 120 val foldpc = UInt(MemPredPCWidth.W) 121 val exceptionVec = ExceptionVec() 122 val trigger = new TriggerCf 123 val preDecodeInfo = new PreDecodeInfo 124 val pred_taken = Bool() 125 val crossPageIPFFix = Bool() 126 val ftqPtr = new FtqPtr 127 val ftqOffset = UInt(log2Up(PredictWidth).W) 128 // passed from DecodedInst 129 val srcType = Vec(numSrc, SrcType()) 130 val lsrc = Vec(numSrc, UInt(6.W)) 131 val ldest = UInt(6.W) 132 val fuType = FuType() 133 val fuOpType = FuOpType() 134 val rfWen = Bool() 135 val fpWen = Bool() 136 val vecWen = Bool() 137 val isXSTrap = Bool() 138 val waitForward = Bool() // no speculate execution 139 val blockBackward = Bool() 140 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 141 val selImm = SelImm() 142 val imm = UInt(XLEN.W) // Todo: check if it need minimized 143 val fpu = new FPUCtrlSignals 144 val vpu = new VPUCtrlSignals 145 val isMove = Bool() 146 val uopIdx = UInt(5.W) 147 val isVset = Bool() 148 val firstUop = Bool() 149 val lastUop = Bool() 150 val commitType = CommitType() 151 // rename 152 val srcState = Vec(numSrc, SrcState()) 153 val psrc = Vec(numSrc, UInt(PhyRegIdxWidth.W)) 154 val pdest = UInt(PhyRegIdxWidth.W) 155 val oldPdest = UInt(PhyRegIdxWidth.W) 156 val robIdx = new RobPtr 157 158 val eliminatedMove = Bool() 159 val debugInfo = new PerfDebugInfo 160 val storeSetHit = Bool() // inst has been allocated an store set 161 val waitForRobIdx = new RobPtr // store set predicted previous store robIdx 162 // Load wait is needed 163 // load inst will not be executed until former store (predicted by mdp) addr calcuated 164 val loadWaitBit = Bool() 165 // If (loadWaitBit && loadWaitStrict), strict load wait is needed 166 // load inst will not be executed until ALL former store addr calcuated 167 val loadWaitStrict = Bool() 168 val ssid = UInt(SSIDWidth.W) 169 // Todo 170 val lqIdx = new LqPtr 171 val sqIdx = new SqPtr 172 // debug module 173 val singleStep = Bool() 174 // schedule 175 val replayInst = Bool() 176 177 def isLUI: Bool = this.fuType === FuType.alu.U && this.selImm === SelImm.IMM_U 178 def isWFI: Bool = this.fuType === FuType.csr.U && fuOpType === CSROpType.wfi 179 180 def isSvinvalBegin(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && !flush 181 def isSvinval(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.sfence && !flush 182 def isSvinvalEnd(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && flush 183 184 def srcIsReady: Vec[Bool] = { 185 VecInit(this.srcType.zip(this.srcState).map { 186 case (t, s) => SrcType.isNotReg(t) || SrcState.isReady(s) 187 }) 188 } 189 190 def clearExceptions( 191 exceptionBits: Seq[Int] = Seq(), 192 flushPipe : Boolean = false, 193 replayInst : Boolean = false 194 ): DynInst = { 195 this.exceptionVec.zipWithIndex.filterNot(x => exceptionBits.contains(x._2)).foreach(_._1 := false.B) 196 if (!flushPipe) { this.flushPipe := false.B } 197 if (!replayInst) { this.replayInst := false.B } 198 this 199 } 200 201 def asWakeUpBundle: IssueQueueWakeUpBundle = { 202 val wakeup = Output(new IssueQueueWakeUpBundle(pdest.getWidth)) 203 wakeup.rfWen := this.rfWen 204 wakeup.fpWen := this.fpWen 205 wakeup.vecWen := this.vecWen 206 wakeup.pdest := this.pdest 207 wakeup 208 } 209 210 def needWriteRf: Bool = (rfWen && ldest =/= 0.U) || fpWen || vecWen 211 } 212 213 trait BundleSource { 214 var source = "not exist" 215 } 216 217 class IssueQueueWakeUpBundle(PregIdxWidth: Int) extends Bundle with BundleSource { 218 val rfWen = Bool() 219 val fpWen = Bool() 220 val vecWen = Bool() 221 val pdest = UInt(PregIdxWidth.W) 222 223 /** 224 * @param successor Seq[(psrc, srcType)] 225 * @return Seq[if wakeup psrc] 226 */ 227 def wakeUp(successor: Seq[(UInt, UInt)], valid: Bool): Seq[Bool]= { 228 successor.map { case (thatPsrc, srcType) => 229 val pdestMatch = pdest === thatPsrc 230 pdestMatch && ( 231 SrcType.isFp(srcType) && this.fpWen || 232 SrcType.isXp(srcType) && this.rfWen || 233 SrcType.isVp(srcType) && this.vecWen 234 ) && valid 235 } 236 } 237 } 238 239 class VPUCtrlSignals(implicit p: Parameters) extends XSBundle { 240 // vtype 241 val vill = Bool() 242 val vma = Bool() // 1: agnostic, 0: undisturbed 243 val vta = Bool() // 1: agnostic, 0: undisturbed 244 val vsew = VSew() 245 val vlmul = VLmul() // 1/8~8 --> -3~3 246 247 val vm = Bool() // 0: need v0.t 248 val vstart = Vl() 249 250 // float rounding mode 251 val frm = Frm() 252 // vector fix int rounding mode 253 val vxrm = Vxrm() 254 // vector uop index, exclude other non-vector uop 255 val vuopIdx = UInt(log2Up(p(XSCoreParamsKey).MaxUopSize).W) 256 // maybe used if data dependancy 257 val vmask = UInt(MaskSrcData().dataWidth.W) 258 val vl = Vl() 259 260 // vector load/store 261 val nf = Nf() 262 263 val needScalaSrc = Bool() 264 265 val isReverse = Bool() // vrsub, vrdiv 266 val isExt = Bool() 267 val isNarrow = Bool() 268 val isDstMask = Bool() // vvm, vvvm, mmm 269 val isMove = Bool() // vmv.s.x, vmv.v.v, vmv.v.x, vmv.v.i 270 271 def vtype: VType = { 272 val res = Wire(VType()) 273 res.illegal := this.vill 274 res.vma := this.vma 275 res.vta := this.vta 276 res.vsew := this.vsew 277 res.vlmul := this.vlmul 278 res 279 } 280 281 def vconfig: VConfig = { 282 val res = Wire(VConfig()) 283 res.vtype := this.vtype 284 res.vl := this.vl 285 res 286 } 287 } 288 289 // DynInst --[IssueQueue]--> DataPath 290 class IssueQueueIssueBundle( 291 iqParams: IssueBlockParams, 292 exuParams: ExeUnitParams, 293 addrWidth: Int, 294 vaddrBits: Int 295 )(implicit 296 p: Parameters 297 ) extends Bundle { 298 private val rfReadDataCfgSet: Seq[Set[DataConfig]] = exuParams.getRfReadDataCfgSet 299 300 val rf: MixedVec[MixedVec[RfReadPortWithConfig]] = Flipped(MixedVec( 301 rfReadDataCfgSet.map((set: Set[DataConfig]) => 302 MixedVec(set.map((x: DataConfig) => new RfReadPortWithConfig(x, addrWidth)).toSeq) 303 ) 304 )) 305 val srcType = Vec(exuParams.numRegSrc, SrcType()) // used to select imm or reg data 306 val immType = SelImm() // used to select imm extractor 307 val common = new ExuInput(exuParams) 308 val jmp = if (exuParams.needPc) Some(Flipped(new IssueQueueJumpBundle)) else None 309 val addrOH = UInt(iqParams.numEntries.W) 310 311 def getSource: SchedulerType = exuParams.getWBSource 312 def getIntRfReadBundle: Seq[RfReadPortWithConfig] = rf.flatten.filter(_.readInt) 313 def getVfRfReadBundle: Seq[RfReadPortWithConfig] = rf.flatten.filter(_.readVf) 314 } 315 316 class OGRespBundle(implicit p:Parameters, params: IssueBlockParams) extends XSBundle { 317 val og0resp = Valid(new StatusArrayDeqRespBundle) 318 val og1resp = Valid(new StatusArrayDeqRespBundle) 319 } 320 321 // DataPath --[ExuInput]--> Exu 322 class ExuInput(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 323 val fuType = FuType() 324 val fuOpType = FuOpType() 325 val src = Vec(params.numRegSrc, UInt(params.dataBitsMax.W)) 326 val imm = UInt(XLEN.W) 327 val robIdx = new RobPtr 328 val iqIdx = UInt(log2Up(MemIQSizeMax).W)// Only used by store yet 329 val isFirstIssue = Bool() // Only used by store yet 330 val pdest = UInt(params.wbPregIdxWidth.W) 331 val rfWen = if (params.writeIntRf) Some(Bool()) else None 332 val fpWen = if (params.writeFpRf) Some(Bool()) else None 333 val vecWen = if (params.writeVecRf) Some(Bool()) else None 334 val fpu = if (params.needFPUCtrl) Some(new FPUCtrlSignals) else None 335 val vpu = if (params.needVPUCtrl) Some(new VPUCtrlSignals) else None 336 val flushPipe = if (params.flushPipe) Some(Bool()) else None 337 val pc = if (params.needPc) Some(UInt(VAddrData().dataWidth.W)) else None 338 val jalrTarget = if (params.hasJmpFu) Some(UInt(VAddrData().dataWidth.W)) else None 339 val preDecode = if (params.hasPredecode) Some(new PreDecodeInfo) else None 340 val ftqIdx = if (params.needPc || params.replayInst) 341 Some(new FtqPtr) else None 342 val ftqOffset = if (params.needPc || params.replayInst) 343 Some(UInt(log2Up(PredictWidth).W)) else None 344 val predictInfo = if (params.hasPredecode) Some(new Bundle { 345 val target = UInt(VAddrData().dataWidth.W) 346 val taken = Bool() 347 }) else None 348 val sqIdx = if (params.hasMemAddrFu || params.hasStdFu) Some(new SqPtr) else None 349 val lqIdx = if (params.hasMemAddrFu) Some(new LqPtr) else None 350 351 def fromIssueBundle(source: IssueQueueIssueBundle): Unit = { 352 // src is assigned to rfReadData 353 this.fuType := source.common.fuType 354 this.fuOpType := source.common.fuOpType 355 this.imm := source.common.imm 356 this.robIdx := source.common.robIdx 357 this.pdest := source.common.pdest 358 this.isFirstIssue := source.common.isFirstIssue // Only used by mem debug log 359 this.iqIdx := source.common.iqIdx // Only used by mem feedback 360 this.rfWen .foreach(_ := source.common.rfWen.get) 361 this.fpWen .foreach(_ := source.common.fpWen.get) 362 this.vecWen .foreach(_ := source.common.vecWen.get) 363 this.fpu .foreach(_ := source.common.fpu.get) 364 this.vpu .foreach(_ := source.common.vpu.get) 365 this.flushPipe .foreach(_ := source.common.flushPipe.get) 366 this.pc .foreach(_ := source.jmp.get.pc) 367 this.jalrTarget .foreach(_ := source.jmp.get.target) 368 this.preDecode .foreach(_ := source.common.preDecode.get) 369 this.ftqIdx .foreach(_ := source.common.ftqIdx.get) 370 this.ftqOffset .foreach(_ := source.common.ftqOffset.get) 371 this.predictInfo .foreach(_ := source.common.predictInfo.get) 372 this.lqIdx .foreach(_ := source.common.lqIdx.get) 373 this.sqIdx .foreach(_ := source.common.sqIdx.get) 374 } 375 } 376 377 // ExuInput --[FuncUnit]--> ExuOutput 378 class ExuOutput( 379 val params: ExeUnitParams, 380 )(implicit 381 val p: Parameters 382 ) extends Bundle with BundleSource with HasXSParameter { 383 val data = UInt(params.dataBitsMax.W) 384 val pdest = UInt(params.wbPregIdxWidth.W) 385 val robIdx = new RobPtr 386 val intWen = if (params.writeIntRf) Some(Bool()) else None 387 val fpWen = if (params.writeFpRf) Some(Bool()) else None 388 val vecWen = if (params.writeVecRf) Some(Bool()) else None 389 val redirect = if (params.hasRedirect) Some(ValidIO(new Redirect)) else None 390 val fflags = if (params.writeFflags) Some(UInt(5.W)) else None 391 val vxsat = if (params.writeVxsat) Some(Bool()) else None 392 val exceptionVec = if (params.exceptionOut.nonEmpty) Some(ExceptionVec()) else None 393 val flushPipe = if (params.flushPipe) Some(Bool()) else None 394 val replay = if (params.replayInst) Some(Bool()) else None 395 val lqIdx = if (params.hasLoadFu) Some(new LqPtr()) else None 396 val sqIdx = if (params.hasStoreAddrFu || params.hasStdFu) 397 Some(new SqPtr()) else None 398 val ftqIdx = if (params.needPc || params.replayInst) 399 Some(new FtqPtr) else None 400 val ftqOffset = if (params.needPc || params.replayInst) 401 Some(UInt(log2Up(PredictWidth).W)) else None 402 // uop info 403 val predecodeInfo = if(params.hasPredecode) Some(new PreDecodeInfo) else None 404 val debug = new DebugBundle 405 val debugInfo = new PerfDebugInfo 406 } 407 408 // ExuOutput + DynInst --> WriteBackBundle 409 class WriteBackBundle(val params: WbConfig)(implicit p: Parameters) extends Bundle with BundleSource { 410 val rfWen = Bool() 411 val fpWen = Bool() 412 val vecWen = Bool() 413 val pdest = UInt(params.pregIdxWidth.W) 414 val data = UInt(params.dataWidth.W) 415 val robIdx = new RobPtr()(p) 416 val flushPipe = Bool() 417 val replayInst = Bool() 418 val redirect = ValidIO(new Redirect) 419 val fflags = UInt(5.W) 420 val exceptionVec = ExceptionVec() 421 val debug = new DebugBundle 422 val debugInfo = new PerfDebugInfo 423 424 def fromExuOutput(source: ExuOutput) = { 425 this.rfWen := source.intWen.getOrElse(false.B) 426 this.fpWen := source.fpWen.getOrElse(false.B) 427 this.vecWen := source.vecWen.getOrElse(false.B) 428 this.pdest := source.pdest 429 this.data := source.data 430 this.robIdx := source.robIdx 431 this.flushPipe := source.flushPipe.getOrElse(false.B) 432 this.replayInst := source.replay.getOrElse(false.B) 433 this.redirect := source.redirect.getOrElse(0.U.asTypeOf(this.redirect)) 434 this.fflags := source.fflags.getOrElse(0.U.asTypeOf(this.fflags)) 435 this.exceptionVec := source.exceptionVec.getOrElse(0.U.asTypeOf(this.exceptionVec)) 436 this.debug := source.debug 437 this.debugInfo := source.debugInfo 438 } 439 440 def asWakeUpBundle: IssueQueueWakeUpBundle = { 441 val wakeup = Output(new IssueQueueWakeUpBundle(params.pregIdxWidth)) 442 wakeup.rfWen := this.rfWen 443 wakeup.fpWen := this.fpWen 444 wakeup.vecWen := this.vecWen 445 wakeup.pdest := this.pdest 446 wakeup.source = this.source 447 wakeup 448 } 449 450 def asIntRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 451 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, this.params.pregIdxWidth))) 452 rfWrite.wen := this.rfWen && fire 453 rfWrite.addr := this.pdest 454 rfWrite.data := this.data 455 rfWrite.intWen := this.rfWen 456 rfWrite.fpWen := false.B 457 rfWrite.vecWen := false.B 458 rfWrite 459 } 460 461 def asVfRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 462 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, this.params.pregIdxWidth))) 463 rfWrite.wen := (this.fpWen || this.vecWen) && fire 464 rfWrite.addr := this.pdest 465 rfWrite.data := this.data 466 rfWrite.intWen := false.B 467 rfWrite.fpWen := this.fpWen 468 rfWrite.vecWen := this.vecWen 469 rfWrite 470 } 471 } 472 473 class ExceptionInfo extends Bundle { 474 val pc = UInt(VAddrData().dataWidth.W) 475 val instr = UInt(32.W) 476 val commitType = CommitType() 477 val exceptionVec = ExceptionVec() 478 val singleStep = Bool() 479 val crossPageIPFFix = Bool() 480 val isInterrupt = Bool() 481 } 482 483 class MemExuInput(implicit p: Parameters) extends XSBundle { 484 val uop = new DynInst 485 val src = Vec(3, UInt(XLEN.W)) 486 val iqIdx = UInt(log2Up(MemIQSizeMax).W) 487 val isFirstIssue = Bool() 488 } 489 490 class MemExuOutput(implicit p: Parameters) extends XSBundle { 491 val uop = new DynInst 492 val data = UInt(XLEN.W) 493 val debug = new DebugBundle 494 } 495 496 class MemMicroOpRbExt(implicit p: Parameters) extends XSBundle { 497 val uop = new DynInst 498 val flag = UInt(1.W) 499 } 500} 501