1package xiangshan.backend 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util.BitPat.bitPatToUInt 6import chisel3.util._ 7import xiangshan._ 8import xiangshan.backend.datapath.DataConfig._ 9import xiangshan.backend.datapath.WbConfig.WbConfig 10import xiangshan.backend.decode.{ImmUnion, XDecode} 11import xiangshan.backend.exu.ExeUnitParams 12import xiangshan.backend.fu.FuType 13import xiangshan.backend.fu.fpu.Bundles.Frm 14import xiangshan.backend.fu.vector.Bundles.{Nf, VConfig, VLmul, VSew, VType, Vl, Vxrm} 15import xiangshan.backend.issue.{IssueBlockParams, IssueQueueJumpBundle, SchedulerType, StatusArrayDeqRespBundle} 16import xiangshan.backend.regfile.{RfReadPortWithConfig, RfWritePortWithConfig} 17import xiangshan.backend.rob.RobPtr 18import xiangshan.frontend._ 19import xiangshan.mem.{LqPtr, SqPtr} 20 21object Bundles { 22 23 // frontend -> backend 24 class StaticInst(implicit p: Parameters) extends XSBundle { 25 val instr = UInt(32.W) 26 val pc = UInt(VAddrBits.W) 27 val foldpc = UInt(MemPredPCWidth.W) 28 val exceptionVec = ExceptionVec() 29 val trigger = new TriggerCf 30 val preDecodeInfo = new PreDecodeInfo 31 val pred_taken = Bool() 32 val crossPageIPFFix = Bool() 33 val ftqPtr = new FtqPtr 34 val ftqOffset = UInt(log2Up(PredictWidth).W) 35 36 def connectCtrlFlow(source: CtrlFlow): Unit = { 37 this.instr := source.instr 38 this.pc := source.pc 39 this.foldpc := source.foldpc 40 this.exceptionVec := source.exceptionVec 41 this.trigger := source.trigger 42 this.preDecodeInfo := source.pd 43 this.pred_taken := source.pred_taken 44 this.crossPageIPFFix := source.crossPageIPFFix 45 this.ftqPtr := source.ftqPtr 46 this.ftqOffset := source.ftqOffset 47 } 48 } 49 50 // StaticInst --[Decode]--> DecodedInst 51 class DecodedInst(implicit p: Parameters) extends XSBundle { 52 def numSrc = backendParams.numSrc 53 // passed from StaticInst 54 val instr = UInt(32.W) 55 val pc = UInt(VAddrBits.W) 56 val foldpc = UInt(MemPredPCWidth.W) 57 val exceptionVec = ExceptionVec() 58 val trigger = new TriggerCf 59 val preDecodeInfo = new PreDecodeInfo 60 val pred_taken = Bool() 61 val crossPageIPFFix = Bool() 62 val ftqPtr = new FtqPtr 63 val ftqOffset = UInt(log2Up(PredictWidth).W) 64 // decoded 65 val srcType = Vec(numSrc, SrcType()) 66 val lsrc = Vec(numSrc, UInt(6.W)) 67 val ldest = UInt(6.W) 68 val fuType = FuType() 69 val fuOpType = FuOpType() 70 val rfWen = Bool() 71 val fpWen = Bool() 72 val vecWen = Bool() 73 val isXSTrap = Bool() 74 val waitForward = Bool() // no speculate execution 75 val blockBackward = Bool() 76 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 77 val selImm = SelImm() 78 val imm = UInt(ImmUnion.maxLen.W) 79 val fpu = new FPUCtrlSignals 80 val vpu = new VPUCtrlSignals 81 val isMove = Bool() 82 val uopIdx = UInt(5.W) 83 val uopSplitType = UopSplitType() 84 val isVset = Bool() 85 val firstUop = Bool() 86 val lastUop = Bool() 87 val commitType = CommitType() // Todo: remove it 88 89 private def allSignals = srcType.take(3) ++ Seq(fuType, fuOpType, rfWen, fpWen, vecWen, 90 isXSTrap, waitForward, blockBackward, flushPipe, uopSplitType, selImm) 91 92 def decode(inst: UInt, table: Iterable[(BitPat, List[BitPat])]): DecodedInst = { 93 val decoder: Seq[UInt] = ListLookup( 94 inst, XDecode.decodeDefault.map(bitPatToUInt), 95 table.map{ case (pat, pats) => (pat, pats.map(bitPatToUInt)) }.toArray 96 ) 97 allSignals zip decoder foreach { case (s, d) => s := d } 98 this 99 } 100 101 def isSoftPrefetch: Bool = { 102 fuType === FuType.alu.U && fuOpType === ALUOpType.or && selImm === SelImm.IMM_I && ldest === 0.U 103 } 104 105 def connectStaticInst(source: StaticInst): Unit = { 106 for ((name, data) <- this.elements) { 107 if (source.elements.contains(name)) { 108 data := source.elements(name) 109 } 110 } 111 } 112 } 113 114 // DecodedInst --[Rename]--> DynInst 115 class DynInst(implicit p: Parameters) extends XSBundle { 116 def numSrc = backendParams.numSrc 117 // passed from StaticInst 118 val instr = UInt(32.W) 119 val pc = UInt(VAddrBits.W) 120 val foldpc = UInt(MemPredPCWidth.W) 121 val exceptionVec = ExceptionVec() 122 val trigger = new TriggerCf 123 val preDecodeInfo = new PreDecodeInfo 124 val pred_taken = Bool() 125 val crossPageIPFFix = Bool() 126 val ftqPtr = new FtqPtr 127 val ftqOffset = UInt(log2Up(PredictWidth).W) 128 // passed from DecodedInst 129 val srcType = Vec(numSrc, SrcType()) 130 val lsrc = Vec(numSrc, UInt(6.W)) 131 val ldest = UInt(6.W) 132 val fuType = FuType() 133 val fuOpType = FuOpType() 134 val rfWen = Bool() 135 val fpWen = Bool() 136 val vecWen = Bool() 137 val isXSTrap = Bool() 138 val waitForward = Bool() // no speculate execution 139 val blockBackward = Bool() 140 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 141 val selImm = SelImm() 142 val imm = UInt(XLEN.W) // Todo: check if it need minimized 143 val fpu = new FPUCtrlSignals 144 val vpu = new VPUCtrlSignals 145 val isMove = Bool() 146 val uopIdx = UInt(5.W) 147 val isVset = Bool() 148 val firstUop = Bool() 149 val lastUop = Bool() 150 val commitType = CommitType() 151 // rename 152 val srcState = Vec(numSrc, SrcState()) 153 val psrc = Vec(numSrc, UInt(PhyRegIdxWidth.W)) 154 val pdest = UInt(PhyRegIdxWidth.W) 155 val oldPdest = UInt(PhyRegIdxWidth.W) 156 val robIdx = new RobPtr 157 158 val eliminatedMove = Bool() 159 val debugInfo = new PerfDebugInfo 160 val storeSetHit = Bool() // inst has been allocated an store set 161 val waitForRobIdx = new RobPtr // store set predicted previous store robIdx 162 // Load wait is needed 163 // load inst will not be executed until former store (predicted by mdp) addr calcuated 164 val loadWaitBit = Bool() 165 // If (loadWaitBit && loadWaitStrict), strict load wait is needed 166 // load inst will not be executed until ALL former store addr calcuated 167 val loadWaitStrict = Bool() 168 val ssid = UInt(SSIDWidth.W) 169 // Todo 170 val lqIdx = new LqPtr 171 val sqIdx = new SqPtr 172 // debug module 173 val singleStep = Bool() 174 // schedule 175 val replayInst = Bool() 176 177 def isLUI: Bool = this.fuType === FuType.alu.U && this.selImm === SelImm.IMM_U 178 def isWFI: Bool = this.fuType === FuType.csr.U && fuOpType === CSROpType.wfi 179 180 def isSvinvalBegin(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && !flush 181 def isSvinval(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.sfence && !flush 182 def isSvinvalEnd(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && flush 183 184 def srcIsReady: Vec[Bool] = { 185 VecInit(this.srcType.zip(this.srcState).map { 186 case (t, s) => SrcType.isNotReg(t) || SrcState.isReady(s) 187 }) 188 } 189 190 def clearExceptions( 191 exceptionBits: Seq[Int] = Seq(), 192 flushPipe : Boolean = false, 193 replayInst : Boolean = false 194 ): DynInst = { 195 this.exceptionVec.zipWithIndex.filterNot(x => exceptionBits.contains(x._2)).foreach(_._1 := false.B) 196 if (!flushPipe) { this.flushPipe := false.B } 197 if (!replayInst) { this.replayInst := false.B } 198 this 199 } 200 201 def asWakeUpBundle: IssueQueueWakeUpBundle = { 202 val wakeup = Output(new IssueQueueWakeUpBundle(pdest.getWidth)) 203 wakeup.rfWen := this.rfWen 204 wakeup.fpWen := this.fpWen 205 wakeup.vecWen := this.vecWen 206 wakeup.pdest := this.pdest 207 wakeup 208 } 209 210 def needWriteRf: Bool = (rfWen && ldest =/= 0.U) || fpWen || vecWen 211 } 212 213 trait BundleSource { 214 var source = "not exist" 215 } 216 217 class IssueQueueWakeUpBundle(PregIdxWidth: Int) extends Bundle with BundleSource { 218 val rfWen = Bool() 219 val fpWen = Bool() 220 val vecWen = Bool() 221 val pdest = UInt(PregIdxWidth.W) 222 223 /** 224 * @param successor Seq[(psrc, srcType)] 225 * @return Seq[if wakeup psrc] 226 */ 227 def wakeUp(successor: Seq[(UInt, UInt)], valid: Bool): Seq[Bool]= { 228 successor.map { case (thatPsrc, srcType) => 229 val pdestMatch = pdest === thatPsrc 230 pdestMatch && ( 231 SrcType.isFp(srcType) && this.fpWen || 232 SrcType.isXp(srcType) && this.rfWen || 233 SrcType.isVp(srcType) && this.vecWen 234 ) && valid 235 } 236 } 237 } 238 239 object VsewBundle { 240 def apply() = UInt(2.W) // 8/16/32/64 --> 0/1/2/3 241 } 242 243 class VPUCtrlSignals(implicit p: Parameters) extends XSBundle { 244 // vtype 245 val vill = Bool() 246 val vma = Bool() // 1: agnostic, 0: undisturbed 247 val vta = Bool() // 1: agnostic, 0: undisturbed 248 val vsew = VSew() 249 val vlmul = VLmul() // 1/8~8 --> -3~3 250 251 val vm = Bool() // 0: need v0.t 252 val vstart = Vl() 253 254 // float rounding mode 255 val frm = Frm() 256 // vector fix int rounding mode 257 val vxrm = Vxrm() 258 // vector uop index, exclude other non-vector uop 259 val vuopIdx = UInt(log2Up(p(XSCoreParamsKey).MaxUopSize).W) 260 // maybe used if data dependancy 261 val vmask = UInt(MaskSrcData().dataWidth.W) 262 val vl = Vl() 263 264 // vector load/store 265 val nf = Nf() 266 267 val isReverse = Bool() // vrsub, vrdiv 268 val isExt = Bool() 269 val isNarrow = Bool() 270 val isDstMask = Bool() // vvm, vvvm, mmm 271 val isMove = Bool() // vmv.s.x, vmv.v.v, vmv.v.x, vmv.v.i 272 273 def vtype: VType = { 274 val res = Wire(VType()) 275 res.illegal := this.vill 276 res.vma := this.vma 277 res.vta := this.vta 278 res.vsew := this.vsew 279 res.vlmul := this.vlmul 280 res 281 } 282 283 def vconfig: VConfig = { 284 val res = Wire(VConfig()) 285 res.vtype := this.vtype 286 res.vl := this.vl 287 res 288 } 289 } 290 291 // DynInst --[IssueQueue]--> DataPath 292 class IssueQueueIssueBundle( 293 iqParams: IssueBlockParams, 294 exuParams: ExeUnitParams, 295 addrWidth: Int, 296 vaddrBits: Int 297 )(implicit 298 p: Parameters 299 ) extends Bundle { 300 private val rfReadDataCfgSet: Seq[Set[DataConfig]] = exuParams.getRfReadDataCfgSet 301 302 val rf: MixedVec[MixedVec[RfReadPortWithConfig]] = Flipped(MixedVec( 303 rfReadDataCfgSet.map((set: Set[DataConfig]) => 304 MixedVec(set.map((x: DataConfig) => new RfReadPortWithConfig(x, addrWidth)).toSeq) 305 ) 306 )) 307 val srcType = Vec(exuParams.numRegSrc, SrcType()) // used to select imm or reg data 308 val immType = SelImm() // used to select imm extractor 309 val common = new ExuInput(exuParams) 310 val jmp = if (exuParams.needPc) Some(Flipped(new IssueQueueJumpBundle)) else None 311 val addrOH = UInt(iqParams.numEntries.W) 312 313 def getSource: SchedulerType = exuParams.getWBSource 314 def getIntRfReadBundle: Seq[RfReadPortWithConfig] = rf.flatten.filter(_.readInt) 315 def getVfRfReadBundle: Seq[RfReadPortWithConfig] = rf.flatten.filter(_.readVf) 316 } 317 318 class OGRespBundle(implicit p:Parameters, params: IssueBlockParams) extends XSBundle { 319 val og0resp = Valid(new StatusArrayDeqRespBundle) 320 val og1resp = Valid(new StatusArrayDeqRespBundle) 321 } 322 323 // DataPath --[ExuInput]--> Exu 324 class ExuInput(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 325 val fuType = FuType() 326 val fuOpType = FuOpType() 327 val src = Vec(params.numRegSrc, UInt(params.dataBitsMax.W)) 328 val imm = UInt(XLEN.W) 329 val robIdx = new RobPtr 330 val iqIdx = UInt(log2Up(MemIQSizeMax).W)// Only used by store yet 331 val isFirstIssue = Bool() // Only used by store yet 332 val pdest = UInt(params.wbPregIdxWidth.W) 333 val rfWen = if (params.writeIntRf) Some(Bool()) else None 334 val fpWen = if (params.writeFpRf) Some(Bool()) else None 335 val vecWen = if (params.writeVecRf) Some(Bool()) else None 336 val fpu = if (params.needFPUCtrl) Some(new FPUCtrlSignals) else None 337 val vpu = if (params.needVPUCtrl) Some(new VPUCtrlSignals) else None 338 val flushPipe = if (params.flushPipe) Some(Bool()) else None 339 val pc = if (params.needPc) Some(UInt(VAddrData().dataWidth.W)) else None 340 val jalrTarget = if (params.hasJmpFu) Some(UInt(VAddrData().dataWidth.W)) else None 341 val preDecode = if (params.hasPredecode) Some(new PreDecodeInfo) else None 342 val ftqIdx = if (params.needPc || params.replayInst) 343 Some(new FtqPtr) else None 344 val ftqOffset = if (params.needPc || params.replayInst) 345 Some(UInt(log2Up(PredictWidth).W)) else None 346 val predictInfo = if (params.hasPredecode) Some(new Bundle { 347 val target = UInt(VAddrData().dataWidth.W) 348 val taken = Bool() 349 }) else None 350 val sqIdx = if (params.hasMemAddrFu || params.hasStdFu) Some(new SqPtr) else None 351 val lqIdx = if (params.hasMemAddrFu) Some(new LqPtr) else None 352 353 def fromIssueBundle(source: IssueQueueIssueBundle): Unit = { 354 // src is assigned to rfReadData 355 this.fuType := source.common.fuType 356 this.fuOpType := source.common.fuOpType 357 this.imm := source.common.imm 358 this.robIdx := source.common.robIdx 359 this.pdest := source.common.pdest 360 this.isFirstIssue := source.common.isFirstIssue // Only used by mem debug log 361 this.iqIdx := source.common.iqIdx // Only used by mem feedback 362 this.rfWen .foreach(_ := source.common.rfWen.get) 363 this.fpWen .foreach(_ := source.common.fpWen.get) 364 this.vecWen .foreach(_ := source.common.vecWen.get) 365 this.fpu .foreach(_ := source.common.fpu.get) 366 this.vpu .foreach(_ := source.common.vpu.get) 367 this.flushPipe .foreach(_ := source.common.flushPipe.get) 368 this.pc .foreach(_ := source.jmp.get.pc) 369 this.jalrTarget .foreach(_ := source.jmp.get.target) 370 this.preDecode .foreach(_ := source.common.preDecode.get) 371 this.ftqIdx .foreach(_ := source.common.ftqIdx.get) 372 this.ftqOffset .foreach(_ := source.common.ftqOffset.get) 373 this.predictInfo .foreach(_ := source.common.predictInfo.get) 374 this.lqIdx .foreach(_ := source.common.lqIdx.get) 375 this.sqIdx .foreach(_ := source.common.sqIdx.get) 376 } 377 } 378 379 // ExuInput --[FuncUnit]--> ExuOutput 380 class ExuOutput( 381 val params: ExeUnitParams, 382 )(implicit 383 val p: Parameters 384 ) extends Bundle with BundleSource with HasXSParameter { 385 val data = UInt(params.dataBitsMax.W) 386 val pdest = UInt(params.wbPregIdxWidth.W) 387 val robIdx = new RobPtr 388 val intWen = if (params.writeIntRf) Some(Bool()) else None 389 val fpWen = if (params.writeFpRf) Some(Bool()) else None 390 val vecWen = if (params.writeVecRf) Some(Bool()) else None 391 val redirect = if (params.hasRedirect) Some(ValidIO(new Redirect)) else None 392 val fflags = if (params.writeFflags) Some(UInt(5.W)) else None 393 val vxsat = if (params.writeVxsat) Some(Bool()) else None 394 val exceptionVec = if (params.exceptionOut.nonEmpty) Some(ExceptionVec()) else None 395 val flushPipe = if (params.flushPipe) Some(Bool()) else None 396 val replay = if (params.replayInst) Some(Bool()) else None 397 val lqIdx = if (params.hasLoadFu) Some(new LqPtr()) else None 398 val sqIdx = if (params.hasStoreAddrFu || params.hasStdFu) 399 Some(new SqPtr()) else None 400 val ftqIdx = if (params.needPc || params.replayInst) 401 Some(new FtqPtr) else None 402 val ftqOffset = if (params.needPc || params.replayInst) 403 Some(UInt(log2Up(PredictWidth).W)) else None 404 // uop info 405 val predecodeInfo = if(params.hasPredecode) Some(new PreDecodeInfo) else None 406 val debug = new DebugBundle 407 val debugInfo = new PerfDebugInfo 408 } 409 410 // ExuOutput + DynInst --> WriteBackBundle 411 class WriteBackBundle(val params: WbConfig)(implicit p: Parameters) extends Bundle with BundleSource { 412 val rfWen = Bool() 413 val fpWen = Bool() 414 val vecWen = Bool() 415 val pdest = UInt(params.pregIdxWidth.W) 416 val data = UInt(params.dataWidth.W) 417 val robIdx = new RobPtr()(p) 418 val flushPipe = Bool() 419 val replayInst = Bool() 420 val redirect = ValidIO(new Redirect) 421 val fflags = UInt(5.W) 422 val exceptionVec = ExceptionVec() 423 val debug = new DebugBundle 424 val debugInfo = new PerfDebugInfo 425 426 def fromExuOutput(source: ExuOutput) = { 427 this.rfWen := source.intWen.getOrElse(false.B) 428 this.fpWen := source.fpWen.getOrElse(false.B) 429 this.vecWen := source.vecWen.getOrElse(false.B) 430 this.pdest := source.pdest 431 this.data := source.data 432 this.robIdx := source.robIdx 433 this.flushPipe := source.flushPipe.getOrElse(false.B) 434 this.replayInst := source.replay.getOrElse(false.B) 435 this.redirect := source.redirect.getOrElse(0.U.asTypeOf(this.redirect)) 436 this.fflags := source.fflags.getOrElse(0.U.asTypeOf(this.fflags)) 437 this.exceptionVec := source.exceptionVec.getOrElse(0.U.asTypeOf(this.exceptionVec)) 438 this.debug := source.debug 439 this.debugInfo := source.debugInfo 440 } 441 442 def asWakeUpBundle: IssueQueueWakeUpBundle = { 443 val wakeup = Output(new IssueQueueWakeUpBundle(params.pregIdxWidth)) 444 wakeup.rfWen := this.rfWen 445 wakeup.fpWen := this.fpWen 446 wakeup.vecWen := this.vecWen 447 wakeup.pdest := this.pdest 448 wakeup.source = this.source 449 wakeup 450 } 451 452 def asIntRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 453 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, this.params.pregIdxWidth))) 454 rfWrite.wen := this.rfWen && fire 455 rfWrite.addr := this.pdest 456 rfWrite.data := this.data 457 rfWrite.intWen := this.rfWen 458 rfWrite.fpWen := false.B 459 rfWrite.vecWen := false.B 460 rfWrite 461 } 462 463 def asVfRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 464 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, this.params.pregIdxWidth))) 465 rfWrite.wen := (this.fpWen || this.vecWen) && fire 466 rfWrite.addr := this.pdest 467 rfWrite.data := this.data 468 rfWrite.intWen := false.B 469 rfWrite.fpWen := this.fpWen 470 rfWrite.vecWen := this.vecWen 471 rfWrite 472 } 473 } 474 475 class ExceptionInfo extends Bundle { 476 val pc = UInt(VAddrData().dataWidth.W) 477 val instr = UInt(32.W) 478 val commitType = CommitType() 479 val exceptionVec = ExceptionVec() 480 val singleStep = Bool() 481 val crossPageIPFFix = Bool() 482 val isInterrupt = Bool() 483 } 484 485 class MemExuInput(implicit p: Parameters) extends XSBundle { 486 val uop = new DynInst 487 val src = Vec(3, UInt(XLEN.W)) 488 val iqIdx = UInt(log2Up(MemIQSizeMax).W) 489 val isFirstIssue = Bool() 490 } 491 492 class MemExuOutput(implicit p: Parameters) extends XSBundle { 493 val uop = new DynInst 494 val data = UInt(XLEN.W) 495 val debug = new DebugBundle 496 } 497 498 class MemMicroOpRbExt(implicit p: Parameters) extends XSBundle { 499 val uop = new DynInst 500 val flag = UInt(1.W) 501 } 502} 503