1package xiangshan.backend 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util.BitPat.bitPatToUInt 6import chisel3.util._ 7import utils.BundleUtils.makeValid 8import utils.OptionWrapper 9import xiangshan._ 10import xiangshan.backend.datapath.DataConfig._ 11import xiangshan.backend.datapath.DataSource 12import xiangshan.backend.datapath.WbConfig.PregWB 13import xiangshan.backend.decode.{ImmUnion, XDecode} 14import xiangshan.backend.exu.ExeUnitParams 15import xiangshan.backend.fu.FuType 16import xiangshan.backend.fu.fpu.Bundles.Frm 17import xiangshan.backend.fu.vector.Bundles._ 18import xiangshan.backend.issue.{IssueBlockParams, IssueQueueDeqRespBundle, SchedulerType} 19import xiangshan.backend.issue.EntryBundles._ 20import xiangshan.backend.regfile.{RfReadPortWithConfig, RfWritePortWithConfig} 21import xiangshan.backend.rob.RobPtr 22import xiangshan.frontend._ 23import xiangshan.mem.{LqPtr, SqPtr} 24import yunsuan.vector.VIFuParam 25 26object Bundles { 27 /** 28 * Connect Same Name Port like bundleSource := bundleSinkBudle. 29 * 30 * There is no limit to the number of ports on both sides. 31 * 32 * Don't forget to connect the remaining ports! 33 */ 34 def connectSamePort (bundleSource: Bundle, bundleSink: Bundle):Unit = { 35 bundleSource.elements.foreach { case (name, data) => 36 if (bundleSink.elements.contains(name)) 37 data := bundleSink.elements(name) 38 } 39 } 40 // frontend -> backend 41 class StaticInst(implicit p: Parameters) extends XSBundle { 42 val instr = UInt(32.W) 43 val pc = UInt(VAddrBits.W) 44 val foldpc = UInt(MemPredPCWidth.W) 45 val exceptionVec = ExceptionVec() 46 val trigger = new TriggerCf 47 val preDecodeInfo = new PreDecodeInfo 48 val pred_taken = Bool() 49 val crossPageIPFFix = Bool() 50 val ftqPtr = new FtqPtr 51 val ftqOffset = UInt(log2Up(PredictWidth).W) 52 53 def connectCtrlFlow(source: CtrlFlow): Unit = { 54 this.instr := source.instr 55 this.pc := source.pc 56 this.foldpc := source.foldpc 57 this.exceptionVec := source.exceptionVec 58 this.trigger := source.trigger 59 this.preDecodeInfo := source.pd 60 this.pred_taken := source.pred_taken 61 this.crossPageIPFFix := source.crossPageIPFFix 62 this.ftqPtr := source.ftqPtr 63 this.ftqOffset := source.ftqOffset 64 } 65 } 66 67 // StaticInst --[Decode]--> DecodedInst 68 class DecodedInst(implicit p: Parameters) extends XSBundle { 69 def numSrc = backendParams.numSrc 70 // passed from StaticInst 71 val instr = UInt(32.W) 72 val pc = UInt(VAddrBits.W) 73 val foldpc = UInt(MemPredPCWidth.W) 74 val exceptionVec = ExceptionVec() 75 val trigger = new TriggerCf 76 val preDecodeInfo = new PreDecodeInfo 77 val pred_taken = Bool() 78 val crossPageIPFFix = Bool() 79 val ftqPtr = new FtqPtr 80 val ftqOffset = UInt(log2Up(PredictWidth).W) 81 // decoded 82 val srcType = Vec(numSrc, SrcType()) 83 val lsrc = Vec(numSrc, UInt(6.W)) 84 val ldest = UInt(6.W) 85 val fuType = FuType() 86 val fuOpType = FuOpType() 87 val rfWen = Bool() 88 val fpWen = Bool() 89 val vecWen = Bool() 90 val v0Wen = Bool() 91 val vlWen = Bool() 92 val isXSTrap = Bool() 93 val waitForward = Bool() // no speculate execution 94 val blockBackward = Bool() 95 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 96 val canRobCompress = Bool() 97 val selImm = SelImm() 98 val imm = UInt(ImmUnion.maxLen.W) 99 val fpu = new FPUCtrlSignals 100 val vpu = new VPUCtrlSignals 101 val vlsInstr = Bool() 102 val wfflags = Bool() 103 val isMove = Bool() 104 val uopIdx = UopIdx() 105 val uopSplitType = UopSplitType() 106 val isVset = Bool() 107 val firstUop = Bool() 108 val lastUop = Bool() 109 val numUops = UInt(log2Up(MaxUopSize).W) // rob need this 110 val numWB = UInt(log2Up(MaxUopSize).W) // rob need this 111 val commitType = CommitType() // Todo: remove it 112 113 val debug_fuType = OptionWrapper(backendParams.debugEn, FuType()) 114 115 private def allSignals = srcType.take(3) ++ Seq(fuType, fuOpType, rfWen, fpWen, vecWen, 116 isXSTrap, waitForward, blockBackward, flushPipe, canRobCompress, uopSplitType, selImm) 117 118 def decode(inst: UInt, table: Iterable[(BitPat, List[BitPat])]): DecodedInst = { 119 val decoder: Seq[UInt] = ListLookup( 120 inst, XDecode.decodeDefault.map(bitPatToUInt), 121 table.map{ case (pat, pats) => (pat, pats.map(bitPatToUInt)) }.toArray 122 ) 123 allSignals zip decoder foreach { case (s, d) => s := d } 124 debug_fuType.foreach(_ := fuType) 125 this 126 } 127 128 def isSoftPrefetch: Bool = { 129 fuType === FuType.alu.U && fuOpType === ALUOpType.or && selImm === SelImm.IMM_I && ldest === 0.U 130 } 131 132 def connectStaticInst(source: StaticInst): Unit = { 133 for ((name, data) <- this.elements) { 134 if (source.elements.contains(name)) { 135 data := source.elements(name) 136 } 137 } 138 } 139 } 140 141 // DecodedInst --[Rename]--> DynInst 142 class DynInst(implicit p: Parameters) extends XSBundle { 143 def numSrc = backendParams.numSrc 144 // passed from StaticInst 145 val instr = UInt(32.W) 146 val pc = UInt(VAddrBits.W) 147 val foldpc = UInt(MemPredPCWidth.W) 148 val exceptionVec = ExceptionVec() 149 val hasException = Bool() 150 val trigger = new TriggerCf 151 val preDecodeInfo = new PreDecodeInfo 152 val pred_taken = Bool() 153 val crossPageIPFFix = Bool() 154 val ftqPtr = new FtqPtr 155 val ftqOffset = UInt(log2Up(PredictWidth).W) 156 // passed from DecodedInst 157 val srcType = Vec(numSrc, SrcType()) 158 val ldest = UInt(6.W) 159 val fuType = FuType() 160 val fuOpType = FuOpType() 161 val rfWen = Bool() 162 val fpWen = Bool() 163 val vecWen = Bool() 164 val isXSTrap = Bool() 165 val waitForward = Bool() // no speculate execution 166 val blockBackward = Bool() 167 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 168 val canRobCompress = Bool() 169 val selImm = SelImm() 170 val imm = UInt(32.W) 171 val fpu = new FPUCtrlSignals 172 val vpu = new VPUCtrlSignals 173 val vlsInstr = Bool() 174 val wfflags = Bool() 175 val isMove = Bool() 176 val uopIdx = UopIdx() 177 val isVset = Bool() 178 val firstUop = Bool() 179 val lastUop = Bool() 180 val numUops = UInt(log2Up(MaxUopSize).W) // rob need this 181 val numWB = UInt(log2Up(MaxUopSize).W) // rob need this 182 val commitType = CommitType() 183 // rename 184 val srcState = Vec(numSrc, SrcState()) 185 val srcLoadDependency = Vec(numSrc, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 186 val psrc = Vec(numSrc, UInt(PhyRegIdxWidth.W)) 187 val pdest = UInt(PhyRegIdxWidth.W) 188 val robIdx = new RobPtr 189 val instrSize = UInt(log2Ceil(RenameWidth + 1).W) 190 val dirtyFs = Bool() 191 val dirtyVs = Bool() 192 193 val eliminatedMove = Bool() 194 // Take snapshot at this CFI inst 195 val snapshot = Bool() 196 val debugInfo = new PerfDebugInfo 197 val storeSetHit = Bool() // inst has been allocated an store set 198 val waitForRobIdx = new RobPtr // store set predicted previous store robIdx 199 // Load wait is needed 200 // load inst will not be executed until former store (predicted by mdp) addr calcuated 201 val loadWaitBit = Bool() 202 // If (loadWaitBit && loadWaitStrict), strict load wait is needed 203 // load inst will not be executed until ALL former store addr calcuated 204 val loadWaitStrict = Bool() 205 val ssid = UInt(SSIDWidth.W) 206 // Todo 207 val lqIdx = new LqPtr 208 val sqIdx = new SqPtr 209 // debug module 210 val singleStep = Bool() 211 // schedule 212 val replayInst = Bool() 213 214 val debug_fuType = OptionWrapper(backendParams.debugEn, FuType()) 215 216 val numLsElem = NumLsElem() 217 218 def getDebugFuType: UInt = debug_fuType.getOrElse(fuType) 219 220 def isLUI: Bool = this.fuType === FuType.alu.U && (this.selImm === SelImm.IMM_U || this.selImm === SelImm.IMM_LUI32) 221 def isLUI32: Bool = this.selImm === SelImm.IMM_LUI32 222 def isWFI: Bool = this.fuType === FuType.csr.U && fuOpType === CSROpType.wfi 223 224 def isSvinvalBegin(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && !flush 225 def isSvinval(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.sfence && !flush 226 def isSvinvalEnd(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && flush 227 228 def isHls: Bool = { 229 fuType === FuType.ldu.U && LSUOpType.isHlv(fuOpType) || fuType === FuType.stu.U && LSUOpType.isHsv(fuOpType) 230 } 231 232 def srcIsReady: Vec[Bool] = { 233 VecInit(this.srcType.zip(this.srcState).map { 234 case (t, s) => SrcType.isNotReg(t) || SrcState.isReady(s) 235 }) 236 } 237 238 def clearExceptions( 239 exceptionBits: Seq[Int] = Seq(), 240 flushPipe : Boolean = false, 241 replayInst : Boolean = false 242 ): DynInst = { 243 this.exceptionVec.zipWithIndex.filterNot(x => exceptionBits.contains(x._2)).foreach(_._1 := false.B) 244 if (!flushPipe) { this.flushPipe := false.B } 245 if (!replayInst) { this.replayInst := false.B } 246 this 247 } 248 249 def needWriteRf: Bool = (rfWen && ldest =/= 0.U) || fpWen || vecWen 250 } 251 252 trait BundleSource { 253 var wakeupSource = "undefined" 254 var idx = 0 255 } 256 257 /** 258 * 259 * @param pregIdxWidth index width of preg 260 * @param exuIndices exu indices of wakeup bundle 261 */ 262 sealed abstract class IssueQueueWakeUpBaseBundle(pregIdxWidth: Int, val exuIndices: Seq[Int])(implicit p: Parameters) extends XSBundle { 263 val rfWen = Bool() 264 val fpWen = Bool() 265 val vecWen = Bool() 266 val pdest = UInt(pregIdxWidth.W) 267 268 /** 269 * @param successor Seq[(psrc, srcType)] 270 * @return Seq[if wakeup psrc] 271 */ 272 def wakeUp(successor: Seq[(UInt, UInt)], valid: Bool): Seq[Bool] = { 273 successor.map { case (thatPsrc, srcType) => 274 val pdestMatch = pdest === thatPsrc 275 pdestMatch && ( 276 SrcType.isFp(srcType) && this.fpWen || 277 SrcType.isXp(srcType) && this.rfWen || 278 SrcType.isVp(srcType) && this.vecWen 279 ) && valid 280 } 281 } 282 def wakeUpFromIQ(successor: Seq[(UInt, UInt)]): Seq[Bool] = { 283 successor.map { case (thatPsrc, srcType) => 284 val pdestMatch = pdest === thatPsrc 285 pdestMatch && ( 286 SrcType.isFp(srcType) && this.fpWen || 287 SrcType.isXp(srcType) && this.rfWen || 288 SrcType.isVp(srcType) && this.vecWen 289 ) 290 } 291 } 292 293 def hasOnlyOneSource: Boolean = exuIndices.size == 1 294 295 def hasMultiSources: Boolean = exuIndices.size > 1 296 297 def isWBWakeUp = this.isInstanceOf[IssueQueueWBWakeUpBundle] 298 299 def isIQWakeUp = this.isInstanceOf[IssueQueueIQWakeUpBundle] 300 301 def exuIdx: Int = { 302 require(hasOnlyOneSource) 303 this.exuIndices.head 304 } 305 } 306 307 class IssueQueueWBWakeUpBundle(exuIndices: Seq[Int], backendParams: BackendParams)(implicit p: Parameters) extends IssueQueueWakeUpBaseBundle(backendParams.pregIdxWidth, exuIndices) { 308 309 } 310 311 class IssueQueueIQWakeUpBundle( 312 exuIdx: Int, 313 backendParams: BackendParams, 314 copyWakeupOut: Boolean = false, 315 copyNum: Int = 0 316 )(implicit p: Parameters) extends IssueQueueWakeUpBaseBundle(backendParams.pregIdxWidth, Seq(exuIdx)) { 317 val loadDependency = Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W)) 318 val is0Lat = Bool() 319 val params = backendParams.allExuParams.filter(_.exuIdx == exuIdx).head 320 val pdestCopy = OptionWrapper(copyWakeupOut, Vec(copyNum, UInt(params.wbPregIdxWidth.W))) 321 val rfWenCopy = OptionWrapper(copyWakeupOut && params.needIntWen, Vec(copyNum, Bool())) 322 val fpWenCopy = OptionWrapper(copyWakeupOut && params.needFpWen, Vec(copyNum, Bool())) 323 val vecWenCopy = OptionWrapper(copyWakeupOut && params.needVecWen, Vec(copyNum, Bool())) 324 val loadDependencyCopy = OptionWrapper(copyWakeupOut && params.isIQWakeUpSink, Vec(copyNum, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W)))) 325 def fromExuInput(exuInput: ExuInput, l2ExuVecs: Vec[UInt]): Unit = { 326 this.rfWen := exuInput.rfWen.getOrElse(false.B) 327 this.fpWen := exuInput.fpWen.getOrElse(false.B) 328 this.vecWen := exuInput.vecWen.getOrElse(false.B) 329 this.pdest := exuInput.pdest 330 } 331 332 def fromExuInput(exuInput: ExuInput): Unit = { 333 this.rfWen := exuInput.rfWen.getOrElse(false.B) 334 this.fpWen := exuInput.fpWen.getOrElse(false.B) 335 this.vecWen := exuInput.vecWen.getOrElse(false.B) 336 this.pdest := exuInput.pdest 337 } 338 } 339 340 class VPUCtrlSignals(implicit p: Parameters) extends XSBundle { 341 // vtype 342 val vill = Bool() 343 val vma = Bool() // 1: agnostic, 0: undisturbed 344 val vta = Bool() // 1: agnostic, 0: undisturbed 345 val vsew = VSew() 346 val vlmul = VLmul() // 1/8~8 --> -3~3 347 348 val vm = Bool() // 0: need v0.t 349 val vstart = Vl() 350 351 // float rounding mode 352 val frm = Frm() 353 // scalar float instr and vector float reduction 354 val fpu = Fpu() 355 // vector fix int rounding mode 356 val vxrm = Vxrm() 357 // vector uop index, exclude other non-vector uop 358 val vuopIdx = UopIdx() 359 val lastUop = Bool() 360 // maybe used if data dependancy 361 val vmask = UInt(MaskSrcData().dataWidth.W) 362 val vl = Vl() 363 364 // vector load/store 365 val nf = Nf() 366 val veew = VEew() 367 368 val isReverse = Bool() // vrsub, vrdiv 369 val isExt = Bool() 370 val isNarrow = Bool() 371 val isDstMask = Bool() // vvm, vvvm, mmm 372 val isOpMask = Bool() // vmand, vmnand 373 val isMove = Bool() // vmv.s.x, vmv.v.v, vmv.v.x, vmv.v.i 374 375 val isDependOldvd = Bool() // some instruction's computation depends on oldvd 376 val isWritePartVd = Bool() // some instruction's computation writes part of vd, such as vredsum 377 378 def vtype: VType = { 379 val res = Wire(VType()) 380 res.illegal := this.vill 381 res.vma := this.vma 382 res.vta := this.vta 383 res.vsew := this.vsew 384 res.vlmul := this.vlmul 385 res 386 } 387 388 def vconfig: VConfig = { 389 val res = Wire(VConfig()) 390 res.vtype := this.vtype 391 res.vl := this.vl 392 res 393 } 394 395 def connectVType(source: VType): Unit = { 396 this.vill := source.illegal 397 this.vma := source.vma 398 this.vta := source.vta 399 this.vsew := source.vsew 400 this.vlmul := source.vlmul 401 } 402 } 403 404 // DynInst --[IssueQueue]--> DataPath 405 class IssueQueueIssueBundle( 406 iqParams: IssueBlockParams, 407 val exuParams: ExeUnitParams, 408 )(implicit 409 p: Parameters 410 ) extends Bundle { 411 private val rfReadDataCfgSet: Seq[Set[DataConfig]] = exuParams.getRfReadDataCfgSet 412 413 val rf: MixedVec[MixedVec[RfReadPortWithConfig]] = Flipped(MixedVec( 414 rfReadDataCfgSet.map((set: Set[DataConfig]) => 415 MixedVec(set.map((x: DataConfig) => new RfReadPortWithConfig(x, exuParams.rdPregIdxWidth)).toSeq) 416 ) 417 )) 418 419 val srcType = Vec(exuParams.numRegSrc, SrcType()) // used to select imm or reg data 420 val immType = SelImm() // used to select imm extractor 421 val common = new ExuInput(exuParams) 422 val addrOH = UInt(iqParams.numEntries.W) 423 424 def exuIdx = exuParams.exuIdx 425 def getSource: SchedulerType = exuParams.getWBSource 426 def getIntWbBusyBundle = common.rfWen.toSeq 427 def getVfWbBusyBundle = common.getVfWen.toSeq 428 429 def getIntRfReadValidBundle(issueValid: Bool): Seq[ValidIO[RfReadPortWithConfig]] = { 430 rf.zip(srcType).map { 431 case (rfRd: MixedVec[RfReadPortWithConfig], t: UInt) => 432 makeValid(issueValid, rfRd.head) 433 }.toSeq 434 } 435 436 def getFpRfReadValidBundle(issueValid: Bool): Seq[ValidIO[RfReadPortWithConfig]] = { 437 rf.zip(srcType).map { 438 case (rfRd: MixedVec[RfReadPortWithConfig], t: UInt) => 439 makeValid(issueValid, rfRd.head) 440 }.toSeq 441 } 442 443 def getVfRfReadValidBundle(issueValid: Bool): Seq[ValidIO[RfReadPortWithConfig]] = { 444 rf.zip(srcType).map { 445 case (rfRd: MixedVec[RfReadPortWithConfig], t: UInt) => 446 makeValid(issueValid, rfRd.head) 447 }.toSeq 448 } 449 450 def getIntRfWriteValidBundle(issueValid: Bool) = { 451 452 } 453 } 454 455 class OGRespBundle(implicit p:Parameters, params: IssueBlockParams) extends XSBundle { 456 val issueQueueParams = this.params 457 val og0resp = Valid(new EntryDeqRespBundle) 458 val og1resp = Valid(new EntryDeqRespBundle) 459 } 460 461 class fuBusyRespBundle(implicit p: Parameters, params: IssueBlockParams) extends Bundle { 462 val respType = RSFeedbackType() // update credit if needs replay 463 val rfWen = Bool() // TODO: use params to identify IntWB/VfWB 464 val fuType = FuType() 465 } 466 467 class WbFuBusyTableWriteBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 468 private val intCertainLat = params.intLatencyCertain 469 private val fpCertainLat = params.fpLatencyCertain 470 private val vfCertainLat = params.vfLatencyCertain 471 private val v0CertainLat = params.v0LatencyCertain 472 private val vlCertainLat = params.vlLatencyCertain 473 private val intLat = params.intLatencyValMax 474 private val fpLat = params.fpLatencyValMax 475 private val vfLat = params.vfLatencyValMax 476 private val v0Lat = params.v0LatencyValMax 477 private val vlLat = params.vlLatencyValMax 478 479 val intWbBusyTable = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 480 val fpWbBusyTable = OptionWrapper(fpCertainLat, UInt((fpLat + 1).W)) 481 val vfWbBusyTable = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 482 val v0WbBusyTable = OptionWrapper(v0CertainLat, UInt((v0Lat + 1).W)) 483 val vlWbBusyTable = OptionWrapper(vlCertainLat, UInt((vlLat + 1).W)) 484 val intDeqRespSet = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 485 val fpDeqRespSet = OptionWrapper(fpCertainLat, UInt((fpLat + 1).W)) 486 val vfDeqRespSet = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 487 val v0DeqRespSet = OptionWrapper(v0CertainLat, UInt((v0Lat + 1).W)) 488 val vlDeqRespSet = OptionWrapper(vlCertainLat, UInt((vlLat + 1).W)) 489 } 490 491 class WbFuBusyTableReadBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 492 private val intCertainLat = params.intLatencyCertain 493 private val fpCertainLat = params.fpLatencyCertain 494 private val vfCertainLat = params.vfLatencyCertain 495 private val v0CertainLat = params.v0LatencyCertain 496 private val vlCertainLat = params.vlLatencyCertain 497 private val intLat = params.intLatencyValMax 498 private val fpLat = params.fpLatencyValMax 499 private val vfLat = params.vfLatencyValMax 500 private val v0Lat = params.v0LatencyValMax 501 private val vlLat = params.vlLatencyValMax 502 503 val intWbBusyTable = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 504 val fpWbBusyTable = OptionWrapper(fpCertainLat, UInt((fpLat + 1).W)) 505 val vfWbBusyTable = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 506 val v0WbBusyTable = OptionWrapper(v0CertainLat, UInt((v0Lat + 1).W)) 507 val vlWbBusyTable = OptionWrapper(vlCertainLat, UInt((vlLat + 1).W)) 508 } 509 510 class WbConflictBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 511 private val intCertainLat = params.intLatencyCertain 512 private val fpCertainLat = params.fpLatencyCertain 513 private val vfCertainLat = params.vfLatencyCertain 514 private val v0CertainLat = params.v0LatencyCertain 515 private val vlCertainLat = params.vlLatencyCertain 516 517 val intConflict = OptionWrapper(intCertainLat, Bool()) 518 val fpConflict = OptionWrapper(fpCertainLat, Bool()) 519 val vfConflict = OptionWrapper(vfCertainLat, Bool()) 520 val v0Conflict = OptionWrapper(v0CertainLat, Bool()) 521 val vlConflict = OptionWrapper(vlCertainLat, Bool()) 522 } 523 524 class ImmInfo extends Bundle { 525 val imm = UInt(32.W) 526 val immType = SelImm() 527 } 528 529 // DataPath --[ExuInput]--> Exu 530 class ExuInput(val params: ExeUnitParams, copyWakeupOut:Boolean = false, copyNum:Int = 0)(implicit p: Parameters) extends XSBundle { 531 val fuType = FuType() 532 val fuOpType = FuOpType() 533 val src = Vec(params.numRegSrc, UInt(params.dataBitsMax.W)) 534 val imm = UInt(32.W) 535 val robIdx = new RobPtr 536 val iqIdx = UInt(log2Up(MemIQSizeMax).W)// Only used by store yet 537 val isFirstIssue = Bool() // Only used by store yet 538 val pdestCopy = OptionWrapper(copyWakeupOut, Vec(copyNum, UInt(params.wbPregIdxWidth.W))) 539 val rfWenCopy = OptionWrapper(copyWakeupOut && params.needIntWen, Vec(copyNum, Bool())) 540 val fpWenCopy = OptionWrapper(copyWakeupOut && params.needFpWen, Vec(copyNum, Bool())) 541 val vecWenCopy = OptionWrapper(copyWakeupOut && params.needVecWen, Vec(copyNum, Bool())) 542 val loadDependencyCopy = OptionWrapper(copyWakeupOut && params.isIQWakeUpSink, Vec(copyNum, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W)))) 543 val pdest = UInt(params.wbPregIdxWidth.W) 544 val rfWen = if (params.needIntWen) Some(Bool()) else None 545 val fpWen = if (params.needFpWen) Some(Bool()) else None 546 val vecWen = if (params.needVecWen) Some(Bool()) else None 547 val fpu = if (params.writeFflags) Some(new FPUCtrlSignals) else None 548 val vpu = if (params.needVPUCtrl) Some(new VPUCtrlSignals) else None 549 val flushPipe = if (params.flushPipe) Some(Bool()) else None 550 val pc = if (params.needPc) Some(UInt(VAddrData().dataWidth.W)) else None 551 val preDecode = if (params.hasPredecode) Some(new PreDecodeInfo) else None 552 val ftqIdx = if (params.needPc || params.replayInst || params.hasStoreAddrFu) 553 Some(new FtqPtr) else None 554 val ftqOffset = if (params.needPc || params.replayInst || params.hasStoreAddrFu) 555 Some(UInt(log2Up(PredictWidth).W)) else None 556 val predictInfo = if (params.needPdInfo) Some(new Bundle { 557 val target = UInt(VAddrData().dataWidth.W) 558 val taken = Bool() 559 }) else None 560 val loadWaitBit = OptionWrapper(params.hasLoadExu, Bool()) 561 val waitForRobIdx = OptionWrapper(params.hasLoadExu, new RobPtr) // store set predicted previous store robIdx 562 val storeSetHit = OptionWrapper(params.hasLoadExu, Bool()) // inst has been allocated an store set 563 val loadWaitStrict = OptionWrapper(params.hasLoadExu, Bool()) // load inst will not be executed until ALL former store addr calcuated 564 val ssid = OptionWrapper(params.hasLoadExu, UInt(SSIDWidth.W)) 565 // only vector load store need 566 val numLsElem = OptionWrapper(params.hasVecLsFu, NumLsElem()) 567 568 val sqIdx = if (params.hasMemAddrFu || params.hasStdFu) Some(new SqPtr) else None 569 val lqIdx = if (params.hasMemAddrFu) Some(new LqPtr) else None 570 val dataSources = Vec(params.numRegSrc, DataSource()) 571 val l1ExuOH = OptionWrapper(params.isIQWakeUpSink, Vec(params.numRegSrc, ExuOH())) 572 val srcTimer = OptionWrapper(params.isIQWakeUpSink, Vec(params.numRegSrc, UInt(3.W))) 573 val loadDependency = OptionWrapper(params.isIQWakeUpSink, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 574 575 val perfDebugInfo = new PerfDebugInfo() 576 577 def exuIdx = this.params.exuIdx 578 579 def needCancel(og0CancelOH: UInt, og1CancelOH: UInt) : Bool = { 580 if (params.isIQWakeUpSink) { 581 require( 582 og0CancelOH.getWidth == l1ExuOH.get.head.getWidth, 583 s"cancelVecSize: {og0: ${og0CancelOH.getWidth}, og1: ${og1CancelOH.getWidth}}" 584 ) 585 val l1Cancel: Bool = l1ExuOH.get.zip(srcTimer.get).map { 586 case(exuOH: UInt, srcTimer: UInt) => 587 (exuOH & og0CancelOH).orR && srcTimer === 1.U 588 }.reduce(_ | _) 589 l1Cancel 590 } else { 591 false.B 592 } 593 } 594 595 def getFpWen = { 596 if (params.writeFpRf) this.fpWen 597 else None 598 } 599 600 def getVfWen = { 601 if(params.writeVecRf) this.vecWen 602 else None 603 } 604 605 def fromIssueBundle(source: IssueQueueIssueBundle): Unit = { 606 // src is assigned to rfReadData 607 this.fuType := source.common.fuType 608 this.fuOpType := source.common.fuOpType 609 this.imm := source.common.imm 610 this.robIdx := source.common.robIdx 611 this.pdest := source.common.pdest 612 this.isFirstIssue := source.common.isFirstIssue // Only used by mem debug log 613 this.iqIdx := source.common.iqIdx // Only used by mem feedback 614 this.dataSources := source.common.dataSources 615 this.l1ExuOH .foreach(_ := source.common.l1ExuOH.get) 616 this.rfWen .foreach(_ := source.common.rfWen.get) 617 this.fpWen .foreach(_ := source.common.fpWen.get) 618 this.vecWen .foreach(_ := source.common.vecWen.get) 619 this.fpu .foreach(_ := source.common.fpu.get) 620 this.vpu .foreach(_ := source.common.vpu.get) 621 this.flushPipe .foreach(_ := source.common.flushPipe.get) 622 this.pc .foreach(_ := source.common.pc.get) 623 this.preDecode .foreach(_ := source.common.preDecode.get) 624 this.ftqIdx .foreach(_ := source.common.ftqIdx.get) 625 this.ftqOffset .foreach(_ := source.common.ftqOffset.get) 626 this.predictInfo .foreach(_ := source.common.predictInfo.get) 627 this.loadWaitBit .foreach(_ := source.common.loadWaitBit.get) 628 this.waitForRobIdx .foreach(_ := source.common.waitForRobIdx.get) 629 this.storeSetHit .foreach(_ := source.common.storeSetHit.get) 630 this.loadWaitStrict.foreach(_ := source.common.loadWaitStrict.get) 631 this.ssid .foreach(_ := source.common.ssid.get) 632 this.lqIdx .foreach(_ := source.common.lqIdx.get) 633 this.sqIdx .foreach(_ := source.common.sqIdx.get) 634 this.numLsElem .foreach(_ := source.common.numLsElem.get) 635 this.srcTimer .foreach(_ := source.common.srcTimer.get) 636 this.loadDependency.foreach(_ := source.common.loadDependency.get.map(_ << 1)) 637 } 638 } 639 640 // ExuInput --[FuncUnit]--> ExuOutput 641 class ExuOutput( 642 val params: ExeUnitParams, 643 )(implicit 644 val p: Parameters 645 ) extends Bundle with BundleSource with HasXSParameter { 646 val data = UInt(params.dataBitsMax.W) 647 val pdest = UInt(params.wbPregIdxWidth.W) 648 val robIdx = new RobPtr 649 val intWen = if (params.needIntWen) Some(Bool()) else None 650 val fpWen = if (params.needFpWen) Some(Bool()) else None 651 val vecWen = if (params.needVecWen) Some(Bool()) else None 652 val redirect = if (params.hasRedirect) Some(ValidIO(new Redirect)) else None 653 val fflags = if (params.writeFflags) Some(UInt(5.W)) else None 654 val wflags = if (params.writeFflags) Some(Bool()) else None 655 val vxsat = if (params.writeVxsat) Some(Bool()) else None 656 val exceptionVec = if (params.exceptionOut.nonEmpty) Some(ExceptionVec()) else None 657 val flushPipe = if (params.flushPipe) Some(Bool()) else None 658 val replay = if (params.replayInst) Some(Bool()) else None 659 val lqIdx = if (params.hasLoadFu) Some(new LqPtr()) else None 660 val sqIdx = if (params.hasStoreAddrFu || params.hasStdFu) 661 Some(new SqPtr()) else None 662 val trigger = if (params.trigger) Some(new TriggerCf) else None 663 // uop info 664 val predecodeInfo = if(params.hasPredecode) Some(new PreDecodeInfo) else None 665 // vldu used only 666 val vls = OptionWrapper(params.hasVLoadFu, new Bundle { 667 val vpu = new VPUCtrlSignals 668 val oldVdPsrc = UInt(PhyRegIdxWidth.W) 669 val vdIdx = UInt(3.W) 670 val vdIdxInField = UInt(3.W) 671 val isIndexed = Bool() 672 val isMasked = Bool() 673 }) 674 val debug = new DebugBundle 675 val debugInfo = new PerfDebugInfo 676 } 677 678 // ExuOutput + DynInst --> WriteBackBundle 679 class WriteBackBundle(val params: PregWB, backendParams: BackendParams)(implicit p: Parameters) extends Bundle with BundleSource { 680 val rfWen = Bool() 681 val fpWen = Bool() 682 val vecWen = Bool() 683 val pdest = UInt(params.pregIdxWidth(backendParams).W) 684 val data = UInt(params.dataWidth.W) 685 val robIdx = new RobPtr()(p) 686 val flushPipe = Bool() 687 val replayInst = Bool() 688 val redirect = ValidIO(new Redirect) 689 val fflags = UInt(5.W) 690 val vxsat = Bool() 691 val exceptionVec = ExceptionVec() 692 val debug = new DebugBundle 693 val debugInfo = new PerfDebugInfo 694 695 this.wakeupSource = s"WB(${params.toString})" 696 697 def fromExuOutput(source: ExuOutput) = { 698 this.rfWen := source.intWen.getOrElse(false.B) 699 this.fpWen := source.fpWen.getOrElse(false.B) 700 this.vecWen := source.vecWen.getOrElse(false.B) 701 this.pdest := source.pdest 702 this.data := source.data 703 this.robIdx := source.robIdx 704 this.flushPipe := source.flushPipe.getOrElse(false.B) 705 this.replayInst := source.replay.getOrElse(false.B) 706 this.redirect := source.redirect.getOrElse(0.U.asTypeOf(this.redirect)) 707 this.fflags := source.fflags.getOrElse(0.U.asTypeOf(this.fflags)) 708 this.vxsat := source.vxsat.getOrElse(0.U.asTypeOf(this.vxsat)) 709 this.exceptionVec := source.exceptionVec.getOrElse(0.U.asTypeOf(this.exceptionVec)) 710 this.debug := source.debug 711 this.debugInfo := source.debugInfo 712 } 713 714 def asIntRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 715 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(IntData()).addrWidth))) 716 rfWrite.wen := this.rfWen && fire 717 rfWrite.addr := this.pdest 718 rfWrite.data := this.data 719 rfWrite.intWen := this.rfWen 720 rfWrite.fpWen := false.B 721 rfWrite.vecWen := false.B 722 rfWrite 723 } 724 725 def asFpRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 726 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(FpData()).addrWidth))) 727 rfWrite.wen := this.fpWen && fire 728 rfWrite.addr := this.pdest 729 rfWrite.data := this.data 730 rfWrite.intWen := false.B 731 rfWrite.fpWen := this.fpWen 732 rfWrite.vecWen := false.B 733 rfWrite 734 } 735 736 def asVfRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 737 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(VecData()).addrWidth))) 738 rfWrite.wen := this.vecWen && fire 739 rfWrite.addr := this.pdest 740 rfWrite.data := this.data 741 rfWrite.intWen := false.B 742 rfWrite.fpWen := false.B 743 rfWrite.vecWen := this.vecWen 744 rfWrite 745 } 746 } 747 748 // ExuOutput --> ExuBypassBundle --[DataPath]-->ExuInput 749 // / 750 // [IssueQueue]--> ExuInput -- 751 class ExuBypassBundle( 752 val params: ExeUnitParams, 753 )(implicit 754 val p: Parameters 755 ) extends Bundle { 756 val data = UInt(params.dataBitsMax.W) 757 val pdest = UInt(params.wbPregIdxWidth.W) 758 } 759 760 class ExceptionInfo(implicit p: Parameters) extends XSBundle { 761 val pc = UInt(VAddrData().dataWidth.W) 762 val instr = UInt(32.W) 763 val commitType = CommitType() 764 val exceptionVec = ExceptionVec() 765 val gpaddr = UInt(GPAddrBits.W) 766 val singleStep = Bool() 767 val crossPageIPFFix = Bool() 768 val isInterrupt = Bool() 769 val isHls = Bool() 770 val vls = Bool() 771 val trigger = new TriggerCf 772 } 773 774 object UopIdx { 775 def apply()(implicit p: Parameters): UInt = UInt(log2Up(p(XSCoreParamsKey).MaxUopSize + 1).W) 776 } 777 778 object FuLatency { 779 def apply(): UInt = UInt(width.W) 780 781 def width = 4 // 0~15 // Todo: assosiate it with FuConfig 782 } 783 784 object ExuOH { 785 def apply(exuNum: Int): UInt = UInt(exuNum.W) 786 787 def apply()(implicit p: Parameters): UInt = UInt(width.W) 788 789 def width(implicit p: Parameters): Int = p(XSCoreParamsKey).backendParams.numExu 790 } 791 792 object ExuVec { 793 def apply(exuNum: Int): Vec[Bool] = Vec(exuNum, Bool()) 794 795 def apply()(implicit p: Parameters): Vec[Bool] = Vec(width, Bool()) 796 797 def width(implicit p: Parameters): Int = p(XSCoreParamsKey).backendParams.numExu 798 } 799 800 class CancelSignal(implicit p: Parameters) extends XSBundle { 801 val rfWen = Bool() 802 val fpWen = Bool() 803 val vecWen = Bool() 804 val pdest = UInt(PhyRegIdxWidth.W) 805 806 def needCancel(srcType: UInt, psrc: UInt, valid: Bool): Bool = { 807 val pdestMatch = pdest === psrc 808 pdestMatch && ( 809 SrcType.isFp(srcType) && !this.rfWen || 810 SrcType.isXp(srcType) && this.rfWen || 811 SrcType.isVp(srcType) && !this.rfWen 812 ) && valid 813 } 814 } 815 816 class MemExuInput(isVector: Boolean = false)(implicit p: Parameters) extends XSBundle { 817 val uop = new DynInst 818 val src = if (isVector) Vec(5, UInt(VLEN.W)) else Vec(3, UInt(XLEN.W)) 819 val iqIdx = UInt(log2Up(MemIQSizeMax).W) 820 val isFirstIssue = Bool() 821 val flowNum = OptionWrapper(isVector, NumLsElem()) 822 823 def src_rs1 = src(0) 824 def src_stride = src(1) 825 def src_vs3 = src(2) 826 def src_mask = if (isVector) src(3) else 0.U 827 def src_vl = if (isVector) src(4) else 0.U 828 } 829 830 class MemExuOutput(isVector: Boolean = false)(implicit p: Parameters) extends XSBundle { 831 val uop = new DynInst 832 val data = if (isVector) UInt(VLEN.W) else UInt(XLEN.W) 833 val mask = if (isVector) Some(UInt(VLEN.W)) else None 834 val vdIdx = if (isVector) Some(UInt(3.W)) else None // TODO: parameterize width 835 val vdIdxInField = if (isVector) Some(UInt(3.W)) else None 836 val debug = new DebugBundle 837 838 def isVls = FuType.isVls(uop.fuType) 839 } 840 841 class MemMicroOpRbExt(implicit p: Parameters) extends XSBundle { 842 val uop = new DynInst 843 val flag = UInt(1.W) 844 } 845 846 object LoadShouldCancel { 847 def apply(loadDependency: Option[Seq[UInt]], ldCancel: Seq[LoadCancelIO]): Bool = { 848 val ld1Cancel = loadDependency.map(_.zip(ldCancel.map(_.ld1Cancel)).map { case (dep, cancel) => cancel && dep(0)}.reduce(_ || _)) 849 val ld2Cancel = loadDependency.map(_.zip(ldCancel.map(_.ld2Cancel)).map { case (dep, cancel) => cancel && dep(1)}.reduce(_ || _)) 850 ld1Cancel.map(_ || ld2Cancel.get).getOrElse(false.B) 851 } 852 } 853} 854