1package xiangshan.backend 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utils.OptionWrapper 7import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 8import utility.{PipelineConnect, ZeroExt} 9import xiangshan._ 10import xiangshan.backend.Bundles.{DynInst, MemExuInput, MemExuOutput} 11import xiangshan.backend.ctrlblock.CtrlBlock 12import xiangshan.backend.datapath.WbConfig._ 13import xiangshan.backend.datapath.{DataPath, NewPipelineConnect, WbDataPath, WbFuBusyTable} 14import xiangshan.backend.exu.ExuBlock 15import xiangshan.backend.fu.vector.Bundles.{VConfig, VType} 16import xiangshan.backend.fu.{FenceIO, FenceToSbuffer, FuConfig, PerfCounterIO} 17import xiangshan.backend.issue.{Scheduler, IntScheduler, MemScheduler, VfScheduler} 18import xiangshan.backend.rob.RobLsqIO 19import xiangshan.frontend.{FtqPtr, FtqRead} 20import xiangshan.mem.{LqPtr, LsqEnqIO, SqPtr} 21 22class Backend(val params: BackendParams)(implicit p: Parameters) extends LazyModule 23 with HasXSParameter { 24 25 println("[Backend] ExuConfigs:") 26 for (exuCfg <- params.allExuParams) { 27 val fuConfigs = exuCfg.fuConfigs 28 val wbPortConfigs = exuCfg.wbPortConfigs 29 val immType = exuCfg.immType 30 31 println("[Backend] " + 32 s"${exuCfg.name}: " + 33 s"${ fuConfigs.map(_.name).mkString("fu(s): {", ",", "}") }, " + 34 s"${ wbPortConfigs.mkString("wb: {", ",", "}") }, " + 35 s"${ immType.map(SelImm.mkString(_)).mkString("imm: {", "," , "}") }, " + 36 s"latMax(${exuCfg.latencyValMax}), ${exuCfg.fuLatancySet.mkString("lat: {",",","}")}, ") 37 require(wbPortConfigs.collectFirst { case x: IntWB => x }.nonEmpty == 38 fuConfigs.map(_.writeIntRf).reduce(_ || _), 39 "int wb port has no priority" ) 40 require(wbPortConfigs.collectFirst { case x: VfWB => x }.nonEmpty == 41 fuConfigs.map(x => x.writeFpRf || x.writeVecRf).reduce(_ || _), 42 "vec wb port has no priority" ) 43 } 44 45 for (cfg <- FuConfig.allConfigs) { 46 println(s"[Backend] $cfg") 47 } 48 49 val ctrlBlock = LazyModule(new CtrlBlock(params)) 50 val intScheduler = params.intSchdParams.map(x => LazyModule(new Scheduler(x))) 51 val vfScheduler = params.vfSchdParams.map(x => LazyModule(new Scheduler(x))) 52 val memScheduler = params.memSchdParams.map(x => LazyModule(new Scheduler(x))) 53 val dataPath = LazyModule(new DataPath(params)) 54 val intExuBlock = params.intSchdParams.map(x => LazyModule(new ExuBlock(x))) 55 val vfExuBlock = params.vfSchdParams.map(x => LazyModule(new ExuBlock(x))) 56 57 lazy val module = new BackendImp(this) 58} 59 60class BackendImp(override val wrapper: Backend)(implicit p: Parameters) extends LazyModuleImp(wrapper) 61 with HasXSParameter{ 62 implicit private val params = wrapper.params 63 val io = IO(new BackendIO()(p, wrapper.params)) 64 65 private val ctrlBlock = wrapper.ctrlBlock.module 66 private val intScheduler = wrapper.intScheduler.get.module 67 private val vfScheduler = wrapper.vfScheduler.get.module 68 private val memScheduler = wrapper.memScheduler.get.module 69 private val dataPath = wrapper.dataPath.module 70 private val intExuBlock = wrapper.intExuBlock.get.module 71 private val vfExuBlock = wrapper.vfExuBlock.get.module 72 private val wbDataPath = Module(new WbDataPath(params)) 73 private val wbFuBusyTable = Module(new WbFuBusyTable) 74 75 wbFuBusyTable.io.in.intSchdBusyTable := intScheduler.io.wbFuBusyTable 76 wbFuBusyTable.io.in.vfSchdBusyTable := vfScheduler.io.wbFuBusyTable 77 wbFuBusyTable.io.in.memSchdBusyTable := memScheduler.io.wbFuBusyTable 78 intScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.intRespRead 79 vfScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.vfRespRead 80 memScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.memRespRead 81 dataPath.io.wbConfictRead := wbFuBusyTable.io.out.wbConflictRead 82 83 wbDataPath.io.fromIntExu.flatten.filter(x => x.bits.params.writeIntRf) 84 85 private val vconfig = dataPath.io.vconfigReadPort.data 86 87 ctrlBlock.io.fromTop.hartId := io.fromTop.hartId 88 ctrlBlock.io.frontend <> io.frontend 89 ctrlBlock.io.fromWB.wbData <> wbDataPath.io.toCtrlBlock.writeback 90 ctrlBlock.io.fromMem.stIn <> io.mem.stIn 91 ctrlBlock.io.fromMem.violation <> io.mem.memoryViolation 92 ctrlBlock.io.csrCtrl <> intExuBlock.io.csrio.get.customCtrl 93 ctrlBlock.io.robio.csr.intrBitSet := intExuBlock.io.csrio.get.interrupt 94 ctrlBlock.io.robio.csr.trapTarget := intExuBlock.io.csrio.get.trapTarget 95 ctrlBlock.io.robio.csr.isXRet := intExuBlock.io.csrio.get.isXRet 96 ctrlBlock.io.robio.csr.wfiEvent := intExuBlock.io.csrio.get.wfi_event 97 ctrlBlock.io.robio.lsq <> io.mem.robLsqIO 98 ctrlBlock.io.fromDataPath.vtype := vconfig(7, 0).asTypeOf(new VType) 99 100 intScheduler.io.fromTop.hartId := io.fromTop.hartId 101 intScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 102 intScheduler.io.fromCtrlBlock.pcVec := ctrlBlock.io.toIssueBlock.pcVec 103 intScheduler.io.fromCtrlBlock.targetVec := ctrlBlock.io.toIssueBlock.targetVec 104 intScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 105 intScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.intUops 106 intScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 107 intScheduler.io.vfWriteBack := 0.U.asTypeOf(intScheduler.io.vfWriteBack) 108 intScheduler.io.fromDataPath := dataPath.io.toIntIQ 109 110 memScheduler.io.fromTop.hartId := io.fromTop.hartId 111 memScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 112 memScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 113 memScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.memUops 114 memScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 115 memScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 116 memScheduler.io.fromMem.get.scommit := io.mem.sqDeq 117 memScheduler.io.fromMem.get.lcommit := io.mem.lqDeq 118 memScheduler.io.fromMem.get.sqCancelCnt := io.mem.sqCancelCnt 119 memScheduler.io.fromMem.get.lqCancelCnt := io.mem.lqCancelCnt 120 memScheduler.io.fromMem.get.stIssuePtr := io.mem.stIssuePtr 121 memScheduler.io.fromMem.get.memWaitUpdateReq.staIssue.zip(io.mem.stIn).foreach { case (sink, source) => 122 sink.valid := source.valid 123 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 124 sink.bits.uop.robIdx := source.bits.robIdx 125 } 126 memScheduler.io.fromDataPath := dataPath.io.toMemIQ 127 memScheduler.io.fromMem.get.ldaFeedback := io.mem.ldaIqFeedback 128 memScheduler.io.fromMem.get.staFeedback := io.mem.staIqFeedback 129 130 vfScheduler.io.fromTop.hartId := io.fromTop.hartId 131 vfScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 132 vfScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 133 vfScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.vfUops 134 vfScheduler.io.intWriteBack := 0.U.asTypeOf(vfScheduler.io.intWriteBack) 135 vfScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 136 vfScheduler.io.fromDataPath := dataPath.io.toVfIQ 137 138 dataPath.io.flush := ctrlBlock.io.toDataPath.flush 139 dataPath.io.vconfigReadPort.addr := ctrlBlock.io.toDataPath.vtypeAddr 140 141 for (i <- 0 until dataPath.io.fromIntIQ.length) { 142 for (j <- 0 until dataPath.io.fromIntIQ(i).length) { 143 NewPipelineConnect(intScheduler.io.toDataPath(i)(j), dataPath.io.fromIntIQ(i)(j), dataPath.io.fromIntIQ(i)(j).valid, 144 intScheduler.io.toDataPath(i)(j).bits.common.robIdx.needFlush(ctrlBlock.io.toDataPath.flush), Option("intScheduler2DataPathPipe")) 145 } 146 } 147 148 for (i <- 0 until dataPath.io.fromVfIQ.length) { 149 for (j <- 0 until dataPath.io.fromVfIQ(i).length) { 150 NewPipelineConnect(vfScheduler.io.toDataPath(i)(j), dataPath.io.fromVfIQ(i)(j), dataPath.io.fromVfIQ(i)(j).valid, 151 vfScheduler.io.toDataPath(i)(j).bits.common.robIdx.needFlush(ctrlBlock.io.toDataPath.flush), Option("vfScheduler2DataPathPipe")) 152 } 153 } 154 155 for (i <- 0 until dataPath.io.fromMemIQ.length) { 156 for (j <- 0 until dataPath.io.fromMemIQ(i).length) { 157 NewPipelineConnect(memScheduler.io.toDataPath(i)(j), dataPath.io.fromMemIQ(i)(j), dataPath.io.fromMemIQ(i)(j).valid, 158 memScheduler.io.toDataPath(i)(j).bits.common.robIdx.needFlush(ctrlBlock.io.toDataPath.flush), Option("memScheduler2DataPathPipe")) 159 } 160 } 161 162 println(s"[Backend] wbDataPath.io.toIntPreg: ${wbDataPath.io.toIntPreg.size}, dataPath.io.fromIntWb: ${dataPath.io.fromIntWb.size}") 163 println(s"[Backend] wbDataPath.io.toVfPreg: ${wbDataPath.io.toVfPreg.size}, dataPath.io.fromFpWb: ${dataPath.io.fromVfWb.size}") 164 dataPath.io.fromIntWb := wbDataPath.io.toIntPreg 165 dataPath.io.fromVfWb := wbDataPath.io.toVfPreg 166 dataPath.io.debugIntRat := ctrlBlock.io.debug_int_rat 167 dataPath.io.debugFpRat := ctrlBlock.io.debug_fp_rat 168 dataPath.io.debugVecRat := ctrlBlock.io.debug_vec_rat 169 dataPath.io.debugVconfigRat := ctrlBlock.io.debug_vconfig_rat 170 171 intExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 172 for (i <- 0 until intExuBlock.io.in.length) { 173 for (j <- 0 until intExuBlock.io.in(i).length) { 174 NewPipelineConnect(dataPath.io.toIntExu(i)(j), intExuBlock.io.in(i)(j), intExuBlock.io.in(i)(j).fire, 175 Mux(dataPath.io.toIntExu(i)(j).fire, 176 dataPath.io.toIntExu(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush), 177 intExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush))) 178 } 179 } 180 181 private val csrio = intExuBlock.io.csrio.get 182 csrio.hartId := io.fromTop.hartId 183 csrio.perf.retiredInstr <> ctrlBlock.io.robio.csr.perfinfo.retiredInstr 184 csrio.perf.ctrlInfo <> ctrlBlock.io.perfInfo.ctrlInfo 185 csrio.perf.perfEventsCtrl <> ctrlBlock.getPerf 186 csrio.fpu.fflags := ctrlBlock.io.robio.csr.fflags 187 csrio.fpu.isIllegal := false.B // Todo: remove it 188 csrio.fpu.dirty_fs := ctrlBlock.io.robio.csr.dirty_fs 189 csrio.vpu <> 0.U.asTypeOf(csrio.vpu) // Todo 190 191 val debugVconfig = dataPath.io.debugVconfig.asTypeOf(new VConfig) 192 val debugVtype = VType.toVtypeStruct(debugVconfig.vtype).asUInt 193 val debugVl = debugVconfig.vl 194 csrio.vpu.set_vxsat := ctrlBlock.io.robio.csr.vxsat 195 csrio.vpu.set_vstart.valid := ctrlBlock.io.robio.csr.vcsrFlag 196 csrio.vpu.set_vstart.bits := 0.U 197 csrio.vpu.set_vtype.valid := ctrlBlock.io.robio.csr.vcsrFlag 198 csrio.vpu.set_vtype.bits := ZeroExt(debugVtype, XLEN) 199 csrio.vpu.set_vl.valid := ctrlBlock.io.robio.csr.vcsrFlag 200 csrio.vpu.set_vl.bits := ZeroExt(debugVl, XLEN) 201 csrio.exception := ctrlBlock.io.robio.exception 202 csrio.memExceptionVAddr := io.mem.exceptionVAddr 203 csrio.externalInterrupt := io.fromTop.externalInterrupt 204 csrio.distributedUpdate(0) := io.mem.csrDistributedUpdate 205 csrio.distributedUpdate(1) := io.frontendCsrDistributedUpdate 206 csrio.perf <> io.perf 207 private val fenceio = intExuBlock.io.fenceio.get 208 fenceio.disableSfence := csrio.disableSfence 209 io.fenceio <> fenceio 210 211 vfExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 212 for (i <- 0 until vfExuBlock.io.in.size) { 213 for (j <- 0 until vfExuBlock.io.in(i).size) { 214 NewPipelineConnect(dataPath.io.toFpExu(i)(j), vfExuBlock.io.in(i)(j), vfExuBlock.io.in(i)(j).fire, 215 Mux(dataPath.io.toFpExu(i)(j).fire, 216 dataPath.io.toFpExu(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush), 217 vfExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush))) 218 } 219 } 220 vfExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 221 222 wbDataPath.io.flush := ctrlBlock.io.redirect 223 wbDataPath.io.fromTop.hartId := io.fromTop.hartId 224 wbDataPath.io.fromIntExu <> intExuBlock.io.out 225 wbDataPath.io.fromVfExu <> vfExuBlock.io.out 226 wbDataPath.io.fromMemExu.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 227 sink.valid := source.valid 228 source.ready := sink.ready 229 sink.bits.data := source.bits.data 230 sink.bits.pdest := source.bits.uop.pdest 231 sink.bits.robIdx := source.bits.uop.robIdx 232 sink.bits.intWen.foreach(_ := source.bits.uop.rfWen) 233 sink.bits.fpWen.foreach(_ := source.bits.uop.fpWen) 234 sink.bits.vecWen.foreach(_ := source.bits.uop.vecWen) 235 sink.bits.exceptionVec.foreach(_ := source.bits.uop.exceptionVec) 236 sink.bits.flushPipe.foreach(_ := source.bits.uop.flushPipe) 237 sink.bits.replay.foreach(_ := source.bits.uop.replayInst) 238 sink.bits.debug := source.bits.debug 239 sink.bits.debugInfo := 0.U.asTypeOf(sink.bits.debugInfo) 240 sink.bits.lqIdx.foreach(_ := source.bits.uop.lqIdx) 241 sink.bits.sqIdx.foreach(_ := source.bits.uop.sqIdx) 242 sink.bits.ftqIdx.foreach(_ := source.bits.uop.ftqPtr) 243 sink.bits.ftqOffset.foreach(_ := source.bits.uop.ftqOffset) 244 } 245 246 // to mem 247 io.mem.redirect := ctrlBlock.io.redirect 248 io.mem.issueUops.zip(dataPath.io.toMemExu.flatten).foreach { case (sink, source) => 249 sink.valid := source.valid 250 source.ready := sink.ready 251 sink.bits.iqIdx := source.bits.iqIdx 252 sink.bits.isFirstIssue := source.bits.isFirstIssue 253 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 254 sink.bits.src := 0.U.asTypeOf(sink.bits.src) 255 sink.bits.src.zip(source.bits.src).foreach { case (l, r) => l := r} 256 sink.bits.uop.fuType := source.bits.fuType 257 sink.bits.uop.fuOpType := source.bits.fuOpType 258 sink.bits.uop.imm := source.bits.imm 259 sink.bits.uop.robIdx := source.bits.robIdx 260 sink.bits.uop.pdest := source.bits.pdest 261 sink.bits.uop.rfWen := source.bits.rfWen.getOrElse(false.B) 262 sink.bits.uop.fpWen := source.bits.fpWen.getOrElse(false.B) 263 sink.bits.uop.vecWen := source.bits.vecWen.getOrElse(false.B) 264 sink.bits.uop.flushPipe := source.bits.flushPipe.getOrElse(false.B) 265 sink.bits.uop.pc := source.bits.pc.getOrElse(0.U) 266 sink.bits.uop.lqIdx := source.bits.lqIdx.getOrElse(0.U.asTypeOf(new LqPtr)) 267 sink.bits.uop.sqIdx := source.bits.sqIdx.getOrElse(0.U.asTypeOf(new SqPtr)) 268 sink.bits.uop.ftqPtr := source.bits.ftqIdx.getOrElse(0.U.asTypeOf(new FtqPtr)) 269 sink.bits.uop.ftqOffset := source.bits.ftqOffset.getOrElse(0.U) 270 } 271 io.mem.loadFastMatch := memScheduler.io.toMem.get.loadFastMatch.map(_.fastMatch) 272 io.mem.loadFastImm := memScheduler.io.toMem.get.loadFastMatch.map(_.fastImm) 273 io.mem.tlbCsr := csrio.tlb 274 io.mem.csrCtrl := csrio.customCtrl 275 io.mem.sfence := fenceio.sfence 276 io.mem.isStoreException := CommitType.lsInstIsStore(ctrlBlock.io.robio.exception.bits.commitType) 277 require(io.mem.loadPcRead.size == params.LduCnt) 278 io.mem.loadPcRead.zipWithIndex.foreach { case (loadPcRead, i) => 279 loadPcRead.data := ctrlBlock.io.memLdPcRead(i).data 280 ctrlBlock.io.memLdPcRead(i).ptr := loadPcRead.ptr 281 ctrlBlock.io.memLdPcRead(i).offset := loadPcRead.offset 282 } 283 // mem io 284 io.mem.lsqEnqIO <> memScheduler.io.memIO.get.lsqEnqIO 285 io.mem.robLsqIO <> ctrlBlock.io.robio.lsq 286 io.mem.toSbuffer <> fenceio.sbuffer 287 288 io.frontendSfence := fenceio.sfence 289 io.frontendTlbCsr := csrio.tlb 290 io.frontendCsrCtrl := csrio.customCtrl 291 292 io.tlb <> csrio.tlb 293 294 io.csrCustomCtrl := csrio.customCtrl 295 296 dontTouch(memScheduler.io) 297 dontTouch(io.mem) 298 dontTouch(dataPath.io.toMemExu) 299 dontTouch(wbDataPath.io.fromMemExu) 300} 301 302class BackendMemIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 303 // params alias 304 private val LoadQueueSize = VirtualLoadQueueSize 305 // In/Out // Todo: split it into one-direction bundle 306 val lsqEnqIO = Flipped(new LsqEnqIO) 307 val robLsqIO = new RobLsqIO 308 val toSbuffer = new FenceToSbuffer 309 val ldaIqFeedback = Vec(params.LduCnt, Flipped(new MemRSFeedbackIO)) 310 val staIqFeedback = Vec(params.StaCnt, Flipped(new MemRSFeedbackIO)) 311 val loadPcRead = Vec(params.LduCnt, Flipped(new FtqRead(UInt(VAddrBits.W)))) 312 313 // Input 314 val writeBack = MixedVec(Seq.fill(params.LduCnt + params.StaCnt * 2)(Flipped(DecoupledIO(new MemExuOutput()))) ++ Seq.fill(params.VlduCnt)(Flipped(DecoupledIO(new MemExuOutput(true))))) 315 316 val s3_delayed_load_error = Input(Vec(LoadPipelineWidth, Bool())) 317 val stIn = Input(Vec(params.StaCnt, ValidIO(new DynInst()))) 318 val memoryViolation = Flipped(ValidIO(new Redirect)) 319 val exceptionVAddr = Input(UInt(VAddrBits.W)) 320 val sqDeq = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) 321 val lqDeq = Input(UInt(log2Up(CommitWidth + 1).W)) 322 323 val lqCancelCnt = Input(UInt(log2Up(VirtualLoadQueueSize + 1).W)) 324 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 325 326 val otherFastWakeup = Flipped(Vec(params.LduCnt + 2 * params.StaCnt, ValidIO(new DynInst))) 327 val stIssuePtr = Input(new SqPtr()) 328 329 val csrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 330 331 // Output 332 val redirect = ValidIO(new Redirect) // rob flush MemBlock 333 val issueUops = MixedVec(Seq.fill(params.LduCnt + params.StaCnt * 2)(DecoupledIO(new MemExuInput())) ++ Seq.fill(params.VlduCnt)(DecoupledIO(new MemExuInput(true)))) 334 val loadFastMatch = Vec(params.LduCnt, Output(UInt(params.LduCnt.W))) 335 val loadFastImm = Vec(params.LduCnt, Output(UInt(12.W))) // Imm_I 336 337 val tlbCsr = Output(new TlbCsrBundle) 338 val csrCtrl = Output(new CustomCSRCtrlIO) 339 val sfence = Output(new SfenceBundle) 340 val isStoreException = Output(Bool()) 341} 342 343class BackendIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 344 val fromTop = new Bundle { 345 val hartId = Input(UInt(8.W)) 346 val externalInterrupt = new ExternalInterruptIO 347 } 348 349 val toTop = new Bundle { 350 val cpuHalted = Output(Bool()) 351 } 352 353 val fenceio = new FenceIO 354 // Todo: merge these bundles into BackendFrontendIO 355 val frontend = Flipped(new FrontendToCtrlIO) 356 val frontendSfence = Output(new SfenceBundle) 357 val frontendCsrCtrl = Output(new CustomCSRCtrlIO) 358 val frontendTlbCsr = Output(new TlbCsrBundle) 359 // distributed csr write 360 val frontendCsrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 361 362 val mem = new BackendMemIO 363 364 val perf = Input(new PerfCounterIO) 365 366 val tlb = Output(new TlbCsrBundle) 367 368 val csrCustomCtrl = Output(new CustomCSRCtrlIO) 369} 370