1package xiangshan.backend 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utils.OptionWrapper 7import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 8import utility.{PipelineConnect, ZeroExt} 9import xiangshan._ 10import xiangshan.backend.Bundles.{DynInst, MemExuInput, MemExuOutput} 11import xiangshan.backend.ctrlblock.CtrlBlock 12import xiangshan.backend.datapath.WbConfig._ 13import xiangshan.backend.datapath.{DataPath, NewPipelineConnect, WbDataPath, WbFuBusyTable} 14import xiangshan.backend.exu.ExuBlock 15import xiangshan.backend.fu.vector.Bundles.{VConfig, VType} 16import xiangshan.backend.fu.{FenceIO, FenceToSbuffer, FuConfig, PerfCounterIO} 17import xiangshan.backend.issue.{Scheduler, IntScheduler, MemScheduler, VfScheduler} 18import xiangshan.backend.rob.RobLsqIO 19import xiangshan.frontend.{FtqPtr, FtqRead} 20import xiangshan.mem.{LqPtr, LsqEnqIO, SqPtr} 21 22class Backend(val params: BackendParams)(implicit p: Parameters) extends LazyModule 23 with HasXSParameter { 24 25 /* Only update the idx in mem-scheduler here 26 * Idx in other schedulers can be updated the same way if needed 27 * 28 * Also note that we filter out the 'stData issue-queues' when counting 29 */ 30 for ((ibp, idx) <- params.memSchdParams.get.issueBlockParams.filter(iq => iq.StdCnt == 0).zipWithIndex) { 31 ibp.updateIdx(idx) 32 } 33 34 println(params.iqWakeUpParams) 35 36 for ((schdCfg, i) <- params.allSchdParams.zipWithIndex) { 37 schdCfg.bindBackendParam(params) 38 } 39 40 for ((iqCfg, i) <- params.allIssueParams.zipWithIndex) { 41 iqCfg.bindBackendParam(params) 42 } 43 44 for ((exuCfg, i) <- params.allExuParams.zipWithIndex) { 45 exuCfg.updateIQWakeUpConfigs(params.iqWakeUpParams) 46 exuCfg.updateExuIdx(i) 47 exuCfg.bindBackendParam(params) 48 } 49 50 println("[Backend] ExuConfigs:") 51 for (exuCfg <- params.allExuParams) { 52 val fuConfigs = exuCfg.fuConfigs 53 val wbPortConfigs = exuCfg.wbPortConfigs 54 val immType = exuCfg.immType 55 56 println("[Backend] " + 57 s"${exuCfg.name}: " + 58 s"${ fuConfigs.map(_.name).mkString("fu(s): {", ",", "}") }, " + 59 s"${ wbPortConfigs.mkString("wb: {", ",", "}") }, " + 60 s"${ immType.map(SelImm.mkString(_)).mkString("imm: {", "," , "}") }, " + 61 s"latMax(${exuCfg.latencyValMax}), ${exuCfg.fuLatancySet.mkString("lat: {",",","}")}, ") 62 require(wbPortConfigs.collectFirst { case x: IntWB => x }.nonEmpty == 63 fuConfigs.map(_.writeIntRf).reduce(_ || _), 64 "int wb port has no priority" ) 65 require(wbPortConfigs.collectFirst { case x: VfWB => x }.nonEmpty == 66 fuConfigs.map(x => x.writeFpRf || x.writeVecRf).reduce(_ || _), 67 "vec wb port has no priority" ) 68 } 69 70 for (cfg <- FuConfig.allConfigs) { 71 println(s"[Backend] $cfg") 72 } 73 74 val ctrlBlock = LazyModule(new CtrlBlock(params)) 75 val intScheduler = params.intSchdParams.map(x => LazyModule(new Scheduler(x))) 76 val vfScheduler = params.vfSchdParams.map(x => LazyModule(new Scheduler(x))) 77 val memScheduler = params.memSchdParams.map(x => LazyModule(new Scheduler(x))) 78 val dataPath = LazyModule(new DataPath(params)) 79 val intExuBlock = params.intSchdParams.map(x => LazyModule(new ExuBlock(x))) 80 val vfExuBlock = params.vfSchdParams.map(x => LazyModule(new ExuBlock(x))) 81 val wbFuBusyTable = LazyModule(new WbFuBusyTable(params)) 82 83 lazy val module = new BackendImp(this) 84} 85 86class BackendImp(override val wrapper: Backend)(implicit p: Parameters) extends LazyModuleImp(wrapper) 87 with HasXSParameter{ 88 implicit private val params = wrapper.params 89 val io = IO(new BackendIO()(p, wrapper.params)) 90 91 private val ctrlBlock = wrapper.ctrlBlock.module 92 private val intScheduler = wrapper.intScheduler.get.module 93 private val vfScheduler = wrapper.vfScheduler.get.module 94 private val memScheduler = wrapper.memScheduler.get.module 95 private val dataPath = wrapper.dataPath.module 96 private val intExuBlock = wrapper.intExuBlock.get.module 97 private val vfExuBlock = wrapper.vfExuBlock.get.module 98 private val wbDataPath = Module(new WbDataPath(params)) 99 private val wbFuBusyTable = wrapper.wbFuBusyTable.module 100 101 private val iqWakeUpMappedBundle: Map[String, ValidIO[Bundles.IssueQueueWakeUpBundle]] = ( 102 intScheduler.io.toSchedulers.wakeupVec ++ 103 vfScheduler.io.toSchedulers.wakeupVec ++ 104 memScheduler.io.toSchedulers.wakeupVec 105 ).map(x => (x.bits.wakeupSource, x)).toMap 106 107 println(s"[Backend] iq wake up keys: ${iqWakeUpMappedBundle.keys}") 108 109 wbFuBusyTable.io.in.intSchdBusyTable := intScheduler.io.wbFuBusyTable 110 wbFuBusyTable.io.in.vfSchdBusyTable := vfScheduler.io.wbFuBusyTable 111 wbFuBusyTable.io.in.memSchdBusyTable := memScheduler.io.wbFuBusyTable 112 intScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.intRespRead 113 vfScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.vfRespRead 114 memScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.memRespRead 115 dataPath.io.wbConfictRead := wbFuBusyTable.io.out.wbConflictRead 116 117 wbDataPath.io.fromIntExu.flatten.filter(x => x.bits.params.writeIntRf) 118 119 private val vconfig = dataPath.io.vconfigReadPort.data 120 121 ctrlBlock.io.fromTop.hartId := io.fromTop.hartId 122 ctrlBlock.io.frontend <> io.frontend 123 ctrlBlock.io.fromWB.wbData <> wbDataPath.io.toCtrlBlock.writeback 124 ctrlBlock.io.fromMem.stIn <> io.mem.stIn 125 ctrlBlock.io.fromMem.violation <> io.mem.memoryViolation 126 ctrlBlock.io.csrCtrl <> intExuBlock.io.csrio.get.customCtrl 127 ctrlBlock.io.robio.csr.intrBitSet := intExuBlock.io.csrio.get.interrupt 128 ctrlBlock.io.robio.csr.trapTarget := intExuBlock.io.csrio.get.trapTarget 129 ctrlBlock.io.robio.csr.isXRet := intExuBlock.io.csrio.get.isXRet 130 ctrlBlock.io.robio.csr.wfiEvent := intExuBlock.io.csrio.get.wfi_event 131 ctrlBlock.io.robio.lsq <> io.mem.robLsqIO 132 ctrlBlock.io.fromDataPath.vtype := vconfig(7, 0).asTypeOf(new VType) 133 134 intScheduler.io.fromTop.hartId := io.fromTop.hartId 135 intScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 136 intScheduler.io.fromCtrlBlock.pcVec := ctrlBlock.io.toIssueBlock.pcVec 137 intScheduler.io.fromCtrlBlock.targetVec := ctrlBlock.io.toIssueBlock.targetVec 138 intScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 139 intScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.intUops 140 intScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 141 intScheduler.io.vfWriteBack := 0.U.asTypeOf(intScheduler.io.vfWriteBack) 142 intScheduler.io.fromDataPath := dataPath.io.toIntIQ 143 intScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.wakeupSource) } 144 145 memScheduler.io.fromTop.hartId := io.fromTop.hartId 146 memScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 147 memScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 148 memScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.memUops 149 memScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 150 memScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 151 memScheduler.io.fromMem.get.scommit := io.mem.sqDeq 152 memScheduler.io.fromMem.get.lcommit := io.mem.lqDeq 153 memScheduler.io.fromMem.get.sqCancelCnt := io.mem.sqCancelCnt 154 memScheduler.io.fromMem.get.lqCancelCnt := io.mem.lqCancelCnt 155 memScheduler.io.fromMem.get.stIssuePtr := io.mem.stIssuePtr 156 memScheduler.io.fromMem.get.memWaitUpdateReq.staIssue.zip(io.mem.stIn).foreach { case (sink, source) => 157 sink.valid := source.valid 158 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 159 sink.bits.uop.robIdx := source.bits.robIdx 160 } 161 memScheduler.io.fromDataPath := dataPath.io.toMemIQ 162 memScheduler.io.fromMem.get.ldaFeedback := io.mem.ldaIqFeedback 163 memScheduler.io.fromMem.get.staFeedback := io.mem.staIqFeedback 164 memScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.wakeupSource) } 165 166 vfScheduler.io.fromTop.hartId := io.fromTop.hartId 167 vfScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 168 vfScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 169 vfScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.vfUops 170 vfScheduler.io.intWriteBack := 0.U.asTypeOf(vfScheduler.io.intWriteBack) 171 vfScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 172 vfScheduler.io.fromDataPath := dataPath.io.toVfIQ 173 vfScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.wakeupSource) } 174 175 dataPath.io.flush := ctrlBlock.io.toDataPath.flush 176 dataPath.io.vconfigReadPort.addr := ctrlBlock.io.toDataPath.vtypeAddr 177 178 for (i <- 0 until dataPath.io.fromIntIQ.length) { 179 for (j <- 0 until dataPath.io.fromIntIQ(i).length) { 180 NewPipelineConnect(intScheduler.io.toDataPath(i)(j), dataPath.io.fromIntIQ(i)(j), dataPath.io.fromIntIQ(i)(j).valid, 181 intScheduler.io.toDataPath(i)(j).bits.common.robIdx.needFlush(ctrlBlock.io.toDataPath.flush), Option("intScheduler2DataPathPipe")) 182 } 183 } 184 185 for (i <- 0 until dataPath.io.fromVfIQ.length) { 186 for (j <- 0 until dataPath.io.fromVfIQ(i).length) { 187 NewPipelineConnect(vfScheduler.io.toDataPath(i)(j), dataPath.io.fromVfIQ(i)(j), dataPath.io.fromVfIQ(i)(j).valid, 188 vfScheduler.io.toDataPath(i)(j).bits.common.robIdx.needFlush(ctrlBlock.io.toDataPath.flush), Option("vfScheduler2DataPathPipe")) 189 } 190 } 191 192 for (i <- 0 until dataPath.io.fromMemIQ.length) { 193 for (j <- 0 until dataPath.io.fromMemIQ(i).length) { 194 NewPipelineConnect(memScheduler.io.toDataPath(i)(j), dataPath.io.fromMemIQ(i)(j), dataPath.io.fromMemIQ(i)(j).valid, 195 memScheduler.io.toDataPath(i)(j).bits.common.robIdx.needFlush(ctrlBlock.io.toDataPath.flush), Option("memScheduler2DataPathPipe")) 196 } 197 } 198 199 println(s"[Backend] wbDataPath.io.toIntPreg: ${wbDataPath.io.toIntPreg.size}, dataPath.io.fromIntWb: ${dataPath.io.fromIntWb.size}") 200 println(s"[Backend] wbDataPath.io.toVfPreg: ${wbDataPath.io.toVfPreg.size}, dataPath.io.fromFpWb: ${dataPath.io.fromVfWb.size}") 201 dataPath.io.fromIntWb := wbDataPath.io.toIntPreg 202 dataPath.io.fromVfWb := wbDataPath.io.toVfPreg 203 dataPath.io.debugIntRat := ctrlBlock.io.debug_int_rat 204 dataPath.io.debugFpRat := ctrlBlock.io.debug_fp_rat 205 dataPath.io.debugVecRat := ctrlBlock.io.debug_vec_rat 206 dataPath.io.debugVconfigRat := ctrlBlock.io.debug_vconfig_rat 207 208 intExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 209 for (i <- 0 until intExuBlock.io.in.length) { 210 for (j <- 0 until intExuBlock.io.in(i).length) { 211 NewPipelineConnect(dataPath.io.toIntExu(i)(j), intExuBlock.io.in(i)(j), intExuBlock.io.in(i)(j).fire, 212 Mux(dataPath.io.toIntExu(i)(j).fire, 213 dataPath.io.toIntExu(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush), 214 intExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush))) 215 } 216 } 217 218 private val csrio = intExuBlock.io.csrio.get 219 csrio.hartId := io.fromTop.hartId 220 csrio.perf.retiredInstr <> ctrlBlock.io.robio.csr.perfinfo.retiredInstr 221 csrio.perf.ctrlInfo <> ctrlBlock.io.perfInfo.ctrlInfo 222 csrio.perf.perfEventsCtrl <> ctrlBlock.getPerf 223 csrio.fpu.fflags := ctrlBlock.io.robio.csr.fflags 224 csrio.fpu.isIllegal := false.B // Todo: remove it 225 csrio.fpu.dirty_fs := ctrlBlock.io.robio.csr.dirty_fs 226 csrio.vpu <> 0.U.asTypeOf(csrio.vpu) // Todo 227 228 val debugVconfig = dataPath.io.debugVconfig.asTypeOf(new VConfig) 229 val debugVtype = VType.toVtypeStruct(debugVconfig.vtype).asUInt 230 val debugVl = debugVconfig.vl 231 csrio.vpu.set_vxsat := ctrlBlock.io.robio.csr.vxsat 232 csrio.vpu.set_vstart.valid := ctrlBlock.io.robio.csr.vcsrFlag 233 csrio.vpu.set_vstart.bits := 0.U 234 csrio.vpu.set_vtype.valid := ctrlBlock.io.robio.csr.vcsrFlag 235 csrio.vpu.set_vtype.bits := ZeroExt(debugVtype, XLEN) 236 csrio.vpu.set_vl.valid := ctrlBlock.io.robio.csr.vcsrFlag 237 csrio.vpu.set_vl.bits := ZeroExt(debugVl, XLEN) 238 csrio.exception := ctrlBlock.io.robio.exception 239 csrio.memExceptionVAddr := io.mem.exceptionVAddr 240 csrio.externalInterrupt := io.fromTop.externalInterrupt 241 csrio.distributedUpdate(0) := io.mem.csrDistributedUpdate 242 csrio.distributedUpdate(1) := io.frontendCsrDistributedUpdate 243 csrio.perf <> io.perf 244 private val fenceio = intExuBlock.io.fenceio.get 245 fenceio.disableSfence := csrio.disableSfence 246 io.fenceio <> fenceio 247 248 vfExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 249 for (i <- 0 until vfExuBlock.io.in.size) { 250 for (j <- 0 until vfExuBlock.io.in(i).size) { 251 NewPipelineConnect(dataPath.io.toFpExu(i)(j), vfExuBlock.io.in(i)(j), vfExuBlock.io.in(i)(j).fire, 252 Mux(dataPath.io.toFpExu(i)(j).fire, 253 dataPath.io.toFpExu(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush), 254 vfExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush))) 255 } 256 } 257 vfExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 258 259 wbDataPath.io.flush := ctrlBlock.io.redirect 260 wbDataPath.io.fromTop.hartId := io.fromTop.hartId 261 wbDataPath.io.fromIntExu <> intExuBlock.io.out 262 wbDataPath.io.fromVfExu <> vfExuBlock.io.out 263 wbDataPath.io.fromMemExu.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 264 sink.valid := source.valid 265 source.ready := sink.ready 266 sink.bits.data := source.bits.data 267 sink.bits.pdest := source.bits.uop.pdest 268 sink.bits.robIdx := source.bits.uop.robIdx 269 sink.bits.intWen.foreach(_ := source.bits.uop.rfWen) 270 sink.bits.fpWen.foreach(_ := source.bits.uop.fpWen) 271 sink.bits.vecWen.foreach(_ := source.bits.uop.vecWen) 272 sink.bits.exceptionVec.foreach(_ := source.bits.uop.exceptionVec) 273 sink.bits.flushPipe.foreach(_ := source.bits.uop.flushPipe) 274 sink.bits.replay.foreach(_ := source.bits.uop.replayInst) 275 sink.bits.debug := source.bits.debug 276 sink.bits.debugInfo := 0.U.asTypeOf(sink.bits.debugInfo) 277 sink.bits.lqIdx.foreach(_ := source.bits.uop.lqIdx) 278 sink.bits.sqIdx.foreach(_ := source.bits.uop.sqIdx) 279 sink.bits.ftqIdx.foreach(_ := source.bits.uop.ftqPtr) 280 sink.bits.ftqOffset.foreach(_ := source.bits.uop.ftqOffset) 281 } 282 283 // to mem 284 io.mem.redirect := ctrlBlock.io.redirect 285 io.mem.issueUops.zip(dataPath.io.toMemExu.flatten).foreach { case (sink, source) => 286 sink.valid := source.valid 287 source.ready := sink.ready 288 sink.bits.iqIdx := source.bits.iqIdx 289 sink.bits.isFirstIssue := source.bits.isFirstIssue 290 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 291 sink.bits.src := 0.U.asTypeOf(sink.bits.src) 292 sink.bits.src.zip(source.bits.src).foreach { case (l, r) => l := r} 293 sink.bits.uop.fuType := source.bits.fuType 294 sink.bits.uop.fuOpType := source.bits.fuOpType 295 sink.bits.uop.imm := source.bits.imm 296 sink.bits.uop.robIdx := source.bits.robIdx 297 sink.bits.uop.pdest := source.bits.pdest 298 sink.bits.uop.rfWen := source.bits.rfWen.getOrElse(false.B) 299 sink.bits.uop.fpWen := source.bits.fpWen.getOrElse(false.B) 300 sink.bits.uop.vecWen := source.bits.vecWen.getOrElse(false.B) 301 sink.bits.uop.flushPipe := source.bits.flushPipe.getOrElse(false.B) 302 sink.bits.uop.pc := source.bits.pc.getOrElse(0.U) 303 sink.bits.uop.lqIdx := source.bits.lqIdx.getOrElse(0.U.asTypeOf(new LqPtr)) 304 sink.bits.uop.sqIdx := source.bits.sqIdx.getOrElse(0.U.asTypeOf(new SqPtr)) 305 sink.bits.uop.ftqPtr := source.bits.ftqIdx.getOrElse(0.U.asTypeOf(new FtqPtr)) 306 sink.bits.uop.ftqOffset := source.bits.ftqOffset.getOrElse(0.U) 307 } 308 io.mem.loadFastMatch := memScheduler.io.toMem.get.loadFastMatch.map(_.fastMatch) 309 io.mem.loadFastImm := memScheduler.io.toMem.get.loadFastMatch.map(_.fastImm) 310 io.mem.tlbCsr := csrio.tlb 311 io.mem.csrCtrl := csrio.customCtrl 312 io.mem.sfence := fenceio.sfence 313 io.mem.isStoreException := CommitType.lsInstIsStore(ctrlBlock.io.robio.exception.bits.commitType) 314 require(io.mem.loadPcRead.size == params.LduCnt) 315 io.mem.loadPcRead.zipWithIndex.foreach { case (loadPcRead, i) => 316 loadPcRead.data := ctrlBlock.io.memLdPcRead(i).data 317 ctrlBlock.io.memLdPcRead(i).ptr := loadPcRead.ptr 318 ctrlBlock.io.memLdPcRead(i).offset := loadPcRead.offset 319 } 320 // mem io 321 io.mem.lsqEnqIO <> memScheduler.io.memIO.get.lsqEnqIO 322 io.mem.robLsqIO <> ctrlBlock.io.robio.lsq 323 io.mem.toSbuffer <> fenceio.sbuffer 324 325 io.frontendSfence := fenceio.sfence 326 io.frontendTlbCsr := csrio.tlb 327 io.frontendCsrCtrl := csrio.customCtrl 328 329 io.tlb <> csrio.tlb 330 331 io.csrCustomCtrl := csrio.customCtrl 332 333 dontTouch(memScheduler.io) 334 dontTouch(io.mem) 335 dontTouch(dataPath.io.toMemExu) 336 dontTouch(wbDataPath.io.fromMemExu) 337} 338 339class BackendMemIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 340 // params alias 341 private val LoadQueueSize = VirtualLoadQueueSize 342 // In/Out // Todo: split it into one-direction bundle 343 val lsqEnqIO = Flipped(new LsqEnqIO) 344 val robLsqIO = new RobLsqIO 345 val toSbuffer = new FenceToSbuffer 346 val ldaIqFeedback = Vec(params.LduCnt, Flipped(new MemRSFeedbackIO)) 347 val staIqFeedback = Vec(params.StaCnt, Flipped(new MemRSFeedbackIO)) 348 val loadPcRead = Vec(params.LduCnt, Flipped(new FtqRead(UInt(VAddrBits.W)))) 349 350 // Input 351 val writeBack = MixedVec(Seq.fill(params.LduCnt + params.StaCnt * 2)(Flipped(DecoupledIO(new MemExuOutput()))) ++ Seq.fill(params.VlduCnt)(Flipped(DecoupledIO(new MemExuOutput(true))))) 352 353 val s3_delayed_load_error = Input(Vec(LoadPipelineWidth, Bool())) 354 val stIn = Input(Vec(params.StaCnt, ValidIO(new DynInst()))) 355 val memoryViolation = Flipped(ValidIO(new Redirect)) 356 val exceptionVAddr = Input(UInt(VAddrBits.W)) 357 val sqDeq = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) 358 val lqDeq = Input(UInt(log2Up(CommitWidth + 1).W)) 359 360 val lqCancelCnt = Input(UInt(log2Up(VirtualLoadQueueSize + 1).W)) 361 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 362 363 val otherFastWakeup = Flipped(Vec(params.LduCnt + 2 * params.StaCnt, ValidIO(new DynInst))) 364 val stIssuePtr = Input(new SqPtr()) 365 366 val csrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 367 368 // Output 369 val redirect = ValidIO(new Redirect) // rob flush MemBlock 370 val issueUops = MixedVec(Seq.fill(params.LduCnt + params.StaCnt * 2)(DecoupledIO(new MemExuInput())) ++ Seq.fill(params.VlduCnt)(DecoupledIO(new MemExuInput(true)))) 371 val loadFastMatch = Vec(params.LduCnt, Output(UInt(params.LduCnt.W))) 372 val loadFastImm = Vec(params.LduCnt, Output(UInt(12.W))) // Imm_I 373 374 val tlbCsr = Output(new TlbCsrBundle) 375 val csrCtrl = Output(new CustomCSRCtrlIO) 376 val sfence = Output(new SfenceBundle) 377 val isStoreException = Output(Bool()) 378} 379 380class BackendIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 381 val fromTop = new Bundle { 382 val hartId = Input(UInt(8.W)) 383 val externalInterrupt = new ExternalInterruptIO 384 } 385 386 val toTop = new Bundle { 387 val cpuHalted = Output(Bool()) 388 } 389 390 val fenceio = new FenceIO 391 // Todo: merge these bundles into BackendFrontendIO 392 val frontend = Flipped(new FrontendToCtrlIO) 393 val frontendSfence = Output(new SfenceBundle) 394 val frontendCsrCtrl = Output(new CustomCSRCtrlIO) 395 val frontendTlbCsr = Output(new TlbCsrBundle) 396 // distributed csr write 397 val frontendCsrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 398 399 val mem = new BackendMemIO 400 401 val perf = Input(new PerfCounterIO) 402 403 val tlb = Output(new TlbCsrBundle) 404 405 val csrCustomCtrl = Output(new CustomCSRCtrlIO) 406} 407