1package xiangshan.backend 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import utility.ZeroExt 8import xiangshan._ 9import xiangshan.backend.Bundles.{DynInst, IssueQueueIQWakeUpBundle, LoadShouldCancel, MemExuInput, MemExuOutput, VPUCtrlSignals} 10import xiangshan.backend.ctrlblock.{DebugLSIO, LsTopdownInfo} 11import xiangshan.backend.datapath.DataConfig.{IntData, VecData} 12import xiangshan.backend.datapath.RdConfig.{IntRD, VfRD} 13import xiangshan.backend.datapath.WbConfig._ 14import xiangshan.backend.datapath._ 15import xiangshan.backend.dispatch.CoreDispatchTopDownIO 16import xiangshan.backend.exu.ExuBlock 17import xiangshan.backend.fu.vector.Bundles.{VConfig, VType} 18import xiangshan.backend.fu.{FenceIO, FenceToSbuffer, FuConfig, FuType, PerfCounterIO} 19import xiangshan.backend.issue.{CancelNetwork, Scheduler, SchedulerImpBase} 20import xiangshan.backend.rob.{RobCoreTopDownIO, RobDebugRollingIO, RobLsqIO} 21import xiangshan.frontend.{FtqPtr, FtqRead, PreDecodeInfo} 22import xiangshan.mem.{LqPtr, LsqEnqIO, SqPtr} 23 24class Backend(val params: BackendParams)(implicit p: Parameters) extends LazyModule 25 with HasXSParameter { 26 27 override def shouldBeInlined: Boolean = false 28 29 /* Only update the idx in mem-scheduler here 30 * Idx in other schedulers can be updated the same way if needed 31 * 32 * Also note that we filter out the 'stData issue-queues' when counting 33 */ 34 for ((ibp, idx) <- params.memSchdParams.get.issueBlockParams.filter(iq => iq.StdCnt == 0 && iq.VstdCnt == 0).zipWithIndex) { 35 ibp.updateIdx(idx) 36 } 37 38 println(params.iqWakeUpParams) 39 40 for ((schdCfg, i) <- params.allSchdParams.zipWithIndex) { 41 schdCfg.bindBackendParam(params) 42 } 43 44 for ((iqCfg, i) <- params.allIssueParams.zipWithIndex) { 45 iqCfg.bindBackendParam(params) 46 } 47 48 for ((exuCfg, i) <- params.allExuParams.zipWithIndex) { 49 exuCfg.bindBackendParam(params) 50 exuCfg.updateIQWakeUpConfigs(params.iqWakeUpParams) 51 exuCfg.updateExuIdx(i) 52 } 53 54 println("[Backend] ExuConfigs:") 55 for (exuCfg <- params.allExuParams) { 56 val fuConfigs = exuCfg.fuConfigs 57 val wbPortConfigs = exuCfg.wbPortConfigs 58 val immType = exuCfg.immType 59 60 println("[Backend] " + 61 s"${exuCfg.name}: " + 62 (if (exuCfg.fakeUnit) "fake, " else "") + 63 (if (exuCfg.hasLoadFu || exuCfg.hasHyldaFu) s"LdExuIdx(${backendParams.getLdExuIdx(exuCfg)})" else "") + 64 s"${fuConfigs.map(_.name).mkString("fu(s): {", ",", "}")}, " + 65 s"${wbPortConfigs.mkString("wb: {", ",", "}")}, " + 66 s"${immType.map(SelImm.mkString(_)).mkString("imm: {", ",", "}")}, " + 67 s"latMax(${exuCfg.latencyValMax}), ${exuCfg.fuLatancySet.mkString("lat: {", ",", "}")}, " + 68 s"srcReg(${exuCfg.numRegSrc})" 69 ) 70 require( 71 wbPortConfigs.collectFirst { case x: IntWB => x }.nonEmpty == 72 fuConfigs.map(_.writeIntRf).reduce(_ || _), 73 s"${exuCfg.name} int wb port has no priority" 74 ) 75 require( 76 wbPortConfigs.collectFirst { case x: VfWB => x }.nonEmpty == 77 fuConfigs.map(x => x.writeFpRf || x.writeVecRf).reduce(_ || _), 78 s"${exuCfg.name} vec wb port has no priority" 79 ) 80 } 81 82 println(s"[Backend] all fu configs") 83 for (cfg <- FuConfig.allConfigs) { 84 println(s"[Backend] $cfg") 85 } 86 87 println(s"[Backend] Int RdConfigs: ExuName(Priority)") 88 for ((port, seq) <- params.getRdPortParams(IntData())) { 89 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 90 } 91 92 println(s"[Backend] Int WbConfigs: ExuName(Priority)") 93 for ((port, seq) <- params.getWbPortParams(IntData())) { 94 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 95 } 96 97 println(s"[Backend] Vf RdConfigs: ExuName(Priority)") 98 for ((port, seq) <- params.getRdPortParams(VecData())) { 99 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 100 } 101 102 println(s"[Backend] Vf WbConfigs: ExuName(Priority)") 103 for ((port, seq) <- params.getWbPortParams(VecData())) { 104 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 105 } 106 107 println(s"[Backend] Dispatch Configs:") 108 println(s"[Backend] Load IQ enq width(${params.numLoadDp}), Store IQ enq width(${params.numStoreDp})") 109 println(s"[Backend] Load DP width(${LSQLdEnqWidth}), Store DP width(${LSQStEnqWidth})") 110 111 val ctrlBlock = LazyModule(new CtrlBlock(params)) 112 val pcTargetMem = LazyModule(new PcTargetMem(params)) 113 val intScheduler = params.intSchdParams.map(x => LazyModule(new Scheduler(x))) 114 val vfScheduler = params.vfSchdParams.map(x => LazyModule(new Scheduler(x))) 115 val memScheduler = params.memSchdParams.map(x => LazyModule(new Scheduler(x))) 116 val cancelNetwork = LazyModule(new CancelNetwork(params)) 117 val dataPath = LazyModule(new DataPath(params)) 118 val intExuBlock = params.intSchdParams.map(x => LazyModule(new ExuBlock(x))) 119 val vfExuBlock = params.vfSchdParams.map(x => LazyModule(new ExuBlock(x))) 120 val wbFuBusyTable = LazyModule(new WbFuBusyTable(params)) 121 122 lazy val module = new BackendImp(this) 123} 124 125class BackendImp(override val wrapper: Backend)(implicit p: Parameters) extends LazyModuleImp(wrapper) 126 with HasXSParameter { 127 implicit private val params = wrapper.params 128 129 val io = IO(new BackendIO()(p, wrapper.params)) 130 131 private val ctrlBlock = wrapper.ctrlBlock.module 132 private val pcTargetMem = wrapper.pcTargetMem.module 133 private val intScheduler: SchedulerImpBase = wrapper.intScheduler.get.module 134 private val vfScheduler = wrapper.vfScheduler.get.module 135 private val memScheduler = wrapper.memScheduler.get.module 136 private val cancelNetwork = wrapper.cancelNetwork.module 137 private val dataPath = wrapper.dataPath.module 138 private val intExuBlock = wrapper.intExuBlock.get.module 139 private val vfExuBlock = wrapper.vfExuBlock.get.module 140 private val bypassNetwork = Module(new BypassNetwork) 141 private val wbDataPath = Module(new WbDataPath(params)) 142 private val wbFuBusyTable = wrapper.wbFuBusyTable.module 143 144 private val iqWakeUpMappedBundle: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = ( 145 intScheduler.io.toSchedulers.wakeupVec ++ 146 vfScheduler.io.toSchedulers.wakeupVec ++ 147 memScheduler.io.toSchedulers.wakeupVec 148 ).map(x => (x.bits.exuIdx, x)).toMap 149 150 println(s"[Backend] iq wake up keys: ${iqWakeUpMappedBundle.keys}") 151 152 wbFuBusyTable.io.in.intSchdBusyTable := intScheduler.io.wbFuBusyTable 153 wbFuBusyTable.io.in.vfSchdBusyTable := vfScheduler.io.wbFuBusyTable 154 wbFuBusyTable.io.in.memSchdBusyTable := memScheduler.io.wbFuBusyTable 155 intScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.intRespRead 156 vfScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.vfRespRead 157 memScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.memRespRead 158 dataPath.io.wbConfictRead := wbFuBusyTable.io.out.wbConflictRead 159 160 wbDataPath.io.fromIntExu.flatten.filter(x => x.bits.params.writeIntRf) 161 162 private val vconfig = dataPath.io.vconfigReadPort.data 163 private val og1CancelOH: UInt = dataPath.io.og1CancelOH 164 private val og0CancelOHFromDataPath: UInt = dataPath.io.og0CancelOH 165 private val og0CancelOHFromCancelNet: UInt = cancelNetwork.io.out.og0CancelOH 166 private val og0CancelOHFromFinalIssue: UInt = Wire(chiselTypeOf(dataPath.io.og0CancelOH)) 167 private val og0CancelOH: UInt = og0CancelOHFromDataPath | og0CancelOHFromCancelNet | og0CancelOHFromFinalIssue 168 private val cancelToBusyTable = dataPath.io.cancelToBusyTable 169 170 ctrlBlock.io.fromTop.hartId := io.fromTop.hartId 171 ctrlBlock.io.frontend <> io.frontend 172 ctrlBlock.io.fromWB.wbData <> wbDataPath.io.toCtrlBlock.writeback 173 ctrlBlock.io.fromMem.stIn <> io.mem.stIn 174 ctrlBlock.io.fromMem.violation <> io.mem.memoryViolation 175 ctrlBlock.io.lqCanAccept := io.mem.lqCanAccept 176 ctrlBlock.io.sqCanAccept := io.mem.sqCanAccept 177 ctrlBlock.io.csrCtrl <> intExuBlock.io.csrio.get.customCtrl 178 ctrlBlock.io.robio.csr.intrBitSet := intExuBlock.io.csrio.get.interrupt 179 ctrlBlock.io.robio.csr.trapTarget := intExuBlock.io.csrio.get.trapTarget 180 ctrlBlock.io.robio.csr.isXRet := intExuBlock.io.csrio.get.isXRet 181 ctrlBlock.io.robio.csr.wfiEvent := intExuBlock.io.csrio.get.wfi_event 182 ctrlBlock.io.robio.lsq <> io.mem.robLsqIO 183 ctrlBlock.io.robio.lsTopdownInfo <> io.mem.lsTopdownInfo 184 ctrlBlock.io.robio.debug_ls <> io.mem.debugLS 185 ctrlBlock.io.fromDataPath.vtype := vconfig(7, 0).asTypeOf(new VType) 186 ctrlBlock.perfinfo := DontCare // TODO: Implement backend hpm 187 ctrlBlock.io.debugEnqLsq.canAccept := io.mem.lsqEnqIO.canAccept 188 ctrlBlock.io.debugEnqLsq.resp := io.mem.lsqEnqIO.resp 189 ctrlBlock.io.debugEnqLsq.req := memScheduler.io.memIO.get.lsqEnqIO.req 190 ctrlBlock.io.debugEnqLsq.needAlloc := memScheduler.io.memIO.get.lsqEnqIO.needAlloc 191 192 193 intScheduler.io.fromTop.hartId := io.fromTop.hartId 194 intScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 195 intScheduler.io.fromCtrlBlock.pcVec := ctrlBlock.io.toIssueBlock.pcVec 196 intScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 197 intScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.intUops 198 intScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 199 intScheduler.io.vfWriteBack := 0.U.asTypeOf(intScheduler.io.vfWriteBack) 200 intScheduler.io.fromDataPath.resp := dataPath.io.toIntIQ 201 intScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 202 intScheduler.io.fromDataPath.og0Cancel := og0CancelOH 203 intScheduler.io.fromDataPath.og1Cancel := og1CancelOH 204 intScheduler.io.ldCancel := io.mem.ldCancel 205 intScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 206 207 memScheduler.io.fromTop.hartId := io.fromTop.hartId 208 memScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 209 memScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 210 memScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.memUops 211 memScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 212 memScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 213 memScheduler.io.fromMem.get.scommit := io.mem.sqDeq 214 memScheduler.io.fromMem.get.lcommit := io.mem.lqDeq 215 memScheduler.io.fromMem.get.sqDeqPtr := io.mem.sqDeqPtr 216 memScheduler.io.fromMem.get.lqDeqPtr := io.mem.lqDeqPtr 217 memScheduler.io.fromMem.get.sqCancelCnt := io.mem.sqCancelCnt 218 memScheduler.io.fromMem.get.lqCancelCnt := io.mem.lqCancelCnt 219 memScheduler.io.fromMem.get.stIssuePtr := io.mem.stIssuePtr 220 memScheduler.io.fromMem.get.memWaitUpdateReq.robIdx.zip(io.mem.stIn).foreach { case (sink, source) => 221 sink.valid := source.valid 222 sink.bits := source.bits.robIdx 223 } 224 memScheduler.io.fromMem.get.memWaitUpdateReq.sqIdx := DontCare // TODO 225 memScheduler.io.fromDataPath.resp := dataPath.io.toMemIQ 226 memScheduler.io.fromMem.get.ldaFeedback := io.mem.ldaIqFeedback 227 memScheduler.io.fromMem.get.staFeedback := io.mem.staIqFeedback 228 memScheduler.io.fromMem.get.hyuFeedback := io.mem.hyuIqFeedback 229 memScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 230 memScheduler.io.fromDataPath.og0Cancel := og0CancelOH 231 memScheduler.io.fromDataPath.og1Cancel := og1CancelOH 232 memScheduler.io.ldCancel := io.mem.ldCancel 233 memScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 234 235 vfScheduler.io.fromTop.hartId := io.fromTop.hartId 236 vfScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 237 vfScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 238 vfScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.vfUops 239 vfScheduler.io.intWriteBack := 0.U.asTypeOf(vfScheduler.io.intWriteBack) 240 vfScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 241 vfScheduler.io.fromDataPath.resp := dataPath.io.toVfIQ 242 vfScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 243 vfScheduler.io.fromDataPath.og0Cancel := og0CancelOH 244 vfScheduler.io.fromDataPath.og1Cancel := og1CancelOH 245 vfScheduler.io.ldCancel := io.mem.ldCancel 246 vfScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 247 248 cancelNetwork.io.in.int <> intScheduler.io.toDataPath 249 cancelNetwork.io.in.vf <> vfScheduler.io.toDataPath 250 cancelNetwork.io.in.mem <> memScheduler.io.toDataPath 251 cancelNetwork.io.in.og0CancelOH := og0CancelOHFromDataPath | og0CancelOHFromFinalIssue 252 cancelNetwork.io.in.og1CancelOH := og1CancelOH 253 intScheduler.io.fromCancelNetwork <> cancelNetwork.io.out.int 254 vfScheduler.io.fromCancelNetwork <> cancelNetwork.io.out.vf 255 memScheduler.io.fromCancelNetwork <> cancelNetwork.io.out.mem 256 257 dataPath.io.hartId := io.fromTop.hartId 258 dataPath.io.flush := ctrlBlock.io.toDataPath.flush 259 dataPath.io.vconfigReadPort.addr := ctrlBlock.io.toDataPath.vtypeAddr 260 dataPath.io.vldReadPort.addr := wbDataPath.io.oldVdAddrToDataPath 261 262 dataPath.io.fromIntIQ <> intScheduler.io.toDataPathAfterDelay 263 dataPath.io.fromVfIQ <> vfScheduler.io.toDataPathAfterDelay 264 dataPath.io.fromMemIQ <> memScheduler.io.toDataPathAfterDelay 265 266 dataPath.io.ldCancel := io.mem.ldCancel 267 268 println(s"[Backend] wbDataPath.io.toIntPreg: ${wbDataPath.io.toIntPreg.size}, dataPath.io.fromIntWb: ${dataPath.io.fromIntWb.size}") 269 println(s"[Backend] wbDataPath.io.toVfPreg: ${wbDataPath.io.toVfPreg.size}, dataPath.io.fromFpWb: ${dataPath.io.fromVfWb.size}") 270 dataPath.io.fromIntWb := wbDataPath.io.toIntPreg 271 dataPath.io.fromVfWb := wbDataPath.io.toVfPreg 272 dataPath.io.debugIntRat .foreach(_ := ctrlBlock.io.debug_int_rat.get) 273 dataPath.io.debugFpRat .foreach(_ := ctrlBlock.io.debug_fp_rat.get) 274 dataPath.io.debugVecRat .foreach(_ := ctrlBlock.io.debug_vec_rat.get) 275 dataPath.io.debugVconfigRat.foreach(_ := ctrlBlock.io.debug_vconfig_rat.get) 276 277 bypassNetwork.io.fromDataPath.int <> dataPath.io.toIntExu 278 bypassNetwork.io.fromDataPath.vf <> dataPath.io.toFpExu 279 bypassNetwork.io.fromDataPath.mem <> dataPath.io.toMemExu 280 bypassNetwork.io.fromExus.connectExuOutput(_.int)(intExuBlock.io.out) 281 bypassNetwork.io.fromExus.connectExuOutput(_.vf)(vfExuBlock.io.out) 282 283 require(bypassNetwork.io.fromExus.mem.flatten.size == io.mem.writeBack.size, 284 s"bypassNetwork.io.fromExus.mem.flatten.size(${bypassNetwork.io.fromExus.mem.flatten.size}: ${bypassNetwork.io.fromExus.mem.map(_.size)}, " + 285 s"io.mem.writeback(${io.mem.writeBack.size})" 286 ) 287 bypassNetwork.io.fromExus.mem.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 288 sink.valid := source.valid 289 sink.bits.pdest := source.bits.uop.pdest 290 sink.bits.data := source.bits.data 291 } 292 293 294 intExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 295 for (i <- 0 until intExuBlock.io.in.length) { 296 for (j <- 0 until intExuBlock.io.in(i).length) { 297 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.int(i)(j).bits.loadDependency, io.mem.ldCancel) 298 NewPipelineConnect( 299 bypassNetwork.io.toExus.int(i)(j), intExuBlock.io.in(i)(j), intExuBlock.io.in(i)(j).fire, 300 Mux( 301 bypassNetwork.io.toExus.int(i)(j).fire, 302 bypassNetwork.io.toExus.int(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 303 intExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 304 ) 305 ) 306 } 307 } 308 309 pcTargetMem.io.fromFrontendFtq := io.frontend.fromFtq 310 pcTargetMem.io.fromDataPathFtq := bypassNetwork.io.toExus.int.flatten.filter(_.bits.params.needTarget).map(_.bits.ftqIdx.get).toSeq 311 intExuBlock.io.in.flatten.filter(_.bits.params.needTarget).map(_.bits.predictInfo.get.target).zipWithIndex.foreach { 312 case (sink, i) => 313 sink := pcTargetMem.io.toExus(i) 314 } 315 316 private val csrio = intExuBlock.io.csrio.get 317 csrio.hartId := io.fromTop.hartId 318 csrio.fpu.fflags := ctrlBlock.io.robio.csr.fflags 319 csrio.fpu.isIllegal := false.B // Todo: remove it 320 csrio.fpu.dirty_fs := ctrlBlock.io.robio.csr.dirty_fs 321 csrio.vpu <> 0.U.asTypeOf(csrio.vpu) // Todo 322 323 val debugVconfig = dataPath.io.debugVconfig.get.asTypeOf(new VConfig) 324 val debugVtype = VType.toVtypeStruct(debugVconfig.vtype).asUInt 325 val debugVl = debugVconfig.vl 326 csrio.vpu.set_vxsat := ctrlBlock.io.robio.csr.vxsat 327 csrio.vpu.set_vstart.valid := ctrlBlock.io.robio.csr.vstart.valid 328 csrio.vpu.set_vstart.bits := ctrlBlock.io.robio.csr.vstart.bits 329 csrio.vpu.set_vtype.valid := ctrlBlock.io.robio.csr.vcsrFlag 330 //Todo here need change design 331 csrio.vpu.set_vtype.bits := ZeroExt(debugVtype, XLEN) 332 csrio.vpu.set_vl.valid := ctrlBlock.io.robio.csr.vcsrFlag 333 csrio.vpu.set_vl.bits := ZeroExt(debugVl, XLEN) 334 csrio.exception := ctrlBlock.io.robio.exception 335 csrio.memExceptionVAddr := io.mem.exceptionVAddr 336 csrio.externalInterrupt := io.fromTop.externalInterrupt 337 csrio.distributedUpdate(0) := io.mem.csrDistributedUpdate 338 csrio.distributedUpdate(1) := io.frontendCsrDistributedUpdate 339 csrio.perf <> io.perf 340 csrio.perf.retiredInstr <> ctrlBlock.io.robio.csr.perfinfo.retiredInstr 341 csrio.perf.ctrlInfo <> ctrlBlock.io.perfInfo.ctrlInfo 342 csrio.perf.perfEventsCtrl <> ctrlBlock.getPerf 343 private val fenceio = intExuBlock.io.fenceio.get 344 io.fenceio <> fenceio 345 fenceio.disableSfence := csrio.disableSfence 346 347 vfExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 348 for (i <- 0 until vfExuBlock.io.in.size) { 349 for (j <- 0 until vfExuBlock.io.in(i).size) { 350 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.vf(i)(j).bits.loadDependency, io.mem.ldCancel) 351 NewPipelineConnect( 352 bypassNetwork.io.toExus.vf(i)(j), vfExuBlock.io.in(i)(j), vfExuBlock.io.in(i)(j).fire, 353 Mux( 354 bypassNetwork.io.toExus.vf(i)(j).fire, 355 bypassNetwork.io.toExus.vf(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 356 vfExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 357 ) 358 ) 359 360 vfExuBlock.io.in(i)(j).bits.vpu.foreach(_.vstart := csrio.vpu.vstart) 361 } 362 } 363 364 intExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 365 vfExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 366 367 wbDataPath.io.flush := ctrlBlock.io.redirect 368 wbDataPath.io.oldVdDataFromDataPath := dataPath.io.vldReadPort.data 369 wbDataPath.io.fromTop.hartId := io.fromTop.hartId 370 wbDataPath.io.fromIntExu <> intExuBlock.io.out 371 wbDataPath.io.fromVfExu <> vfExuBlock.io.out 372 wbDataPath.io.fromMemExu.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 373 sink.valid := source.valid 374 source.ready := sink.ready 375 sink.bits.data := source.bits.data 376 sink.bits.pdest := source.bits.uop.pdest 377 sink.bits.robIdx := source.bits.uop.robIdx 378 sink.bits.intWen.foreach(_ := source.bits.uop.rfWen) 379 sink.bits.fpWen.foreach(_ := source.bits.uop.fpWen) 380 sink.bits.vecWen.foreach(_ := source.bits.uop.vecWen) 381 sink.bits.exceptionVec.foreach(_ := source.bits.uop.exceptionVec) 382 sink.bits.flushPipe.foreach(_ := source.bits.uop.flushPipe) 383 sink.bits.replay.foreach(_ := source.bits.uop.replayInst) 384 sink.bits.debug := source.bits.debug 385 sink.bits.debugInfo := source.bits.uop.debugInfo 386 sink.bits.lqIdx.foreach(_ := source.bits.uop.lqIdx) 387 sink.bits.sqIdx.foreach(_ := source.bits.uop.sqIdx) 388 sink.bits.predecodeInfo.foreach(_ := source.bits.uop.preDecodeInfo) 389 sink.bits.vls.foreach(x => { 390 x.vdIdx := source.bits.vdIdx.get 391 x.vdIdxInField := source.bits.vdIdxInField.get 392 x.vpu := source.bits.uop.vpu 393 x.oldVdPsrc := source.bits.uop.psrc(2) 394 x.isIndexed := VlduType.isIndexed(source.bits.uop.fuOpType) 395 }) 396 sink.bits.trigger.foreach(_ := source.bits.uop.trigger) 397 } 398 399 // to mem 400 private val memIssueParams = params.memSchdParams.get.issueBlockParams 401 private val memExuBlocksHasLDU = memIssueParams.map(_.exuBlockParams.map(x => x.hasLoadFu || x.hasHyldaFu)) 402 println(s"[Backend] memExuBlocksHasLDU: $memExuBlocksHasLDU") 403 404 private val toMem = Wire(bypassNetwork.io.toExus.mem.cloneType) 405 for (i <- toMem.indices) { 406 for (j <- toMem(i).indices) { 407 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.mem(i)(j).bits.loadDependency, io.mem.ldCancel) 408 val issueTimeout = 409 if (memExuBlocksHasLDU(i)(j)) 410 Counter(0 until 16, toMem(i)(j).valid && !toMem(i)(j).fire, bypassNetwork.io.toExus.mem(i)(j).fire)._2 411 else 412 false.B 413 414 if (memScheduler.io.loadFinalIssueResp(i).nonEmpty && memExuBlocksHasLDU(i)(j)) { 415 memScheduler.io.loadFinalIssueResp(i)(j).valid := issueTimeout 416 memScheduler.io.loadFinalIssueResp(i)(j).bits.dataInvalidSqIdx := DontCare 417 memScheduler.io.loadFinalIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType 418 memScheduler.io.loadFinalIssueResp(i)(j).bits.respType := RSFeedbackType.fuBusy 419 memScheduler.io.loadFinalIssueResp(i)(j).bits.rfWen := toMem(i)(j).bits.rfWen.getOrElse(false.B) 420 memScheduler.io.loadFinalIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx 421 memScheduler.io.loadFinalIssueResp(i)(j).bits.uopIdx := toMem(i)(j).bits.vpu.getOrElse(0.U.asTypeOf(new VPUCtrlSignals)).vuopIdx 422 } 423 424 NewPipelineConnect( 425 bypassNetwork.io.toExus.mem(i)(j), toMem(i)(j), toMem(i)(j).fire, 426 Mux( 427 bypassNetwork.io.toExus.mem(i)(j).fire, 428 bypassNetwork.io.toExus.mem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 429 toMem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || issueTimeout 430 ) 431 ) 432 433 if (memScheduler.io.memAddrIssueResp(i).nonEmpty && memExuBlocksHasLDU(i)(j)) { 434 memScheduler.io.memAddrIssueResp(i)(j).valid := toMem(i)(j).fire && FuType.isLoad(toMem(i)(j).bits.fuType) 435 memScheduler.io.memAddrIssueResp(i)(j).bits.dataInvalidSqIdx := DontCare 436 memScheduler.io.memAddrIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType 437 memScheduler.io.memAddrIssueResp(i)(j).bits.respType := RSFeedbackType.fuIdle 438 memScheduler.io.memAddrIssueResp(i)(j).bits.rfWen := toMem(i)(j).bits.rfWen.getOrElse(false.B) 439 memScheduler.io.memAddrIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx 440 memScheduler.io.memAddrIssueResp(i)(j).bits.uopIdx := 0.U 441 } 442 } 443 } 444 445 io.mem.redirect := ctrlBlock.io.redirect 446 private val memIssueUops = 447 Seq(io.mem.issueLda(0)) ++ Seq(io.mem.issueSta(0)) ++ 448 io.mem.issueHylda ++ io.mem.issueHysta ++ 449 Seq(io.mem.issueLda(1)) ++ 450 io.mem.issueVldu ++ 451 io.mem.issueStd 452 io.mem.issueUops.zip(toMem.flatten).foreach { case (sink, source) => 453 sink.valid := source.valid 454 source.ready := sink.ready 455 sink.bits.iqIdx := source.bits.iqIdx 456 sink.bits.isFirstIssue := source.bits.isFirstIssue 457 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 458 sink.bits.src := 0.U.asTypeOf(sink.bits.src) 459 sink.bits.src.zip(source.bits.src).foreach { case (l, r) => l := r} 460 sink.bits.deqPortIdx := source.bits.deqLdExuIdx.getOrElse(0.U) 461 sink.bits.uop.fuType := source.bits.fuType 462 sink.bits.uop.fuOpType := source.bits.fuOpType 463 sink.bits.uop.imm := source.bits.imm 464 sink.bits.uop.robIdx := source.bits.robIdx 465 sink.bits.uop.pdest := source.bits.pdest 466 sink.bits.uop.rfWen := source.bits.rfWen.getOrElse(false.B) 467 sink.bits.uop.fpWen := source.bits.fpWen.getOrElse(false.B) 468 sink.bits.uop.vecWen := source.bits.vecWen.getOrElse(false.B) 469 sink.bits.uop.flushPipe := source.bits.flushPipe.getOrElse(false.B) 470 sink.bits.uop.pc := source.bits.pc.getOrElse(0.U) 471 sink.bits.uop.lqIdx := source.bits.lqIdx.getOrElse(0.U.asTypeOf(new LqPtr)) 472 sink.bits.uop.sqIdx := source.bits.sqIdx.getOrElse(0.U.asTypeOf(new SqPtr)) 473 sink.bits.uop.ftqPtr := source.bits.ftqIdx.getOrElse(0.U.asTypeOf(new FtqPtr)) 474 sink.bits.uop.ftqOffset := source.bits.ftqOffset.getOrElse(0.U) 475 sink.bits.uop.debugInfo := source.bits.perfDebugInfo 476 sink.bits.uop.vpu := source.bits.vpu.getOrElse(0.U.asTypeOf(new VPUCtrlSignals)) 477 sink.bits.uop.preDecodeInfo := source.bits.preDecode.getOrElse(0.U.asTypeOf(new PreDecodeInfo)) 478 } 479 io.mem.loadFastMatch := memScheduler.io.toMem.get.loadFastMatch.map(_.fastMatch) 480 io.mem.loadFastImm := memScheduler.io.toMem.get.loadFastMatch.map(_.fastImm) 481 io.mem.tlbCsr := csrio.tlb 482 io.mem.csrCtrl := csrio.customCtrl 483 io.mem.sfence := fenceio.sfence 484 io.mem.isStoreException := CommitType.lsInstIsStore(ctrlBlock.io.robio.exception.bits.commitType) 485 io.mem.isVlsException := ctrlBlock.io.robio.exception.bits.vls 486 require(io.mem.loadPcRead.size == params.LduCnt) 487 io.mem.loadPcRead.zipWithIndex.foreach { case (loadPcRead, i) => 488 loadPcRead := ctrlBlock.io.memLdPcRead(i).data 489 ctrlBlock.io.memLdPcRead(i).ptr := io.mem.issueLda(i).bits.uop.ftqPtr 490 ctrlBlock.io.memLdPcRead(i).offset := io.mem.issueLda(i).bits.uop.ftqOffset 491 require(toMem.head(i).bits.ftqIdx.isDefined && toMem.head(i).bits.ftqOffset.isDefined) 492 } 493 494 io.mem.storePcRead.zipWithIndex.foreach { case (storePcRead, i) => 495 storePcRead := ctrlBlock.io.memStPcRead(i).data 496 ctrlBlock.io.memStPcRead(i).ptr := io.mem.issueSta(i).bits.uop.ftqPtr 497 ctrlBlock.io.memStPcRead(i).offset := io.mem.issueSta(i).bits.uop.ftqOffset 498 require(toMem(1)(i).bits.ftqIdx.isDefined && toMem(1)(i).bits.ftqOffset.isDefined) 499 } 500 501 io.mem.hyuPcRead.zipWithIndex.foreach( { case (hyuPcRead, i) => 502 hyuPcRead := ctrlBlock.io.memHyPcRead(i).data 503 ctrlBlock.io.memHyPcRead(i).ptr := io.mem.issueHylda(i).bits.uop.ftqPtr 504 ctrlBlock.io.memHyPcRead(i).offset := io.mem.issueHylda(i).bits.uop.ftqOffset 505 require(toMem(2)(i).bits.ftqIdx.isDefined && toMem(2)(i).bits.ftqOffset.isDefined) 506 }) 507 508 ctrlBlock.io.robio.robHeadLsIssue := io.mem.issueUops.map(deq => deq.fire && deq.bits.uop.robIdx === ctrlBlock.io.robio.robDeqPtr).reduce(_ || _) 509 510 // mem io 511 io.mem.lsqEnqIO <> memScheduler.io.memIO.get.lsqEnqIO 512 io.mem.robLsqIO <> ctrlBlock.io.robio.lsq 513 514 private val intFinalIssueBlock = intExuBlock.io.in.flatten.map(_ => false.B) 515 private val vfFinalIssueBlock = vfExuBlock.io.in.flatten.map(_ => false.B) 516 private val memFinalIssueBlock = io.mem.issueUops zip memExuBlocksHasLDU.flatten map { 517 case (out, isLdu) => 518 if (isLdu) RegNext(out.valid && !out.ready, false.B) 519 else false.B 520 } 521 println(s"[backend]: width of [int|vf|mem]FinalIssueBlock: ${intFinalIssueBlock.size}|${vfFinalIssueBlock.size}|${memFinalIssueBlock.size}") 522 og0CancelOHFromFinalIssue := VecInit((intFinalIssueBlock ++ vfFinalIssueBlock ++ memFinalIssueBlock).toSeq).asUInt 523 524 io.frontendSfence := fenceio.sfence 525 io.frontendTlbCsr := csrio.tlb 526 io.frontendCsrCtrl := csrio.customCtrl 527 528 io.tlb <> csrio.tlb 529 530 io.csrCustomCtrl := csrio.customCtrl 531 532 io.toTop.cpuHalted := false.B // TODO: implement cpu halt 533 534 io.debugTopDown.fromRob := ctrlBlock.io.debugTopDown.fromRob 535 ctrlBlock.io.debugTopDown.fromCore := io.debugTopDown.fromCore 536 537 io.debugRolling := ctrlBlock.io.debugRolling 538 539 dontTouch(memScheduler.io) 540 dontTouch(dataPath.io.toMemExu) 541 dontTouch(wbDataPath.io.fromMemExu) 542} 543 544class BackendMemIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 545 // Since fast load replay always use load unit 0, Backend flips two load port to avoid conflicts 546 val flippedLda = true 547 // params alias 548 private val LoadQueueSize = VirtualLoadQueueSize 549 // In/Out // Todo: split it into one-direction bundle 550 val lsqEnqIO = Flipped(new LsqEnqIO) 551 val robLsqIO = new RobLsqIO 552 val ldaIqFeedback = Vec(params.LduCnt, Flipped(new MemRSFeedbackIO)) 553 val staIqFeedback = Vec(params.StaCnt, Flipped(new MemRSFeedbackIO)) 554 val hyuIqFeedback = Vec(params.HyuCnt, Flipped(new MemRSFeedbackIO)) 555 val ldCancel = Vec(params.LduCnt + params.HyuCnt, Flipped(new LoadCancelIO)) 556 val loadPcRead = Vec(params.LduCnt, Output(UInt(VAddrBits.W))) 557 val storePcRead = Vec(params.StaCnt, Output(UInt(VAddrBits.W))) 558 val hyuPcRead = Vec(params.HyuCnt, Output(UInt(VAddrBits.W))) 559 // Input 560 val writebackLda = Vec(params.LduCnt, Flipped(DecoupledIO(new MemExuOutput))) 561 val writebackSta = Vec(params.StaCnt, Flipped(DecoupledIO(new MemExuOutput))) 562 val writebackStd = Vec(params.StdCnt, Flipped(DecoupledIO(new MemExuOutput))) 563 val writebackHyuLda = Vec(params.HyuCnt, Flipped(DecoupledIO(new MemExuOutput))) 564 val writebackHyuSta = Vec(params.HyuCnt, Flipped(DecoupledIO(new MemExuOutput))) 565 val writebackVldu = Vec(params.VlduCnt, Flipped(DecoupledIO(new MemExuOutput(true)))) 566 567 val s3_delayed_load_error = Input(Vec(LoadPipelineWidth, Bool())) 568 val stIn = Input(Vec(params.StaCnt, ValidIO(new DynInst()))) 569 val memoryViolation = Flipped(ValidIO(new Redirect)) 570 val exceptionVAddr = Input(UInt(VAddrBits.W)) 571 val sqDeq = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) 572 val lqDeq = Input(UInt(log2Up(CommitWidth + 1).W)) 573 val sqDeqPtr = Input(new SqPtr) 574 val lqDeqPtr = Input(new LqPtr) 575 576 val lqCancelCnt = Input(UInt(log2Up(VirtualLoadQueueSize + 1).W)) 577 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 578 579 val lqCanAccept = Input(Bool()) 580 val sqCanAccept = Input(Bool()) 581 582 val otherFastWakeup = Flipped(Vec(params.LduCnt + params.HyuCnt, ValidIO(new DynInst))) 583 val stIssuePtr = Input(new SqPtr()) 584 585 val csrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 586 587 val debugLS = Flipped(Output(new DebugLSIO)) 588 589 val lsTopdownInfo = Vec(params.LduCnt + params.HyuCnt, Flipped(Output(new LsTopdownInfo))) 590 // Output 591 val redirect = ValidIO(new Redirect) // rob flush MemBlock 592 val issueLda = MixedVec(Seq.fill(params.LduCnt)(DecoupledIO(new MemExuInput()))) 593 val issueSta = MixedVec(Seq.fill(params.StaCnt)(DecoupledIO(new MemExuInput()))) 594 val issueStd = MixedVec(Seq.fill(params.StdCnt)(DecoupledIO(new MemExuInput()))) 595 val issueHylda = MixedVec(Seq.fill(params.HyuCnt)(DecoupledIO(new MemExuInput()))) 596 val issueHysta = MixedVec(Seq.fill(params.HyuCnt)(DecoupledIO(new MemExuInput()))) 597 val issueVldu = MixedVec(Seq.fill(params.VlduCnt)(DecoupledIO(new MemExuInput(true)))) 598 599 val loadFastMatch = Vec(params.LduCnt, Output(UInt(params.LduCnt.W))) 600 val loadFastImm = Vec(params.LduCnt, Output(UInt(12.W))) // Imm_I 601 602 val tlbCsr = Output(new TlbCsrBundle) 603 val csrCtrl = Output(new CustomCSRCtrlIO) 604 val sfence = Output(new SfenceBundle) 605 val isStoreException = Output(Bool()) 606 val isVlsException = Output(Bool()) 607 608 // ATTENTION: The issue ports' sequence order should be the same as IQs' deq config 609 private [backend] def issueUops: Seq[DecoupledIO[MemExuInput]] = { 610 Seq(issueLda(0)) ++ Seq(issueSta(0)) ++ 611 issueHylda ++ issueHysta ++ 612 Seq(issueLda(1)) ++ 613 issueVldu ++ 614 issueStd 615 } 616 617 // ATTENTION: The writeback ports' sequence order should be the same as IQs' deq config 618 private [backend] def writeBack: Seq[DecoupledIO[MemExuOutput]] = { 619 Seq(writebackLda(0)) ++ Seq(writebackSta(0)) ++ 620 writebackHyuLda ++ writebackHyuSta ++ 621 Seq(writebackLda(1)) ++ 622 writebackVldu ++ 623 writebackStd 624 } 625} 626 627class BackendIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 628 val fromTop = new Bundle { 629 val hartId = Input(UInt(8.W)) 630 val externalInterrupt = new ExternalInterruptIO 631 } 632 633 val toTop = new Bundle { 634 val cpuHalted = Output(Bool()) 635 } 636 637 val fenceio = new FenceIO 638 // Todo: merge these bundles into BackendFrontendIO 639 val frontend = Flipped(new FrontendToCtrlIO) 640 val frontendSfence = Output(new SfenceBundle) 641 val frontendCsrCtrl = Output(new CustomCSRCtrlIO) 642 val frontendTlbCsr = Output(new TlbCsrBundle) 643 // distributed csr write 644 val frontendCsrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 645 646 val mem = new BackendMemIO 647 648 val perf = Input(new PerfCounterIO) 649 650 val tlb = Output(new TlbCsrBundle) 651 652 val csrCustomCtrl = Output(new CustomCSRCtrlIO) 653 654 val debugTopDown = new Bundle { 655 val fromRob = new RobCoreTopDownIO 656 val fromCore = new CoreDispatchTopDownIO 657 } 658 val debugRolling = new RobDebugRollingIO 659} 660