1package xiangshan.backend 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import utility.ZeroExt 8import xiangshan._ 9import xiangshan.backend.Bundles.{DynInst, IssueQueueIQWakeUpBundle, MemExuInput, MemExuOutput, LoadShouldCancel} 10import xiangshan.backend.ctrlblock.{DebugLSIO, LsTopdownInfo} 11import xiangshan.backend.datapath.DataConfig.{IntData, VecData} 12import xiangshan.backend.datapath.RdConfig.{IntRD, VfRD} 13import xiangshan.backend.datapath.WbConfig._ 14import xiangshan.backend.datapath._ 15import xiangshan.backend.exu.ExuBlock 16import xiangshan.backend.fu.vector.Bundles.{VConfig, VType} 17import xiangshan.backend.fu.{FenceIO, FenceToSbuffer, FuConfig, PerfCounterIO} 18import xiangshan.backend.issue.{CancelNetwork, Scheduler} 19import xiangshan.backend.rob.RobLsqIO 20import xiangshan.frontend.{FtqPtr, FtqRead} 21import xiangshan.mem.{LqPtr, LsqEnqIO, SqPtr} 22 23class Backend(val params: BackendParams)(implicit p: Parameters) extends LazyModule 24 with HasXSParameter { 25 26 /* Only update the idx in mem-scheduler here 27 * Idx in other schedulers can be updated the same way if needed 28 * 29 * Also note that we filter out the 'stData issue-queues' when counting 30 */ 31 for ((ibp, idx) <- params.memSchdParams.get.issueBlockParams.filter(iq => iq.StdCnt == 0).zipWithIndex) { 32 ibp.updateIdx(idx) 33 } 34 35 println(params.iqWakeUpParams) 36 37 for ((schdCfg, i) <- params.allSchdParams.zipWithIndex) { 38 schdCfg.bindBackendParam(params) 39 } 40 41 for ((iqCfg, i) <- params.allIssueParams.zipWithIndex) { 42 iqCfg.bindBackendParam(params) 43 } 44 45 for ((exuCfg, i) <- params.allExuParams.zipWithIndex) { 46 exuCfg.updateIQWakeUpConfigs(params.iqWakeUpParams) 47 exuCfg.updateExuIdx(i) 48 exuCfg.bindBackendParam(params) 49 } 50 51 println("[Backend] ExuConfigs:") 52 for (exuCfg <- params.allExuParams) { 53 val fuConfigs = exuCfg.fuConfigs 54 val wbPortConfigs = exuCfg.wbPortConfigs 55 val immType = exuCfg.immType 56 57 println("[Backend] " + 58 s"${exuCfg.name}: " + 59 s"${fuConfigs.map(_.name).mkString("fu(s): {", ",", "}")}, " + 60 s"${wbPortConfigs.mkString("wb: {", ",", "}")}, " + 61 s"${immType.map(SelImm.mkString(_)).mkString("imm: {", ",", "}")}, " + 62 s"latMax(${exuCfg.latencyValMax}), ${exuCfg.fuLatancySet.mkString("lat: {", ",", "}")}, " 63 ) 64 require( 65 wbPortConfigs.collectFirst { case x: IntWB => x }.nonEmpty == 66 fuConfigs.map(_.writeIntRf).reduce(_ || _), 67 "int wb port has no priority" 68 ) 69 require( 70 wbPortConfigs.collectFirst { case x: VfWB => x }.nonEmpty == 71 fuConfigs.map(x => x.writeFpRf || x.writeVecRf).reduce(_ || _), 72 "vec wb port has no priority" 73 ) 74 } 75 76 println(s"[Backend] all fu configs") 77 for (cfg <- FuConfig.allConfigs) { 78 println(s"[Backend] $cfg") 79 } 80 81 println(s"[Backend] Int RdConfigs: ExuName(Priority)") 82 for ((port, seq) <- params.getRdPortParams(IntData())) { 83 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 84 } 85 86 println(s"[Backend] Int WbConfigs: ExuName(Priority)") 87 for ((port, seq) <- params.getWbPortParams(IntData())) { 88 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 89 } 90 91 println(s"[Backend] Vf RdConfigs: ExuName(Priority)") 92 for ((port, seq) <- params.getRdPortParams(VecData())) { 93 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 94 } 95 96 println(s"[Backend] Vf WbConfigs: ExuName(Priority)") 97 for ((port, seq) <- params.getWbPortParams(VecData())) { 98 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 99 } 100 101 val ctrlBlock = LazyModule(new CtrlBlock(params)) 102 val pcTargetMem = LazyModule(new PcTargetMem(params)) 103 val intScheduler = params.intSchdParams.map(x => LazyModule(new Scheduler(x))) 104 val vfScheduler = params.vfSchdParams.map(x => LazyModule(new Scheduler(x))) 105 val memScheduler = params.memSchdParams.map(x => LazyModule(new Scheduler(x))) 106 val cancelNetwork = LazyModule(new CancelNetwork(params)) 107 val dataPath = LazyModule(new DataPath(params)) 108 val intExuBlock = params.intSchdParams.map(x => LazyModule(new ExuBlock(x))) 109 val vfExuBlock = params.vfSchdParams.map(x => LazyModule(new ExuBlock(x))) 110 val wbFuBusyTable = LazyModule(new WbFuBusyTable(params)) 111 112 lazy val module = new BackendImp(this) 113} 114 115class BackendImp(override val wrapper: Backend)(implicit p: Parameters) extends LazyModuleImp(wrapper) 116 with HasXSParameter { 117 implicit private val params = wrapper.params 118 119 val io = IO(new BackendIO()(p, wrapper.params)) 120 121 private val ctrlBlock = wrapper.ctrlBlock.module 122 private val pcTargetMem = wrapper.pcTargetMem.module 123 private val intScheduler = wrapper.intScheduler.get.module 124 private val vfScheduler = wrapper.vfScheduler.get.module 125 private val memScheduler = wrapper.memScheduler.get.module 126 private val cancelNetwork = wrapper.cancelNetwork.module 127 private val dataPath = wrapper.dataPath.module 128 private val intExuBlock = wrapper.intExuBlock.get.module 129 private val vfExuBlock = wrapper.vfExuBlock.get.module 130 private val bypassNetwork = Module(new BypassNetwork) 131 private val wbDataPath = Module(new WbDataPath(params)) 132 private val wbFuBusyTable = wrapper.wbFuBusyTable.module 133 134 private val iqWakeUpMappedBundle: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = ( 135 intScheduler.io.toSchedulers.wakeupVec ++ 136 vfScheduler.io.toSchedulers.wakeupVec ++ 137 memScheduler.io.toSchedulers.wakeupVec 138 ).map(x => (x.bits.exuIdx, x)).toMap 139 140 println(s"[Backend] iq wake up keys: ${iqWakeUpMappedBundle.keys}") 141 142 wbFuBusyTable.io.in.intSchdBusyTable := intScheduler.io.wbFuBusyTable 143 wbFuBusyTable.io.in.vfSchdBusyTable := vfScheduler.io.wbFuBusyTable 144 wbFuBusyTable.io.in.memSchdBusyTable := memScheduler.io.wbFuBusyTable 145 intScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.intRespRead 146 vfScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.vfRespRead 147 memScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.memRespRead 148 dataPath.io.wbConfictRead := wbFuBusyTable.io.out.wbConflictRead 149 150 wbDataPath.io.fromIntExu.flatten.filter(x => x.bits.params.writeIntRf) 151 152 private val vconfig = dataPath.io.vconfigReadPort.data 153 private val og1CancelVec: Vec[Bool] = dataPath.io.og1CancelVec 154 private val og0CancelVecFromDataPath: Vec[Bool] = dataPath.io.og0CancelVec 155 private val og0CancelVecFromCancelNet: Vec[Bool] = cancelNetwork.io.out.og0CancelVec 156 private val og0CancelVecFromFinalIssue: Vec[Bool] = Wire(chiselTypeOf(dataPath.io.og0CancelVec)) 157 private val og0CancelVec: Seq[Bool] = og0CancelVecFromDataPath.zip(og0CancelVecFromCancelNet).zip(og0CancelVecFromFinalIssue).map(x => x._1._1 | x._1._2 | x._2) 158 private val cancelToBusyTable = dataPath.io.cancelToBusyTable 159 160 ctrlBlock.io.fromTop.hartId := io.fromTop.hartId 161 ctrlBlock.io.frontend <> io.frontend 162 ctrlBlock.io.fromWB.wbData <> wbDataPath.io.toCtrlBlock.writeback 163 ctrlBlock.io.fromMem.stIn <> io.mem.stIn 164 ctrlBlock.io.fromMem.violation <> io.mem.memoryViolation 165 ctrlBlock.io.lqCanAccept := io.mem.lqCanAccept 166 ctrlBlock.io.sqCanAccept := io.mem.sqCanAccept 167 ctrlBlock.io.csrCtrl <> intExuBlock.io.csrio.get.customCtrl 168 ctrlBlock.io.robio.csr.intrBitSet := intExuBlock.io.csrio.get.interrupt 169 ctrlBlock.io.robio.csr.trapTarget := intExuBlock.io.csrio.get.trapTarget 170 ctrlBlock.io.robio.csr.isXRet := intExuBlock.io.csrio.get.isXRet 171 ctrlBlock.io.robio.csr.wfiEvent := intExuBlock.io.csrio.get.wfi_event 172 ctrlBlock.io.robio.lsq <> io.mem.robLsqIO 173 ctrlBlock.io.robio.lsTopdownInfo <> io.mem.lsTopdownInfo 174 ctrlBlock.io.robio.debug_ls <> io.mem.debugLS 175 ctrlBlock.io.fromDataPath.vtype := vconfig(7, 0).asTypeOf(new VType) 176 177 intScheduler.io.fromTop.hartId := io.fromTop.hartId 178 intScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 179 intScheduler.io.fromCtrlBlock.pcVec := ctrlBlock.io.toIssueBlock.pcVec 180 intScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 181 intScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.intUops 182 intScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 183 intScheduler.io.vfWriteBack := 0.U.asTypeOf(intScheduler.io.vfWriteBack) 184 intScheduler.io.fromDataPath.resp := dataPath.io.toIntIQ 185 intScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 186 intScheduler.io.fromDataPath.og0Cancel := og0CancelVec 187 intScheduler.io.fromDataPath.og1Cancel := og1CancelVec 188 intScheduler.io.ldCancel := io.mem.ldCancel 189 intScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 190 191 memScheduler.io.fromTop.hartId := io.fromTop.hartId 192 memScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 193 memScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 194 memScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.memUops 195 memScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 196 memScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 197 memScheduler.io.fromMem.get.scommit := io.mem.sqDeq 198 memScheduler.io.fromMem.get.lcommit := io.mem.lqDeq 199 memScheduler.io.fromMem.get.sqCancelCnt := io.mem.sqCancelCnt 200 memScheduler.io.fromMem.get.lqCancelCnt := io.mem.lqCancelCnt 201 memScheduler.io.fromMem.get.stIssuePtr := io.mem.stIssuePtr 202 memScheduler.io.fromMem.get.memWaitUpdateReq.staIssue.zip(io.mem.stIn).foreach { case (sink, source) => 203 sink.valid := source.valid 204 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 205 sink.bits.uop.robIdx := source.bits.robIdx 206 } 207 memScheduler.io.fromDataPath.resp := dataPath.io.toMemIQ 208 memScheduler.io.fromMem.get.ldaFeedback := io.mem.ldaIqFeedback 209 memScheduler.io.fromMem.get.staFeedback := io.mem.staIqFeedback 210 memScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 211 memScheduler.io.fromDataPath.og0Cancel := og0CancelVec 212 memScheduler.io.fromDataPath.og1Cancel := og1CancelVec 213 memScheduler.io.ldCancel := io.mem.ldCancel 214 memScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 215 216 vfScheduler.io.fromTop.hartId := io.fromTop.hartId 217 vfScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 218 vfScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 219 vfScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.vfUops 220 vfScheduler.io.intWriteBack := 0.U.asTypeOf(vfScheduler.io.intWriteBack) 221 vfScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 222 vfScheduler.io.fromDataPath.resp := dataPath.io.toVfIQ 223 vfScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 224 vfScheduler.io.fromDataPath.og0Cancel := og0CancelVec 225 vfScheduler.io.fromDataPath.og1Cancel := og1CancelVec 226 vfScheduler.io.ldCancel := io.mem.ldCancel 227 vfScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 228 229 cancelNetwork.io.in.int <> intScheduler.io.toDataPath 230 cancelNetwork.io.in.vf <> vfScheduler.io.toDataPath 231 cancelNetwork.io.in.mem <> memScheduler.io.toDataPath 232 cancelNetwork.io.in.og0CancelVec := og0CancelVecFromDataPath.zip(og0CancelVecFromFinalIssue).map(x => x._1 || x._2) 233 cancelNetwork.io.in.og1CancelVec := og1CancelVec 234 intScheduler.io.fromCancelNetwork <> cancelNetwork.io.out.int 235 vfScheduler.io.fromCancelNetwork <> cancelNetwork.io.out.vf 236 memScheduler.io.fromCancelNetwork <> cancelNetwork.io.out.mem 237 238 dataPath.io.flush := ctrlBlock.io.toDataPath.flush 239 dataPath.io.vconfigReadPort.addr := ctrlBlock.io.toDataPath.vtypeAddr 240 241 dataPath.io.fromIntIQ <> intScheduler.io.toDataPathAfterDelay 242 dataPath.io.fromVfIQ <> vfScheduler.io.toDataPathAfterDelay 243 dataPath.io.fromMemIQ <> memScheduler.io.toDataPathAfterDelay 244 245 dataPath.io.ldCancel := io.mem.ldCancel 246 247 println(s"[Backend] wbDataPath.io.toIntPreg: ${wbDataPath.io.toIntPreg.size}, dataPath.io.fromIntWb: ${dataPath.io.fromIntWb.size}") 248 println(s"[Backend] wbDataPath.io.toVfPreg: ${wbDataPath.io.toVfPreg.size}, dataPath.io.fromFpWb: ${dataPath.io.fromVfWb.size}") 249 dataPath.io.fromIntWb := wbDataPath.io.toIntPreg 250 dataPath.io.fromVfWb := wbDataPath.io.toVfPreg 251 dataPath.io.debugIntRat := ctrlBlock.io.debug_int_rat 252 dataPath.io.debugFpRat := ctrlBlock.io.debug_fp_rat 253 dataPath.io.debugVecRat := ctrlBlock.io.debug_vec_rat 254 dataPath.io.debugVconfigRat := ctrlBlock.io.debug_vconfig_rat 255 256 bypassNetwork.io.fromDataPath.int <> dataPath.io.toIntExu 257 bypassNetwork.io.fromDataPath.vf <> dataPath.io.toFpExu 258 bypassNetwork.io.fromDataPath.mem <> dataPath.io.toMemExu 259 bypassNetwork.io.fromExus.connectExuOutput(_.int)(intExuBlock.io.out) 260 bypassNetwork.io.fromExus.connectExuOutput(_.vf)(vfExuBlock.io.out) 261 bypassNetwork.io.fromExus.mem.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 262 sink.valid := source.valid 263 sink.bits.pdest := source.bits.uop.pdest 264 sink.bits.data := source.bits.data 265 } 266 267 268 intExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 269 for (i <- 0 until intExuBlock.io.in.length) { 270 for (j <- 0 until intExuBlock.io.in(i).length) { 271 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.int(i)(j).bits.loadDependency, io.mem.ldCancel) 272 NewPipelineConnect( 273 bypassNetwork.io.toExus.int(i)(j), intExuBlock.io.in(i)(j), intExuBlock.io.in(i)(j).fire, 274 Mux( 275 bypassNetwork.io.toExus.int(i)(j).fire, 276 bypassNetwork.io.toExus.int(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 277 intExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 278 ) 279 ) 280 } 281 } 282 283 pcTargetMem.io.fromFrontendFtq := io.frontend.fromFtq 284 pcTargetMem.io.fromDataPathFtq := bypassNetwork.io.toExus.int.flatten.filter(_.bits.params.hasPredecode).map(_.bits.ftqIdx.get) 285 intExuBlock.io.in.flatten.filter(_.bits.params.hasPredecode).map(_.bits.predictInfo.get.target).zipWithIndex.foreach { 286 case (sink, i) => 287 sink := pcTargetMem.io.toExus(i) 288 } 289 290 private val csrio = intExuBlock.io.csrio.get 291 csrio.hartId := io.fromTop.hartId 292 csrio.perf.retiredInstr <> ctrlBlock.io.robio.csr.perfinfo.retiredInstr 293 csrio.perf.ctrlInfo <> ctrlBlock.io.perfInfo.ctrlInfo 294 csrio.perf.perfEventsCtrl <> ctrlBlock.getPerf 295 csrio.fpu.fflags := ctrlBlock.io.robio.csr.fflags 296 csrio.fpu.isIllegal := false.B // Todo: remove it 297 csrio.fpu.dirty_fs := ctrlBlock.io.robio.csr.dirty_fs 298 csrio.vpu <> 0.U.asTypeOf(csrio.vpu) // Todo 299 300 val debugVconfig = dataPath.io.debugVconfig.asTypeOf(new VConfig) 301 val debugVtype = VType.toVtypeStruct(debugVconfig.vtype).asUInt 302 val debugVl = debugVconfig.vl 303 csrio.vpu.set_vxsat := ctrlBlock.io.robio.csr.vxsat 304 csrio.vpu.set_vstart.valid := ctrlBlock.io.robio.csr.vcsrFlag 305 csrio.vpu.set_vstart.bits := 0.U 306 csrio.vpu.set_vtype.valid := ctrlBlock.io.robio.csr.vcsrFlag 307 csrio.vpu.set_vtype.bits := ZeroExt(debugVtype, XLEN) 308 csrio.vpu.set_vl.valid := ctrlBlock.io.robio.csr.vcsrFlag 309 csrio.vpu.set_vl.bits := ZeroExt(debugVl, XLEN) 310 csrio.exception := ctrlBlock.io.robio.exception 311 csrio.memExceptionVAddr := io.mem.exceptionVAddr 312 csrio.externalInterrupt := io.fromTop.externalInterrupt 313 csrio.distributedUpdate(0) := io.mem.csrDistributedUpdate 314 csrio.distributedUpdate(1) := io.frontendCsrDistributedUpdate 315 csrio.perf <> io.perf 316 private val fenceio = intExuBlock.io.fenceio.get 317 fenceio.disableSfence := csrio.disableSfence 318 io.fenceio <> fenceio 319 320 vfExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 321 for (i <- 0 until vfExuBlock.io.in.size) { 322 for (j <- 0 until vfExuBlock.io.in(i).size) { 323 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.vf(i)(j).bits.loadDependency, io.mem.ldCancel) 324 NewPipelineConnect( 325 bypassNetwork.io.toExus.vf(i)(j), vfExuBlock.io.in(i)(j), vfExuBlock.io.in(i)(j).fire, 326 Mux( 327 bypassNetwork.io.toExus.vf(i)(j).fire, 328 bypassNetwork.io.toExus.vf(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 329 vfExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 330 ) 331 ) 332 333 vfExuBlock.io.in(i)(j).bits.vpu.foreach(_.vstart := csrio.vpu.vstart) 334 } 335 } 336 vfExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 337 338 wbDataPath.io.flush := ctrlBlock.io.redirect 339 wbDataPath.io.fromTop.hartId := io.fromTop.hartId 340 wbDataPath.io.fromIntExu <> intExuBlock.io.out 341 wbDataPath.io.fromVfExu <> vfExuBlock.io.out 342 wbDataPath.io.fromMemExu.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 343 sink.valid := source.valid 344 source.ready := sink.ready 345 sink.bits.data := source.bits.data 346 sink.bits.pdest := source.bits.uop.pdest 347 sink.bits.robIdx := source.bits.uop.robIdx 348 sink.bits.intWen.foreach(_ := source.bits.uop.rfWen) 349 sink.bits.fpWen.foreach(_ := source.bits.uop.fpWen) 350 sink.bits.vecWen.foreach(_ := source.bits.uop.vecWen) 351 sink.bits.exceptionVec.foreach(_ := source.bits.uop.exceptionVec) 352 sink.bits.flushPipe.foreach(_ := source.bits.uop.flushPipe) 353 sink.bits.replay.foreach(_ := source.bits.uop.replayInst) 354 sink.bits.debug := source.bits.debug 355 sink.bits.debugInfo := 0.U.asTypeOf(sink.bits.debugInfo) 356 sink.bits.lqIdx.foreach(_ := source.bits.uop.lqIdx) 357 sink.bits.sqIdx.foreach(_ := source.bits.uop.sqIdx) 358 sink.bits.ftqIdx.foreach(_ := source.bits.uop.ftqPtr) 359 sink.bits.ftqOffset.foreach(_ := source.bits.uop.ftqOffset) 360 } 361 362 // to mem 363 private val memIssueParams = params.memSchdParams.get.issueBlockParams 364 private val memExuBlocksHasLDU = memIssueParams.map(_.exuBlockParams.map(_.fuConfigs.contains(FuConfig.LduCfg))) 365 private val toMem = Wire(bypassNetwork.io.toExus.mem.cloneType) 366 for (i <- toMem.indices) { 367 for (j <- toMem(i).indices) { 368 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.mem(i)(j).bits.loadDependency, io.mem.ldCancel) 369 val issueTimeout = 370 if (memExuBlocksHasLDU(i)(j)) 371 Counter(0 until 16, toMem(i)(j).valid && !toMem(i)(j).fire, bypassNetwork.io.toExus.mem(i)(j).fire)._2 372 else 373 false.B 374 375 if (memScheduler.io.loadFinalIssueResp(i).nonEmpty) { 376 memScheduler.io.loadFinalIssueResp(i)(j).valid := issueTimeout 377 memScheduler.io.loadFinalIssueResp(i)(j).bits.dataInvalidSqIdx := DontCare 378 memScheduler.io.loadFinalIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType 379 memScheduler.io.loadFinalIssueResp(i)(j).bits.respType := RSFeedbackType.fuBusy 380 memScheduler.io.loadFinalIssueResp(i)(j).bits.rfWen := toMem(i)(j).bits.rfWen.getOrElse(false.B) 381 memScheduler.io.loadFinalIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx 382 } 383 384 NewPipelineConnect( 385 bypassNetwork.io.toExus.mem(i)(j), toMem(i)(j), toMem(i)(j).fire, 386 Mux( 387 bypassNetwork.io.toExus.mem(i)(j).fire, 388 bypassNetwork.io.toExus.mem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 389 toMem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || issueTimeout 390 ) 391 ) 392 } 393 } 394 395 io.mem.redirect := ctrlBlock.io.redirect 396 io.mem.issueUops.zip(toMem.flatten).foreach { case (sink, source) => 397 sink.valid := source.valid 398 source.ready := sink.ready 399 sink.bits.iqIdx := source.bits.iqIdx 400 sink.bits.isFirstIssue := source.bits.isFirstIssue 401 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 402 sink.bits.src := 0.U.asTypeOf(sink.bits.src) 403 sink.bits.src.zip(source.bits.src).foreach { case (l, r) => l := r} 404 sink.bits.deqPortIdx := source.bits.deqPortIdx.getOrElse(0.U) 405 sink.bits.uop.fuType := source.bits.fuType 406 sink.bits.uop.fuOpType := source.bits.fuOpType 407 sink.bits.uop.imm := source.bits.imm 408 sink.bits.uop.robIdx := source.bits.robIdx 409 sink.bits.uop.pdest := source.bits.pdest 410 sink.bits.uop.rfWen := source.bits.rfWen.getOrElse(false.B) 411 sink.bits.uop.fpWen := source.bits.fpWen.getOrElse(false.B) 412 sink.bits.uop.vecWen := source.bits.vecWen.getOrElse(false.B) 413 sink.bits.uop.flushPipe := source.bits.flushPipe.getOrElse(false.B) 414 sink.bits.uop.pc := source.bits.pc.getOrElse(0.U) 415 sink.bits.uop.lqIdx := source.bits.lqIdx.getOrElse(0.U.asTypeOf(new LqPtr)) 416 sink.bits.uop.sqIdx := source.bits.sqIdx.getOrElse(0.U.asTypeOf(new SqPtr)) 417 sink.bits.uop.ftqPtr := source.bits.ftqIdx.getOrElse(0.U.asTypeOf(new FtqPtr)) 418 sink.bits.uop.ftqOffset := source.bits.ftqOffset.getOrElse(0.U) 419 } 420 io.mem.loadFastMatch := memScheduler.io.toMem.get.loadFastMatch.map(_.fastMatch) 421 io.mem.loadFastImm := memScheduler.io.toMem.get.loadFastMatch.map(_.fastImm) 422 io.mem.tlbCsr := csrio.tlb 423 io.mem.csrCtrl := csrio.customCtrl 424 io.mem.sfence := fenceio.sfence 425 io.mem.isStoreException := CommitType.lsInstIsStore(ctrlBlock.io.robio.exception.bits.commitType) 426 require(io.mem.loadPcRead.size == params.LduCnt) 427 io.mem.loadPcRead.zipWithIndex.foreach { case (loadPcRead, i) => 428 loadPcRead.data := ctrlBlock.io.memLdPcRead(i).data 429 ctrlBlock.io.memLdPcRead(i).ptr := loadPcRead.ptr 430 ctrlBlock.io.memLdPcRead(i).offset := loadPcRead.offset 431 } 432 433 ctrlBlock.io.robio.robHeadLsIssue := io.mem.issueUops.map(deq => deq.fire && deq.bits.uop.robIdx === ctrlBlock.io.robio.robDeqPtr).reduce(_ || _) 434 435 // mem io 436 io.mem.lsqEnqIO <> memScheduler.io.memIO.get.lsqEnqIO 437 io.mem.robLsqIO <> ctrlBlock.io.robio.lsq 438 io.mem.toSbuffer <> fenceio.sbuffer 439 440 private val intFinalIssueBlock = intExuBlock.io.in.flatten.map(_ => false.B) 441 private val vfFinalIssueBlock = vfExuBlock.io.in.flatten.map(_ => false.B) 442 private val memFinalIssueBlock = io.mem.issueUops zip memExuBlocksHasLDU.flatten map { 443 case (out, isLdu) => 444 if (isLdu) RegNext(out.valid && !out.ready, false.B) 445 else false.B 446 } 447 og0CancelVecFromFinalIssue := intFinalIssueBlock ++ vfFinalIssueBlock ++ memFinalIssueBlock 448 449 io.frontendSfence := fenceio.sfence 450 io.frontendTlbCsr := csrio.tlb 451 io.frontendCsrCtrl := csrio.customCtrl 452 453 io.tlb <> csrio.tlb 454 455 io.csrCustomCtrl := csrio.customCtrl 456 457 dontTouch(memScheduler.io) 458 dontTouch(io.mem) 459 dontTouch(dataPath.io.toMemExu) 460 dontTouch(wbDataPath.io.fromMemExu) 461} 462 463class BackendMemIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 464 // params alias 465 private val LoadQueueSize = VirtualLoadQueueSize 466 // In/Out // Todo: split it into one-direction bundle 467 val lsqEnqIO = Flipped(new LsqEnqIO) 468 val robLsqIO = new RobLsqIO 469 val toSbuffer = new FenceToSbuffer 470 val ldaIqFeedback = Vec(params.LduCnt, Flipped(new MemRSFeedbackIO)) 471 val staIqFeedback = Vec(params.StaCnt, Flipped(new MemRSFeedbackIO)) 472 val ldCancel = Vec(params.LduCnt, Flipped(new LoadCancelIO)) 473 val loadPcRead = Vec(params.LduCnt, Flipped(new FtqRead(UInt(VAddrBits.W)))) 474 475 // Input 476 val writeBack = MixedVec(Seq.fill(params.LduCnt + params.StaCnt * 2)(Flipped(DecoupledIO(new MemExuOutput()))) ++ Seq.fill(params.VlduCnt)(Flipped(DecoupledIO(new MemExuOutput(true))))) 477 478 val s3_delayed_load_error = Input(Vec(LoadPipelineWidth, Bool())) 479 val stIn = Input(Vec(params.StaCnt, ValidIO(new DynInst()))) 480 val memoryViolation = Flipped(ValidIO(new Redirect)) 481 val exceptionVAddr = Input(UInt(VAddrBits.W)) 482 val sqDeq = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) 483 val lqDeq = Input(UInt(log2Up(CommitWidth + 1).W)) 484 485 val lqCancelCnt = Input(UInt(log2Up(VirtualLoadQueueSize + 1).W)) 486 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 487 488 val lqCanAccept = Input(Bool()) 489 val sqCanAccept = Input(Bool()) 490 491 val otherFastWakeup = Flipped(Vec(params.LduCnt + 2 * params.StaCnt, ValidIO(new DynInst))) 492 val stIssuePtr = Input(new SqPtr()) 493 494 val csrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 495 496 val debugLS = Flipped(Output(new DebugLSIO)) 497 498 val lsTopdownInfo = Vec(params.LduCnt, Flipped(Output(new LsTopdownInfo))) 499 // Output 500 val redirect = ValidIO(new Redirect) // rob flush MemBlock 501 val issueUops = MixedVec(Seq.fill(params.LduCnt + params.StaCnt + params.StdCnt)(DecoupledIO(new MemExuInput())) ++ Seq.fill(params.VlduCnt)(DecoupledIO(new MemExuInput(true)))) 502 val loadFastMatch = Vec(params.LduCnt, Output(UInt(params.LduCnt.W))) 503 val loadFastImm = Vec(params.LduCnt, Output(UInt(12.W))) // Imm_I 504 505 val tlbCsr = Output(new TlbCsrBundle) 506 val csrCtrl = Output(new CustomCSRCtrlIO) 507 val sfence = Output(new SfenceBundle) 508 val isStoreException = Output(Bool()) 509} 510 511class BackendIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 512 val fromTop = new Bundle { 513 val hartId = Input(UInt(8.W)) 514 val externalInterrupt = new ExternalInterruptIO 515 } 516 517 val toTop = new Bundle { 518 val cpuHalted = Output(Bool()) 519 } 520 521 val fenceio = new FenceIO 522 // Todo: merge these bundles into BackendFrontendIO 523 val frontend = Flipped(new FrontendToCtrlIO) 524 val frontendSfence = Output(new SfenceBundle) 525 val frontendCsrCtrl = Output(new CustomCSRCtrlIO) 526 val frontendTlbCsr = Output(new TlbCsrBundle) 527 // distributed csr write 528 val frontendCsrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 529 530 val mem = new BackendMemIO 531 532 val perf = Input(new PerfCounterIO) 533 534 val tlb = Output(new TlbCsrBundle) 535 536 val csrCustomCtrl = Output(new CustomCSRCtrlIO) 537} 538