1package xiangshan.backend 2 3import bus.simplebus.SimpleBusUC 4import chisel3._ 5import chisel3.util._ 6import chisel3.util.experimental.BoringUtils 7import noop.MemMMUIO 8import xiangshan._ 9import xiangshan.backend.decode.{DecodeBuffer, DecodeStage} 10import xiangshan.backend.rename.Rename 11import xiangshan.backend.brq.Brq 12import xiangshan.backend.dispatch.Dispatch 13import xiangshan.backend.exu._ 14import xiangshan.backend.fu.FunctionUnit 15import xiangshan.backend.issue.{IssueQueue, ReservationStation} 16import xiangshan.backend.regfile.{Regfile, RfWritePort} 17import xiangshan.backend.roq.Roq 18import xiangshan.mem._ 19import utils.ParallelOR 20 21/** Backend Pipeline: 22 * Decode -> Rename -> Dispatch-1 -> Dispatch-2 -> Issue -> Exe 23 */ 24class Backend extends XSModule 25 with NeedImpl { 26 val io = IO(new Bundle { 27 val frontend = Flipped(new FrontendToBackendIO) 28 val mem = Flipped(new MemToBackendIO) 29 }) 30 31 32 val aluExeUnits =Array.tabulate(exuParameters.AluCnt)(_ => Module(new AluExeUnit)) 33 val jmpExeUnit = Module(new JmpExeUnit) 34 val mulExeUnits = Array.tabulate(exuParameters.MulCnt)(_ => Module(new MulExeUnit)) 35 val mduExeUnits = Array.tabulate(exuParameters.MduCnt)(_ => Module(new MulDivExeUnit)) 36 // val fmacExeUnits = Array.tabulate(exuParameters.FmacCnt)(_ => Module(new Fmac)) 37 // val fmiscExeUnits = Array.tabulate(exuParameters.FmiscCnt)(_ => Module(new Fmisc)) 38 // val fmiscDivSqrtExeUnits = Array.tabulate(exuParameters.FmiscDivSqrtCnt)(_ => Module(new FmiscDivSqrt)) 39 val exeUnits = jmpExeUnit +: (aluExeUnits ++ mulExeUnits ++ mduExeUnits) 40 exeUnits.foreach(_.io.exception := DontCare) 41 exeUnits.foreach(_.io.dmem := DontCare) 42 exeUnits.foreach(_.io.mcommit := DontCare) 43 44 val decode = Module(new DecodeStage) 45 val brq = Module(new Brq) 46 val decBuf = Module(new DecodeBuffer) 47 val rename = Module(new Rename) 48 val dispatch = Module(new Dispatch) 49 val roq = Module(new Roq) 50 val intRf = Module(new Regfile( 51 numReadPorts = NRIntReadPorts, 52 numWirtePorts = NRIntWritePorts, 53 hasZero = true 54 )) 55 val fpRf = Module(new Regfile( 56 numReadPorts = NRFpReadPorts, 57 numWirtePorts = NRFpWritePorts, 58 hasZero = false 59 )) 60 61 // backend redirect, flush pipeline 62 val redirect = Mux( 63 roq.io.redirect.valid, 64 roq.io.redirect, 65 Mux( 66 brq.io.redirect.valid, 67 brq.io.redirect, 68 io.mem.replayAll 69 ) 70 ) 71 72 io.frontend.redirect := redirect 73 io.frontend.redirect.valid := redirect.valid && !redirect.bits.isReplay 74 75 val memConfigs = 76 Seq.fill(exuParameters.LduCnt)(Exu.ldExeUnitCfg) ++ 77 Seq.fill(exuParameters.StuCnt)(Exu.stExeUnitCfg) 78 79 val exuConfigs = exeUnits.map(_.config) ++ memConfigs 80 81 val exeWbReqs = exeUnits.map(_.io.out) ++ io.mem.ldout ++ io.mem.stout 82 83 def needWakeup(cfg: ExuConfig): Boolean = 84 (cfg.readIntRf && cfg.writeIntRf) || (cfg.readFpRf && cfg.writeFpRf) 85 86 def needData(a: ExuConfig, b: ExuConfig): Boolean = 87 (a.readIntRf && b.writeIntRf) || (a.readFpRf && b.writeFpRf) 88 89 90 val reservedStations = exuConfigs.zipWithIndex.map({ case (cfg, i) => 91 val wakeUpDateVec = exuConfigs.zip(exeWbReqs).filter(x => needData(cfg, x._1)).map(_._2) 92 val bypassCnt = exuConfigs.count(c => c.enableBypass && needData(cfg, c)) 93 94 println(s"exu:${cfg.name} wakeupCnt:${wakeUpDateVec.length} bypassCnt:$bypassCnt") 95 96 val rs = Module(new ReservationStation( 97 cfg, wakeUpDateVec.length, bypassCnt, cfg.enableBypass, fifo = false 98 )) 99 rs.io.redirect <> redirect 100 rs.io.numExist <> dispatch.io.numExist(i) 101 rs.io.enqCtrl <> dispatch.io.enqIQCtrl(i) 102 rs.io.enqData <> dispatch.io.enqIQData(i) 103 for( 104 (wakeUpPort, exuOut) <- 105 rs.io.wakeUpPorts.zip(wakeUpDateVec) 106 ){ 107 wakeUpPort.bits := exuOut.bits 108 wakeUpPort.valid := exuOut.valid 109 } 110 111 112 cfg match { 113 case Exu.ldExeUnitCfg => 114 case Exu.stExeUnitCfg => 115 case otherCfg => 116 exeUnits(i).io.in <> rs.io.deq 117 exeUnits(i).io.redirect <> redirect 118 } 119 120 rs 121 }) 122 123 for( rs <- reservedStations){ 124 rs.io.bypassUops <> reservedStations. 125 filter(x => x.enableBypass && needData(rs.exuCfg, x.exuCfg)). 126 map(_.io.selectedUop) 127 128 val bypassDataVec = exuConfigs.zip(exeWbReqs). 129 filter(x => x._1.enableBypass && needData(rs.exuCfg, x._1)).map(_._2) 130 131 for(i <- bypassDataVec.indices){ 132 rs.io.bypassData(i).valid := bypassDataVec(i).valid 133 rs.io.bypassData(i).bits := bypassDataVec(i).bits 134 } 135 } 136 137 io.mem.commits <> roq.io.commits 138 io.mem.roqDeqPtr := roq.io.roqDeqPtr 139 io.mem.ldin <> reservedStations.filter(_.exuCfg == Exu.ldExeUnitCfg).map(_.io.deq) 140 io.mem.stin <> reservedStations.filter(_.exuCfg == Exu.stExeUnitCfg).map(_.io.deq) 141 jmpExeUnit.io.exception.valid := roq.io.redirect.valid && roq.io.redirect.bits.isException 142 jmpExeUnit.io.exception.bits := roq.io.exception 143 144 io.frontend.outOfOrderBrInfo <> brq.io.outOfOrderBrInfo 145 io.frontend.inOrderBrInfo <> brq.io.inOrderBrInfo 146 147 decode.io.in <> io.frontend.cfVec 148 brq.io.roqRedirect <> roq.io.redirect 149 brq.io.memRedirect <> io.mem.replayAll 150 brq.io.bcommit := roq.io.bcommit 151 brq.io.enqReqs <> decode.io.toBrq 152 for ((x, y) <- brq.io.exuRedirect.zip(exeUnits.filter(_.config.hasRedirect))) { 153 x.bits := y.io.out.bits 154 x.valid := y.io.out.fire() && y.io.out.bits.redirectValid 155 } 156 decode.io.brTags <> brq.io.brTags 157 decBuf.io.isWalking := ParallelOR(roq.io.commits.map(c => c.valid && c.bits.isWalk)) // TODO: opt this 158 decBuf.io.redirect <> redirect 159 decBuf.io.in <> decode.io.out 160 161 rename.io.redirect <> redirect 162 rename.io.roqCommits <> roq.io.commits 163 rename.io.in <> decBuf.io.out 164 rename.io.intRfReadAddr <> dispatch.io.readIntRf.map(_.addr) ++ dispatch.io.intMemRegAddr 165 rename.io.intPregRdy <> dispatch.io.intPregRdy ++ dispatch.io.intMemRegRdy 166 rename.io.fpRfReadAddr <> dispatch.io.readFpRf.map(_.addr) ++ dispatch.io.fpMemRegAddr 167 rename.io.fpPregRdy <> dispatch.io.fpPregRdy ++ dispatch.io.fpMemRegRdy 168 rename.io.replayPregReq <> dispatch.io.replayPregReq 169 dispatch.io.redirect <> redirect 170 dispatch.io.fromRename <> rename.io.out 171 172 roq.io.memRedirect <> io.mem.replayAll 173 roq.io.brqRedirect <> brq.io.redirect 174 roq.io.dp1Req <> dispatch.io.toRoq 175 dispatch.io.roqIdxs <> roq.io.roqIdxs 176 io.mem.dp1Req <> dispatch.io.toLsroq 177 dispatch.io.lsroqIdxs <> io.mem.lsroqIdxs 178 dispatch.io.commits <> roq.io.commits 179 180 intRf.io.readPorts <> dispatch.io.readIntRf 181 fpRf.io.readPorts <> dispatch.io.readFpRf 182 183 io.mem.redirect <> redirect 184 185 val wbu = Module(new Wbu(exuConfigs)) 186 wbu.io.in <> exeWbReqs 187 188 val wbIntResults = wbu.io.toIntRf 189 val wbFpResults = wbu.io.toFpRf 190 191 def exuOutToRfWrite(x: Valid[ExuOutput]): RfWritePort = { 192 val rfWrite = Wire(new RfWritePort) 193 rfWrite.wen := x.valid 194 rfWrite.addr := x.bits.uop.pdest 195 rfWrite.data := x.bits.data 196 rfWrite 197 } 198 intRf.io.writePorts <> wbIntResults.map(exuOutToRfWrite) 199 fpRf.io.writePorts <> wbFpResults.map(exuOutToRfWrite) 200 201 rename.io.wbIntResults <> wbIntResults 202 rename.io.wbFpResults <> wbFpResults 203 204 roq.io.exeWbResults.take(exeWbReqs.length).zip(wbu.io.toRoq).foreach(x => x._1 := x._2) 205 roq.io.exeWbResults.last := brq.io.out 206 207 208 // TODO: Remove sink and source 209 val tmp = WireInit(0.U) 210 val sinks = Array[String]( 211 "DTLBFINISH", 212 "DTLBPF", 213 "DTLBENABLE", 214 "perfCntCondMdcacheLoss", 215 "perfCntCondMl2cacheLoss", 216 "perfCntCondMdcacheHit", 217 "lsuMMIO", 218 "perfCntCondMl2cacheHit", 219 "perfCntCondMl2cacheReq", 220 "mtip", 221 "perfCntCondMdcacheReq", 222 "meip" 223 ) 224 for (s <- sinks) { 225 BoringUtils.addSink(tmp, s) 226 } 227 228 val debugIntReg, debugFpReg = WireInit(VecInit(Seq.fill(32)(0.U(XLEN.W)))) 229 BoringUtils.addSink(debugIntReg, "DEBUG_INT_ARCH_REG") 230 BoringUtils.addSink(debugFpReg, "DEBUG_FP_ARCH_REG") 231 val debugArchReg = WireInit(VecInit(debugIntReg ++ debugFpReg)) 232 if (!env.FPGAPlatform) { 233 BoringUtils.addSource(debugArchReg, "difftestRegs") 234 } 235 236} 237