1package xiangshan.backend 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import utility.{Constantin, ZeroExt} 8import xiangshan._ 9import xiangshan.backend.Bundles.{DynInst, IssueQueueIQWakeUpBundle, LoadShouldCancel, MemExuInput, MemExuOutput, VPUCtrlSignals} 10import xiangshan.backend.ctrlblock.{DebugLSIO, LsTopdownInfo} 11import xiangshan.backend.datapath.DataConfig.{IntData, VecData} 12import xiangshan.backend.datapath.RdConfig.{IntRD, VfRD} 13import xiangshan.backend.datapath.WbConfig._ 14import xiangshan.backend.datapath._ 15import xiangshan.backend.dispatch.CoreDispatchTopDownIO 16import xiangshan.backend.exu.ExuBlock 17import xiangshan.backend.fu.vector.Bundles.{VConfig, VType} 18import xiangshan.backend.fu.{FenceIO, FenceToSbuffer, FuConfig, FuType, PerfCounterIO} 19import xiangshan.backend.issue.EntryBundles._ 20import xiangshan.backend.issue.{CancelNetwork, Scheduler, SchedulerImpBase} 21import xiangshan.backend.rob.{RobCoreTopDownIO, RobDebugRollingIO, RobLsqIO, RobPtr} 22import xiangshan.frontend.{FtqPtr, FtqRead, PreDecodeInfo} 23import xiangshan.mem.{LqPtr, LsqEnqIO, SqPtr} 24import scala.collection.mutable 25 26class Backend(val params: BackendParams)(implicit p: Parameters) extends LazyModule 27 with HasXSParameter { 28 29 override def shouldBeInlined: Boolean = false 30 31 /* Only update the idx in mem-scheduler here 32 * Idx in other schedulers can be updated the same way if needed 33 * 34 * Also note that we filter out the 'stData issue-queues' when counting 35 */ 36 for ((ibp, idx) <- params.memSchdParams.get.issueBlockParams.filter(iq => iq.StdCnt == 0 && iq.VstdCnt == 0).zipWithIndex) { 37 ibp.updateIdx(idx) 38 } 39 40 println(params.iqWakeUpParams) 41 42 for ((schdCfg, i) <- params.allSchdParams.zipWithIndex) { 43 schdCfg.bindBackendParam(params) 44 } 45 46 for ((iqCfg, i) <- params.allIssueParams.zipWithIndex) { 47 iqCfg.bindBackendParam(params) 48 } 49 50 for ((exuCfg, i) <- params.allExuParams.zipWithIndex) { 51 exuCfg.bindBackendParam(params) 52 exuCfg.updateIQWakeUpConfigs(params.iqWakeUpParams) 53 exuCfg.updateExuIdx(i) 54 } 55 56 println("[Backend] ExuConfigs:") 57 for (exuCfg <- params.allExuParams) { 58 val fuConfigs = exuCfg.fuConfigs 59 val wbPortConfigs = exuCfg.wbPortConfigs 60 val immType = exuCfg.immType 61 62 println("[Backend] " + 63 s"${exuCfg.name}: " + 64 (if (exuCfg.fakeUnit) "fake, " else "") + 65 (if (exuCfg.hasLoadFu || exuCfg.hasHyldaFu) s"LdExuIdx(${backendParams.getLdExuIdx(exuCfg)})" else "") + 66 s"${fuConfigs.map(_.name).mkString("fu(s): {", ",", "}")}, " + 67 s"${wbPortConfigs.mkString("wb: {", ",", "}")}, " + 68 s"${immType.map(SelImm.mkString(_)).mkString("imm: {", ",", "}")}, " + 69 s"latMax(${exuCfg.latencyValMax}), ${exuCfg.fuLatancySet.mkString("lat: {", ",", "}")}, " + 70 s"srcReg(${exuCfg.numRegSrc})" 71 ) 72 require( 73 wbPortConfigs.collectFirst { case x: IntWB => x }.nonEmpty == 74 fuConfigs.map(_.writeIntRf).reduce(_ || _), 75 s"${exuCfg.name} int wb port has no priority" 76 ) 77 require( 78 wbPortConfigs.collectFirst { case x: VfWB => x }.nonEmpty == 79 fuConfigs.map(x => x.writeFpRf || x.writeVecRf).reduce(_ || _), 80 s"${exuCfg.name} vec wb port has no priority" 81 ) 82 } 83 84 println(s"[Backend] all fu configs") 85 for (cfg <- FuConfig.allConfigs) { 86 println(s"[Backend] $cfg") 87 } 88 89 println(s"[Backend] Int RdConfigs: ExuName(Priority)") 90 for ((port, seq) <- params.getRdPortParams(IntData())) { 91 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 92 } 93 94 println(s"[Backend] Int WbConfigs: ExuName(Priority)") 95 for ((port, seq) <- params.getWbPortParams(IntData())) { 96 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 97 } 98 99 println(s"[Backend] Vf RdConfigs: ExuName(Priority)") 100 for ((port, seq) <- params.getRdPortParams(VecData())) { 101 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 102 } 103 104 println(s"[Backend] Vf WbConfigs: ExuName(Priority)") 105 for ((port, seq) <- params.getWbPortParams(VecData())) { 106 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 107 } 108 109 println(s"[Backend] Dispatch Configs:") 110 println(s"[Backend] Load IQ enq width(${params.numLoadDp}), Store IQ enq width(${params.numStoreDp})") 111 println(s"[Backend] Load DP width(${LSQLdEnqWidth}), Store DP width(${LSQStEnqWidth})") 112 113 params.updateCopyPdestInfo 114 println(s"[Backend] copyPdestInfo ${params.copyPdestInfo}") 115 params.allExuParams.map(_.copyNum) 116 val ctrlBlock = LazyModule(new CtrlBlock(params)) 117 val pcTargetMem = LazyModule(new PcTargetMem(params)) 118 val intScheduler = params.intSchdParams.map(x => LazyModule(new Scheduler(x))) 119 val vfScheduler = params.vfSchdParams.map(x => LazyModule(new Scheduler(x))) 120 val memScheduler = params.memSchdParams.map(x => LazyModule(new Scheduler(x))) 121 val dataPath = LazyModule(new DataPath(params)) 122 val intExuBlock = params.intSchdParams.map(x => LazyModule(new ExuBlock(x))) 123 val vfExuBlock = params.vfSchdParams.map(x => LazyModule(new ExuBlock(x))) 124 val wbFuBusyTable = LazyModule(new WbFuBusyTable(params)) 125 126 lazy val module = new BackendImp(this) 127} 128 129class BackendImp(override val wrapper: Backend)(implicit p: Parameters) extends LazyModuleImp(wrapper) 130 with HasXSParameter { 131 implicit private val params = wrapper.params 132 133 val io = IO(new BackendIO()(p, wrapper.params)) 134 135 private val ctrlBlock = wrapper.ctrlBlock.module 136 private val pcTargetMem = wrapper.pcTargetMem.module 137 private val intScheduler: SchedulerImpBase = wrapper.intScheduler.get.module 138 private val vfScheduler = wrapper.vfScheduler.get.module 139 private val memScheduler = wrapper.memScheduler.get.module 140 private val dataPath = wrapper.dataPath.module 141 private val intExuBlock = wrapper.intExuBlock.get.module 142 private val vfExuBlock = wrapper.vfExuBlock.get.module 143 private val bypassNetwork = Module(new BypassNetwork) 144 private val wbDataPath = Module(new WbDataPath(params)) 145 private val wbFuBusyTable = wrapper.wbFuBusyTable.module 146 147 private val iqWakeUpMappedBundle: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = ( 148 intScheduler.io.toSchedulers.wakeupVec ++ 149 vfScheduler.io.toSchedulers.wakeupVec ++ 150 memScheduler.io.toSchedulers.wakeupVec 151 ).map(x => (x.bits.exuIdx, x)).toMap 152 153 println(s"[Backend] iq wake up keys: ${iqWakeUpMappedBundle.keys}") 154 155 wbFuBusyTable.io.in.intSchdBusyTable := intScheduler.io.wbFuBusyTable 156 wbFuBusyTable.io.in.vfSchdBusyTable := vfScheduler.io.wbFuBusyTable 157 wbFuBusyTable.io.in.memSchdBusyTable := memScheduler.io.wbFuBusyTable 158 intScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.intRespRead 159 vfScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.vfRespRead 160 memScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.memRespRead 161 dataPath.io.wbConfictRead := wbFuBusyTable.io.out.wbConflictRead 162 163 wbDataPath.io.fromIntExu.flatten.filter(x => x.bits.params.writeIntRf) 164 165 private val vconfig = dataPath.io.vconfigReadPort.data 166 private val og1CancelOH: UInt = dataPath.io.og1CancelOH 167 private val og0CancelOH: UInt = dataPath.io.og0CancelOH 168 private val cancelToBusyTable = dataPath.io.cancelToBusyTable 169 170 ctrlBlock.io.IQValidNumVec := intScheduler.io.IQValidNumVec 171 ctrlBlock.io.fromTop.hartId := io.fromTop.hartId 172 ctrlBlock.io.frontend <> io.frontend 173 ctrlBlock.io.fromWB.wbData <> wbDataPath.io.toCtrlBlock.writeback 174 ctrlBlock.io.fromMem.stIn <> io.mem.stIn 175 ctrlBlock.io.fromMem.violation <> io.mem.memoryViolation 176 ctrlBlock.io.lqCanAccept := io.mem.lqCanAccept 177 ctrlBlock.io.sqCanAccept := io.mem.sqCanAccept 178 ctrlBlock.io.csrCtrl <> intExuBlock.io.csrio.get.customCtrl 179 ctrlBlock.io.robio.csr.intrBitSet := intExuBlock.io.csrio.get.interrupt 180 ctrlBlock.io.robio.csr.trapTarget := intExuBlock.io.csrio.get.trapTarget 181 ctrlBlock.io.robio.csr.isXRet := intExuBlock.io.csrio.get.isXRet 182 ctrlBlock.io.robio.csr.wfiEvent := intExuBlock.io.csrio.get.wfi_event 183 ctrlBlock.io.robio.lsq <> io.mem.robLsqIO 184 ctrlBlock.io.robio.lsTopdownInfo <> io.mem.lsTopdownInfo 185 ctrlBlock.io.robio.debug_ls <> io.mem.debugLS 186 ctrlBlock.io.fromDataPath.vtype := vconfig(7, 0).asTypeOf(new VType) 187 ctrlBlock.perfinfo := DontCare // TODO: Implement backend hpm 188 ctrlBlock.io.debugEnqLsq.canAccept := io.mem.lsqEnqIO.canAccept 189 ctrlBlock.io.debugEnqLsq.resp := io.mem.lsqEnqIO.resp 190 ctrlBlock.io.debugEnqLsq.req := memScheduler.io.memIO.get.lsqEnqIO.req 191 ctrlBlock.io.debugEnqLsq.needAlloc := memScheduler.io.memIO.get.lsqEnqIO.needAlloc 192 193 194 intScheduler.io.fromTop.hartId := io.fromTop.hartId 195 intScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 196 intScheduler.io.fromCtrlBlock.pcVec := ctrlBlock.io.toIssueBlock.pcVec 197 intScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 198 intScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.intUops 199 intScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 200 intScheduler.io.vfWriteBack := 0.U.asTypeOf(intScheduler.io.vfWriteBack) 201 intScheduler.io.fromDataPath.resp := dataPath.io.toIntIQ 202 intScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 203 intScheduler.io.fromDataPath.og0Cancel := og0CancelOH 204 intScheduler.io.fromDataPath.og1Cancel := og1CancelOH 205 intScheduler.io.ldCancel := io.mem.ldCancel 206 intScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 207 208 memScheduler.io.fromTop.hartId := io.fromTop.hartId 209 memScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 210 memScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 211 memScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.memUops 212 memScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 213 memScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 214 memScheduler.io.fromMem.get.scommit := io.mem.sqDeq 215 memScheduler.io.fromMem.get.lcommit := io.mem.lqDeq 216 memScheduler.io.fromMem.get.wakeup := io.mem.wakeup 217 memScheduler.io.fromMem.get.sqDeqPtr := io.mem.sqDeqPtr 218 memScheduler.io.fromMem.get.lqDeqPtr := io.mem.lqDeqPtr 219 memScheduler.io.fromMem.get.sqCancelCnt := io.mem.sqCancelCnt 220 memScheduler.io.fromMem.get.lqCancelCnt := io.mem.lqCancelCnt 221 memScheduler.io.fromMem.get.stIssuePtr := io.mem.stIssuePtr 222 require(memScheduler.io.fromMem.get.memWaitUpdateReq.robIdx.length == io.mem.stIn.length) 223 memScheduler.io.fromMem.get.memWaitUpdateReq.robIdx.zip(io.mem.stIn).foreach { case (sink, source) => 224 sink.valid := source.valid 225 sink.bits := source.bits.robIdx 226 } 227 memScheduler.io.fromMem.get.memWaitUpdateReq.sqIdx := DontCare // TODO 228 memScheduler.io.fromDataPath.resp := dataPath.io.toMemIQ 229 memScheduler.io.fromMem.get.ldaFeedback := io.mem.ldaIqFeedback 230 memScheduler.io.fromMem.get.staFeedback := io.mem.staIqFeedback 231 memScheduler.io.fromMem.get.hyuFeedback := io.mem.hyuIqFeedback 232 memScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 233 memScheduler.io.fromDataPath.og0Cancel := og0CancelOH 234 memScheduler.io.fromDataPath.og1Cancel := og1CancelOH 235 memScheduler.io.ldCancel := io.mem.ldCancel 236 memScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 237 238 vfScheduler.io.fromTop.hartId := io.fromTop.hartId 239 vfScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 240 vfScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 241 vfScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.vfUops 242 vfScheduler.io.intWriteBack := 0.U.asTypeOf(vfScheduler.io.intWriteBack) 243 vfScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 244 vfScheduler.io.fromDataPath.resp := dataPath.io.toVfIQ 245 vfScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 246 vfScheduler.io.fromDataPath.og0Cancel := og0CancelOH 247 vfScheduler.io.fromDataPath.og1Cancel := og1CancelOH 248 vfScheduler.io.ldCancel := io.mem.ldCancel 249 vfScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 250 251 dataPath.io.hartId := io.fromTop.hartId 252 dataPath.io.flush := ctrlBlock.io.toDataPath.flush 253 dataPath.io.vconfigReadPort.addr := ctrlBlock.io.toDataPath.vtypeAddr 254 dataPath.io.vldReadPort.addr := wbDataPath.io.oldVdAddrToDataPath 255 256 dataPath.io.fromIntIQ <> intScheduler.io.toDataPathAfterDelay 257 dataPath.io.fromVfIQ <> vfScheduler.io.toDataPathAfterDelay 258 dataPath.io.fromMemIQ <> memScheduler.io.toDataPathAfterDelay 259 260 dataPath.io.ldCancel := io.mem.ldCancel 261 262 println(s"[Backend] wbDataPath.io.toIntPreg: ${wbDataPath.io.toIntPreg.size}, dataPath.io.fromIntWb: ${dataPath.io.fromIntWb.size}") 263 println(s"[Backend] wbDataPath.io.toVfPreg: ${wbDataPath.io.toVfPreg.size}, dataPath.io.fromFpWb: ${dataPath.io.fromVfWb.size}") 264 dataPath.io.fromIntWb := wbDataPath.io.toIntPreg 265 dataPath.io.fromVfWb := wbDataPath.io.toVfPreg 266 dataPath.io.debugIntRat .foreach(_ := ctrlBlock.io.debug_int_rat.get) 267 dataPath.io.debugFpRat .foreach(_ := ctrlBlock.io.debug_fp_rat.get) 268 dataPath.io.debugVecRat .foreach(_ := ctrlBlock.io.debug_vec_rat.get) 269 dataPath.io.debugVconfigRat.foreach(_ := ctrlBlock.io.debug_vconfig_rat.get) 270 271 bypassNetwork.io.fromDataPath.int <> dataPath.io.toIntExu 272 bypassNetwork.io.fromDataPath.vf <> dataPath.io.toFpExu 273 bypassNetwork.io.fromDataPath.mem <> dataPath.io.toMemExu 274 bypassNetwork.io.fromDataPath.immInfo := dataPath.io.og1ImmInfo 275 bypassNetwork.io.fromExus.connectExuOutput(_.int)(intExuBlock.io.out) 276 bypassNetwork.io.fromExus.connectExuOutput(_.vf)(vfExuBlock.io.out) 277 278 require(bypassNetwork.io.fromExus.mem.flatten.size == io.mem.writeBack.size, 279 s"bypassNetwork.io.fromExus.mem.flatten.size(${bypassNetwork.io.fromExus.mem.flatten.size}: ${bypassNetwork.io.fromExus.mem.map(_.size)}, " + 280 s"io.mem.writeback(${io.mem.writeBack.size})" 281 ) 282 bypassNetwork.io.fromExus.mem.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 283 sink.valid := source.valid 284 sink.bits.pdest := source.bits.uop.pdest 285 sink.bits.data := source.bits.data 286 } 287 288 289 intExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 290 for (i <- 0 until intExuBlock.io.in.length) { 291 for (j <- 0 until intExuBlock.io.in(i).length) { 292 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.int(i)(j).bits.loadDependency, io.mem.ldCancel) 293 NewPipelineConnect( 294 bypassNetwork.io.toExus.int(i)(j), intExuBlock.io.in(i)(j), intExuBlock.io.in(i)(j).fire, 295 Mux( 296 bypassNetwork.io.toExus.int(i)(j).fire, 297 bypassNetwork.io.toExus.int(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 298 intExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 299 ), 300 Option("intExuBlock2bypassNetwork") 301 ) 302 } 303 } 304 305 pcTargetMem.io.fromFrontendFtq := io.frontend.fromFtq 306 pcTargetMem.io.fromDataPathFtq := bypassNetwork.io.toExus.int.flatten.filter(_.bits.params.needTarget).map(_.bits.ftqIdx.get).toSeq 307 intExuBlock.io.in.flatten.filter(_.bits.params.needTarget).map(_.bits.predictInfo.get.target).zipWithIndex.foreach { 308 case (sink, i) => 309 sink := pcTargetMem.io.toExus(i) 310 } 311 pcTargetMem.io.pcToDataPath <> dataPath.io.pcFromPcTargetMem 312 private val csrio = intExuBlock.io.csrio.get 313 csrio.hartId := io.fromTop.hartId 314 csrio.fpu.fflags := ctrlBlock.io.robio.csr.fflags 315 csrio.fpu.isIllegal := false.B // Todo: remove it 316 csrio.fpu.dirty_fs := ctrlBlock.io.robio.csr.dirty_fs 317 csrio.vpu <> 0.U.asTypeOf(csrio.vpu) // Todo 318 319// val debugVconfig = dataPath.io.debugVconfig.get.asTypeOf(new VConfig) 320// val debugVtype = VType.toVtypeStruct(debugVconfig.vtype).asUInt 321// val debugVl = debugVconfig.vl 322 csrio.vpu.set_vxsat := ctrlBlock.io.robio.csr.vxsat 323 csrio.vpu.set_vstart.valid := ctrlBlock.io.robio.csr.vstart.valid 324 csrio.vpu.set_vstart.bits := ctrlBlock.io.robio.csr.vstart.bits 325 csrio.vpu.set_vtype.valid := ctrlBlock.io.robio.csr.vcsrFlag 326 //Todo here need change design 327 csrio.vpu.set_vtype.bits := 0.U//ZeroExt(debugVtype, XLEN) 328 csrio.vpu.set_vl.valid := ctrlBlock.io.robio.csr.vcsrFlag 329 csrio.vpu.set_vl.bits := 0.U//ZeroExt(debugVl, XLEN) 330 csrio.exception := ctrlBlock.io.robio.exception 331 csrio.memExceptionVAddr := io.mem.exceptionVAddr 332 csrio.externalInterrupt := io.fromTop.externalInterrupt 333 csrio.distributedUpdate(0) := io.mem.csrDistributedUpdate 334 csrio.distributedUpdate(1) := io.frontendCsrDistributedUpdate 335 csrio.perf <> io.perf 336 csrio.perf.retiredInstr <> ctrlBlock.io.robio.csr.perfinfo.retiredInstr 337 csrio.perf.ctrlInfo <> ctrlBlock.io.perfInfo.ctrlInfo 338 csrio.perf.perfEventsCtrl <> ctrlBlock.getPerf 339 private val fenceio = intExuBlock.io.fenceio.get 340 io.fenceio <> fenceio 341 fenceio.disableSfence := csrio.disableSfence 342 343 vfExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 344 for (i <- 0 until vfExuBlock.io.in.size) { 345 for (j <- 0 until vfExuBlock.io.in(i).size) { 346 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.vf(i)(j).bits.loadDependency, io.mem.ldCancel) 347 NewPipelineConnect( 348 bypassNetwork.io.toExus.vf(i)(j), vfExuBlock.io.in(i)(j), vfExuBlock.io.in(i)(j).fire, 349 Mux( 350 bypassNetwork.io.toExus.vf(i)(j).fire, 351 bypassNetwork.io.toExus.vf(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 352 vfExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 353 ), 354 Option("vfExuBlock2bypassNetwork") 355 ) 356 357 vfExuBlock.io.in(i)(j).bits.vpu.foreach(_.vstart := csrio.vpu.vstart) 358 } 359 } 360 361 intExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 362 vfExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 363 364 wbDataPath.io.flush := ctrlBlock.io.redirect 365 wbDataPath.io.oldVdDataFromDataPath := dataPath.io.vldReadPort.data 366 wbDataPath.io.fromTop.hartId := io.fromTop.hartId 367 wbDataPath.io.fromIntExu <> intExuBlock.io.out 368 wbDataPath.io.fromVfExu <> vfExuBlock.io.out 369 wbDataPath.io.fromMemExu.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 370 sink.valid := source.valid 371 source.ready := sink.ready 372 sink.bits.data := source.bits.data 373 sink.bits.pdest := source.bits.uop.pdest 374 sink.bits.robIdx := source.bits.uop.robIdx 375 sink.bits.intWen.foreach(_ := source.bits.uop.rfWen) 376 sink.bits.fpWen.foreach(_ := source.bits.uop.fpWen) 377 sink.bits.vecWen.foreach(_ := source.bits.uop.vecWen) 378 sink.bits.exceptionVec.foreach(_ := source.bits.uop.exceptionVec) 379 sink.bits.flushPipe.foreach(_ := source.bits.uop.flushPipe) 380 sink.bits.replay.foreach(_ := source.bits.uop.replayInst) 381 sink.bits.debug := source.bits.debug 382 sink.bits.debugInfo := source.bits.uop.debugInfo 383 sink.bits.lqIdx.foreach(_ := source.bits.uop.lqIdx) 384 sink.bits.sqIdx.foreach(_ := source.bits.uop.sqIdx) 385 sink.bits.predecodeInfo.foreach(_ := source.bits.uop.preDecodeInfo) 386 sink.bits.vls.foreach(x => { 387 x.vdIdx := source.bits.vdIdx.get 388 x.vdIdxInField := source.bits.vdIdxInField.get 389 x.vpu := source.bits.uop.vpu 390 x.oldVdPsrc := source.bits.uop.psrc(2) 391 x.isIndexed := VlduType.isIndexed(source.bits.uop.fuOpType) 392 x.isMasked := VlduType.isMasked(source.bits.uop.fuOpType) 393 }) 394 sink.bits.trigger.foreach(_ := source.bits.uop.trigger) 395 } 396 397 // to mem 398 private val memIssueParams = params.memSchdParams.get.issueBlockParams 399 private val memExuBlocksHasLDU = memIssueParams.map(_.exuBlockParams.map(x => x.hasLoadFu || x.hasHyldaFu)) 400 println(s"[Backend] memExuBlocksHasLDU: $memExuBlocksHasLDU") 401 402 private val toMem = Wire(bypassNetwork.io.toExus.mem.cloneType) 403 for (i <- toMem.indices) { 404 for (j <- toMem(i).indices) { 405 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.mem(i)(j).bits.loadDependency, io.mem.ldCancel) 406 val issueTimeout = 407 if (memExuBlocksHasLDU(i)(j)) 408 Counter(0 until 16, toMem(i)(j).valid && !toMem(i)(j).fire, bypassNetwork.io.toExus.mem(i)(j).fire)._2 409 else 410 false.B 411 412 if (memScheduler.io.loadFinalIssueResp(i).nonEmpty && memExuBlocksHasLDU(i)(j)) { 413 memScheduler.io.loadFinalIssueResp(i)(j).valid := issueTimeout 414 memScheduler.io.loadFinalIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType 415 memScheduler.io.loadFinalIssueResp(i)(j).bits.resp := RespType.block 416 memScheduler.io.loadFinalIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx 417 memScheduler.io.loadFinalIssueResp(i)(j).bits.uopIdx.foreach(_ := toMem(i)(j).bits.vpu.get.vuopIdx) 418 } 419 420 NewPipelineConnect( 421 bypassNetwork.io.toExus.mem(i)(j), toMem(i)(j), toMem(i)(j).fire, 422 Mux( 423 bypassNetwork.io.toExus.mem(i)(j).fire, 424 bypassNetwork.io.toExus.mem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 425 toMem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || issueTimeout 426 ), 427 Option("bypassNetwork2toMemExus") 428 ) 429 430 if (memScheduler.io.memAddrIssueResp(i).nonEmpty && memExuBlocksHasLDU(i)(j)) { 431 memScheduler.io.memAddrIssueResp(i)(j).valid := toMem(i)(j).fire && FuType.isLoad(toMem(i)(j).bits.fuType) 432 memScheduler.io.memAddrIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType 433 memScheduler.io.memAddrIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx 434 memScheduler.io.memAddrIssueResp(i)(j).bits.resp := RespType.success // for load inst, firing at toMem means issuing successfully 435 } 436 } 437 } 438 439 io.mem.redirect := ctrlBlock.io.redirect 440 io.mem.issueUops.zip(toMem.flatten).foreach { case (sink, source) => 441 val enableMdp = Constantin.createRecord("EnableMdp", true.B)(0) 442 sink.valid := source.valid 443 source.ready := sink.ready 444 sink.bits.iqIdx := source.bits.iqIdx 445 sink.bits.isFirstIssue := source.bits.isFirstIssue 446 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 447 sink.bits.src := 0.U.asTypeOf(sink.bits.src) 448 sink.bits.src.zip(source.bits.src).foreach { case (l, r) => l := r} 449 sink.bits.uop.fuType := source.bits.fuType 450 sink.bits.uop.fuOpType := source.bits.fuOpType 451 sink.bits.uop.imm := source.bits.imm 452 sink.bits.uop.robIdx := source.bits.robIdx 453 sink.bits.uop.pdest := source.bits.pdest 454 sink.bits.uop.rfWen := source.bits.rfWen.getOrElse(false.B) 455 sink.bits.uop.fpWen := source.bits.fpWen.getOrElse(false.B) 456 sink.bits.uop.vecWen := source.bits.vecWen.getOrElse(false.B) 457 sink.bits.uop.flushPipe := source.bits.flushPipe.getOrElse(false.B) 458 sink.bits.uop.pc := source.bits.pc.getOrElse(0.U) 459 sink.bits.uop.loadWaitBit := Mux(enableMdp, source.bits.loadWaitBit.getOrElse(false.B), false.B) 460 sink.bits.uop.waitForRobIdx := Mux(enableMdp, source.bits.waitForRobIdx.getOrElse(0.U.asTypeOf(new RobPtr)), 0.U.asTypeOf(new RobPtr)) 461 sink.bits.uop.storeSetHit := Mux(enableMdp, source.bits.storeSetHit.getOrElse(false.B), false.B) 462 sink.bits.uop.loadWaitStrict := Mux(enableMdp, source.bits.loadWaitStrict.getOrElse(false.B), false.B) 463 sink.bits.uop.ssid := Mux(enableMdp, source.bits.ssid.getOrElse(0.U(SSIDWidth.W)), 0.U(SSIDWidth.W)) 464 sink.bits.uop.lqIdx := source.bits.lqIdx.getOrElse(0.U.asTypeOf(new LqPtr)) 465 sink.bits.uop.sqIdx := source.bits.sqIdx.getOrElse(0.U.asTypeOf(new SqPtr)) 466 sink.bits.uop.ftqPtr := source.bits.ftqIdx.getOrElse(0.U.asTypeOf(new FtqPtr)) 467 sink.bits.uop.ftqOffset := source.bits.ftqOffset.getOrElse(0.U) 468 sink.bits.uop.debugInfo := source.bits.perfDebugInfo 469 sink.bits.uop.vpu := source.bits.vpu.getOrElse(0.U.asTypeOf(new VPUCtrlSignals)) 470 sink.bits.uop.preDecodeInfo := source.bits.preDecode.getOrElse(0.U.asTypeOf(new PreDecodeInfo)) 471 } 472 io.mem.loadFastMatch := memScheduler.io.toMem.get.loadFastMatch.map(_.fastMatch) 473 io.mem.loadFastImm := memScheduler.io.toMem.get.loadFastMatch.map(_.fastImm) 474 io.mem.tlbCsr := csrio.tlb 475 io.mem.csrCtrl := csrio.customCtrl 476 io.mem.sfence := fenceio.sfence 477 io.mem.isStoreException := CommitType.lsInstIsStore(ctrlBlock.io.robio.exception.bits.commitType) 478 io.mem.isVlsException := ctrlBlock.io.robio.exception.bits.vls 479 require(io.mem.loadPcRead.size == params.LduCnt) 480 io.mem.loadPcRead.zipWithIndex.foreach { case (loadPcRead, i) => 481 loadPcRead := ctrlBlock.io.memLdPcRead(i).data 482 ctrlBlock.io.memLdPcRead(i).ptr := io.mem.issueLda(i).bits.uop.ftqPtr 483 ctrlBlock.io.memLdPcRead(i).offset := io.mem.issueLda(i).bits.uop.ftqOffset 484 } 485 486 io.mem.storePcRead.zipWithIndex.foreach { case (storePcRead, i) => 487 storePcRead := ctrlBlock.io.memStPcRead(i).data 488 ctrlBlock.io.memStPcRead(i).ptr := io.mem.issueSta(i).bits.uop.ftqPtr 489 ctrlBlock.io.memStPcRead(i).offset := io.mem.issueSta(i).bits.uop.ftqOffset 490 } 491 492 io.mem.hyuPcRead.zipWithIndex.foreach( { case (hyuPcRead, i) => 493 hyuPcRead := ctrlBlock.io.memHyPcRead(i).data 494 ctrlBlock.io.memHyPcRead(i).ptr := io.mem.issueHylda(i).bits.uop.ftqPtr 495 ctrlBlock.io.memHyPcRead(i).offset := io.mem.issueHylda(i).bits.uop.ftqOffset 496 }) 497 498 ctrlBlock.io.robio.robHeadLsIssue := io.mem.issueUops.map(deq => deq.fire && deq.bits.uop.robIdx === ctrlBlock.io.robio.robDeqPtr).reduce(_ || _) 499 500 // mem io 501 io.mem.lsqEnqIO <> memScheduler.io.memIO.get.lsqEnqIO 502 io.mem.robLsqIO <> ctrlBlock.io.robio.lsq 503 504 io.frontendSfence := fenceio.sfence 505 io.frontendTlbCsr := csrio.tlb 506 io.frontendCsrCtrl := csrio.customCtrl 507 508 io.tlb <> csrio.tlb 509 510 io.csrCustomCtrl := csrio.customCtrl 511 512 io.toTop.cpuHalted := false.B // TODO: implement cpu halt 513 514 io.debugTopDown.fromRob := ctrlBlock.io.debugTopDown.fromRob 515 ctrlBlock.io.debugTopDown.fromCore := io.debugTopDown.fromCore 516 517 io.debugRolling := ctrlBlock.io.debugRolling 518 519 if(backendParams.debugEn) { 520 dontTouch(memScheduler.io) 521 dontTouch(dataPath.io.toMemExu) 522 dontTouch(wbDataPath.io.fromMemExu) 523 } 524} 525 526class BackendMemIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 527 // Since fast load replay always use load unit 0, Backend flips two load port to avoid conflicts 528 val flippedLda = true 529 // params alias 530 private val LoadQueueSize = VirtualLoadQueueSize 531 // In/Out // Todo: split it into one-direction bundle 532 val lsqEnqIO = Flipped(new LsqEnqIO) 533 val robLsqIO = new RobLsqIO 534 val ldaIqFeedback = Vec(params.LduCnt, Flipped(new MemRSFeedbackIO)) 535 val staIqFeedback = Vec(params.StaCnt, Flipped(new MemRSFeedbackIO)) 536 val hyuIqFeedback = Vec(params.HyuCnt, Flipped(new MemRSFeedbackIO)) 537 val ldCancel = Vec(params.LdExuCnt, Flipped(new LoadCancelIO)) 538 val wakeup = Vec(params.LdExuCnt, Flipped(Valid(new DynInst))) 539 val loadPcRead = Vec(params.LduCnt, Output(UInt(VAddrBits.W))) 540 val storePcRead = Vec(params.StaCnt, Output(UInt(VAddrBits.W))) 541 val hyuPcRead = Vec(params.HyuCnt, Output(UInt(VAddrBits.W))) 542 // Input 543 val writebackLda = Vec(params.LduCnt, Flipped(DecoupledIO(new MemExuOutput))) 544 val writebackSta = Vec(params.StaCnt, Flipped(DecoupledIO(new MemExuOutput))) 545 val writebackStd = Vec(params.StdCnt, Flipped(DecoupledIO(new MemExuOutput))) 546 val writebackHyuLda = Vec(params.HyuCnt, Flipped(DecoupledIO(new MemExuOutput))) 547 val writebackHyuSta = Vec(params.HyuCnt, Flipped(DecoupledIO(new MemExuOutput))) 548 val writebackVldu = Vec(params.VlduCnt, Flipped(DecoupledIO(new MemExuOutput(true)))) 549 550 val s3_delayed_load_error = Input(Vec(LoadPipelineWidth, Bool())) 551 val stIn = Input(Vec(params.StaExuCnt, ValidIO(new DynInst()))) 552 val memoryViolation = Flipped(ValidIO(new Redirect)) 553 val exceptionVAddr = Input(UInt(VAddrBits.W)) 554 val sqDeq = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) 555 val lqDeq = Input(UInt(log2Up(CommitWidth + 1).W)) 556 val sqDeqPtr = Input(new SqPtr) 557 val lqDeqPtr = Input(new LqPtr) 558 559 val lqCancelCnt = Input(UInt(log2Up(VirtualLoadQueueSize + 1).W)) 560 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 561 562 val lqCanAccept = Input(Bool()) 563 val sqCanAccept = Input(Bool()) 564 565 val otherFastWakeup = Flipped(Vec(params.LduCnt + params.HyuCnt, ValidIO(new DynInst))) 566 val stIssuePtr = Input(new SqPtr()) 567 568 val csrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 569 570 val debugLS = Flipped(Output(new DebugLSIO)) 571 572 val lsTopdownInfo = Vec(params.LduCnt + params.HyuCnt, Flipped(Output(new LsTopdownInfo))) 573 // Output 574 val redirect = ValidIO(new Redirect) // rob flush MemBlock 575 val issueLda = MixedVec(Seq.fill(params.LduCnt)(DecoupledIO(new MemExuInput()))) 576 val issueSta = MixedVec(Seq.fill(params.StaCnt)(DecoupledIO(new MemExuInput()))) 577 val issueStd = MixedVec(Seq.fill(params.StdCnt)(DecoupledIO(new MemExuInput()))) 578 val issueHylda = MixedVec(Seq.fill(params.HyuCnt)(DecoupledIO(new MemExuInput()))) 579 val issueHysta = MixedVec(Seq.fill(params.HyuCnt)(DecoupledIO(new MemExuInput()))) 580 val issueVldu = MixedVec(Seq.fill(params.VlduCnt)(DecoupledIO(new MemExuInput(true)))) 581 582 val loadFastMatch = Vec(params.LduCnt, Output(UInt(params.LduCnt.W))) 583 val loadFastImm = Vec(params.LduCnt, Output(UInt(12.W))) // Imm_I 584 585 val tlbCsr = Output(new TlbCsrBundle) 586 val csrCtrl = Output(new CustomCSRCtrlIO) 587 val sfence = Output(new SfenceBundle) 588 val isStoreException = Output(Bool()) 589 val isVlsException = Output(Bool()) 590 591 // ATTENTION: The issue ports' sequence order should be the same as IQs' deq config 592 private [backend] def issueUops: Seq[DecoupledIO[MemExuInput]] = { 593 issueSta ++ 594 issueHylda ++ issueHysta ++ 595 issueLda ++ 596 issueVldu ++ 597 issueStd 598 }.toSeq 599 600 // ATTENTION: The writeback ports' sequence order should be the same as IQs' deq config 601 private [backend] def writeBack: Seq[DecoupledIO[MemExuOutput]] = { 602 writebackSta ++ 603 writebackHyuLda ++ writebackHyuSta ++ 604 writebackLda ++ 605 writebackVldu ++ 606 writebackStd 607 } 608} 609 610class BackendIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 611 val fromTop = new Bundle { 612 val hartId = Input(UInt(8.W)) 613 val externalInterrupt = new ExternalInterruptIO 614 } 615 616 val toTop = new Bundle { 617 val cpuHalted = Output(Bool()) 618 } 619 620 val fenceio = new FenceIO 621 // Todo: merge these bundles into BackendFrontendIO 622 val frontend = Flipped(new FrontendToCtrlIO) 623 val frontendSfence = Output(new SfenceBundle) 624 val frontendCsrCtrl = Output(new CustomCSRCtrlIO) 625 val frontendTlbCsr = Output(new TlbCsrBundle) 626 // distributed csr write 627 val frontendCsrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 628 629 val mem = new BackendMemIO 630 631 val perf = Input(new PerfCounterIO) 632 633 val tlb = Output(new TlbCsrBundle) 634 635 val csrCustomCtrl = Output(new CustomCSRCtrlIO) 636 637 val debugTopDown = new Bundle { 638 val fromRob = new RobCoreTopDownIO 639 val fromCore = new CoreDispatchTopDownIO 640 } 641 val debugRolling = new RobDebugRollingIO 642} 643