1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15* 16* 17* Acknowledgement 18* 19* This implementation is inspired by several key papers: 20* [1] Robert. M. Tomasulo. "[An efficient algorithm for exploiting multiple arithmetic units.] 21* (https://doi.org/10.1147/rd.111.0025)" IBM Journal of Research and Development (IBMJ) 11.1: 25-33. 1967. 22***************************************************************************************/ 23 24package xiangshan.backend 25 26import org.chipsalliance.cde.config.Parameters 27import chisel3._ 28import chisel3.util._ 29import device.MsiInfoBundle 30import difftest._ 31import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 32import system.HasSoCParameter 33import utility._ 34import xiangshan._ 35import xiangshan.backend.Bundles.{DynInst, IssueQueueIQWakeUpBundle, LoadShouldCancel, MemExuInput, MemExuOutput, VPUCtrlSignals} 36import xiangshan.backend.ctrlblock.{DebugLSIO, LsTopdownInfo} 37import xiangshan.backend.datapath.DataConfig.{IntData, VecData, FpData} 38import xiangshan.backend.datapath.RdConfig.{IntRD, VfRD} 39import xiangshan.backend.datapath.WbConfig._ 40import xiangshan.backend.datapath.DataConfig._ 41import xiangshan.backend.datapath._ 42import xiangshan.backend.dispatch.CoreDispatchTopDownIO 43import xiangshan.backend.exu.ExuBlock 44import xiangshan.backend.fu.vector.Bundles.{VConfig, VType} 45import xiangshan.backend.fu.{FenceIO, FenceToSbuffer, FuConfig, FuType, PFEvent, PerfCounterIO} 46import xiangshan.backend.issue.EntryBundles._ 47import xiangshan.backend.issue.{CancelNetwork, Scheduler, SchedulerArithImp, SchedulerImpBase, SchedulerMemImp} 48import xiangshan.backend.rob.{RobCoreTopDownIO, RobDebugRollingIO, RobLsqIO, RobPtr} 49import xiangshan.backend.trace.TraceCoreInterface 50import xiangshan.frontend.{FtqPtr, FtqRead, PreDecodeInfo} 51import xiangshan.mem.{LqPtr, LsqEnqIO, SqPtr} 52 53import scala.collection.mutable 54 55class Backend(val params: BackendParams)(implicit p: Parameters) extends LazyModule 56 with HasXSParameter { 57 override def shouldBeInlined: Boolean = false 58 val inner = LazyModule(new BackendInlined(params)) 59 lazy val module = new BackendImp(this) 60} 61 62class BackendImp(wrapper: Backend)(implicit p: Parameters) extends LazyModuleImp(wrapper) { 63 val io = IO(new BackendIO()(p, wrapper.params)) 64 io <> wrapper.inner.module.io 65 if (p(DebugOptionsKey).ResetGen) { 66 ResetGen(ResetGenNode(Seq(ModuleNode(wrapper.inner.module))), reset, sim = false) 67 } 68} 69 70class BackendInlined(val params: BackendParams)(implicit p: Parameters) extends LazyModule 71 with HasXSParameter { 72 73 override def shouldBeInlined: Boolean = true 74 75 // check read & write port config 76 params.configChecks 77 78 /* Only update the idx in mem-scheduler here 79 * Idx in other schedulers can be updated the same way if needed 80 * 81 * Also note that we filter out the 'stData issue-queues' when counting 82 */ 83 for ((ibp, idx) <- params.memSchdParams.get.issueBlockParams.filter(iq => iq.StdCnt == 0).zipWithIndex) { 84 ibp.updateIdx(idx) 85 } 86 87 println(params.iqWakeUpParams) 88 89 for ((schdCfg, i) <- params.allSchdParams.zipWithIndex) { 90 schdCfg.bindBackendParam(params) 91 } 92 93 for ((iqCfg, i) <- params.allIssueParams.zipWithIndex) { 94 iqCfg.bindBackendParam(params) 95 } 96 97 for ((exuCfg, i) <- params.allExuParams.zipWithIndex) { 98 exuCfg.bindBackendParam(params) 99 exuCfg.updateIQWakeUpConfigs(params.iqWakeUpParams) 100 exuCfg.updateExuIdx(i) 101 } 102 103 println("[Backend] ExuConfigs:") 104 for (exuCfg <- params.allExuParams) { 105 val fuConfigs = exuCfg.fuConfigs 106 val wbPortConfigs = exuCfg.wbPortConfigs 107 val immType = exuCfg.immType 108 109 println("[Backend] " + 110 s"${exuCfg.name}: " + 111 (if (exuCfg.fakeUnit) "fake, " else "") + 112 (if (exuCfg.hasLoadFu || exuCfg.hasHyldaFu) s"LdExuIdx(${backendParams.getLdExuIdx(exuCfg)})" else "") + 113 s"${fuConfigs.map(_.name).mkString("fu(s): {", ",", "}")}, " + 114 s"${wbPortConfigs.mkString("wb: {", ",", "}")}, " + 115 s"${immType.map(SelImm.mkString(_)).mkString("imm: {", ",", "}")}, " + 116 s"latMax(${exuCfg.latencyValMax}), ${exuCfg.fuLatancySet.mkString("lat: {", ",", "}")}, " + 117 s"srcReg(${exuCfg.numRegSrc})" 118 ) 119 require( 120 wbPortConfigs.collectFirst { case x: IntWB => x }.nonEmpty == 121 fuConfigs.map(_.writeIntRf).reduce(_ || _), 122 s"${exuCfg.name} int wb port has no priority" 123 ) 124 require( 125 wbPortConfigs.collectFirst { case x: FpWB => x }.nonEmpty == 126 fuConfigs.map(x => x.writeFpRf).reduce(_ || _), 127 s"${exuCfg.name} fp wb port has no priority" 128 ) 129 require( 130 wbPortConfigs.collectFirst { case x: VfWB => x }.nonEmpty == 131 fuConfigs.map(x => x.writeVecRf).reduce(_ || _), 132 s"${exuCfg.name} vec wb port has no priority" 133 ) 134 } 135 136 println(s"[Backend] all fu configs") 137 for (cfg <- FuConfig.allConfigs) { 138 println(s"[Backend] $cfg") 139 } 140 141 println(s"[Backend] Int RdConfigs: ExuName(Priority)") 142 for ((port, seq) <- params.getRdPortParams(IntData())) { 143 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 144 } 145 146 println(s"[Backend] Int WbConfigs: ExuName(Priority)") 147 for ((port, seq) <- params.getWbPortParams(IntData())) { 148 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 149 } 150 151 println(s"[Backend] Fp RdConfigs: ExuName(Priority)") 152 for ((port, seq) <- params.getRdPortParams(FpData())) { 153 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 154 } 155 156 println(s"[Backend] Fp WbConfigs: ExuName(Priority)") 157 for ((port, seq) <- params.getWbPortParams(FpData())) { 158 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 159 } 160 161 println(s"[Backend] Vf RdConfigs: ExuName(Priority)") 162 for ((port, seq) <- params.getRdPortParams(VecData())) { 163 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 164 } 165 166 println(s"[Backend] Vf WbConfigs: ExuName(Priority)") 167 for ((port, seq) <- params.getWbPortParams(VecData())) { 168 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 169 } 170 171 println(s"[Backend] Dispatch Configs:") 172 println(s"[Backend] Load IQ enq width(${params.numLoadDp}), Store IQ enq width(${params.numStoreDp})") 173 println(s"[Backend] Load DP width(${LSQLdEnqWidth}), Store DP width(${LSQStEnqWidth})") 174 175 params.updateCopyPdestInfo 176 println(s"[Backend] copyPdestInfo ${params.copyPdestInfo}") 177 params.allExuParams.map(_.copyNum) 178 val ctrlBlock = LazyModule(new CtrlBlock(params)) 179 val pcTargetMem = LazyModule(new PcTargetMem(params)) 180 val intScheduler = params.intSchdParams.map(x => LazyModule(new Scheduler(x))) 181 val fpScheduler = params.fpSchdParams.map(x => LazyModule(new Scheduler(x))) 182 val vfScheduler = params.vfSchdParams.map(x => LazyModule(new Scheduler(x))) 183 val memScheduler = params.memSchdParams.map(x => LazyModule(new Scheduler(x))) 184 val dataPath = LazyModule(new DataPath(params)) 185 val intExuBlock = params.intSchdParams.map(x => LazyModule(new ExuBlock(x))) 186 val fpExuBlock = params.fpSchdParams.map(x => LazyModule(new ExuBlock(x))) 187 val vfExuBlock = params.vfSchdParams.map(x => LazyModule(new ExuBlock(x))) 188 val wbFuBusyTable = LazyModule(new WbFuBusyTable(params)) 189 190 lazy val module = new BackendInlinedImp(this) 191} 192 193class BackendInlinedImp(override val wrapper: BackendInlined)(implicit p: Parameters) extends LazyModuleImp(wrapper) 194 with HasXSParameter 195 with HasPerfEvents 196 with HasCriticalErrors { 197 implicit private val params: BackendParams = wrapper.params 198 199 val io = IO(new BackendIO()(p, wrapper.params)) 200 201 private val ctrlBlock = wrapper.ctrlBlock.module 202 private val pcTargetMem = wrapper.pcTargetMem.module 203 private val intScheduler: SchedulerImpBase = wrapper.intScheduler.get.module 204 private val fpScheduler = wrapper.fpScheduler.get.module 205 private val vfScheduler = wrapper.vfScheduler.get.module 206 private val memScheduler = wrapper.memScheduler.get.module 207 private val dataPath = wrapper.dataPath.module 208 private val intExuBlock = wrapper.intExuBlock.get.module 209 private val fpExuBlock = wrapper.fpExuBlock.get.module 210 private val vfExuBlock = wrapper.vfExuBlock.get.module 211 private val og2ForVector = Module(new Og2ForVector(params)) 212 private val bypassNetwork = Module(new BypassNetwork) 213 private val wbDataPath = Module(new WbDataPath(params)) 214 private val wbFuBusyTable = wrapper.wbFuBusyTable.module 215 private val vecExcpMod = Module(new VecExcpDataMergeModule) 216 217 private val iqWakeUpMappedBundle: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = ( 218 intScheduler.io.toSchedulers.wakeupVec ++ 219 fpScheduler.io.toSchedulers.wakeupVec ++ 220 vfScheduler.io.toSchedulers.wakeupVec ++ 221 memScheduler.io.toSchedulers.wakeupVec 222 ).map(x => (x.bits.exuIdx, x)).toMap 223 224 println(s"[Backend] iq wake up keys: ${iqWakeUpMappedBundle.keys}") 225 226 wbFuBusyTable.io.in.intSchdBusyTable := intScheduler.io.wbFuBusyTable 227 wbFuBusyTable.io.in.fpSchdBusyTable := fpScheduler.io.wbFuBusyTable 228 wbFuBusyTable.io.in.vfSchdBusyTable := vfScheduler.io.wbFuBusyTable 229 wbFuBusyTable.io.in.memSchdBusyTable := memScheduler.io.wbFuBusyTable 230 intScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.intRespRead 231 fpScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.fpRespRead 232 vfScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.vfRespRead 233 memScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.memRespRead 234 dataPath.io.wbConfictRead := wbFuBusyTable.io.out.wbConflictRead 235 236 private val og1Cancel = dataPath.io.og1Cancel 237 private val og0Cancel = dataPath.io.og0Cancel 238 private val vlFromIntIsZero = intExuBlock.io.vlIsZero.get 239 private val vlFromIntIsVlmax = intExuBlock.io.vlIsVlmax.get 240 private val vlFromVfIsZero = vfExuBlock.io.vlIsZero.get 241 private val vlFromVfIsVlmax = vfExuBlock.io.vlIsVlmax.get 242 243 private val backendCriticalError = Wire(Bool()) 244 245 ctrlBlock.io.intIQValidNumVec := intScheduler.io.intIQValidNumVec 246 ctrlBlock.io.fpIQValidNumVec := fpScheduler.io.fpIQValidNumVec 247 ctrlBlock.io.fromTop.hartId := io.fromTop.hartId 248 ctrlBlock.io.frontend <> io.frontend 249 ctrlBlock.io.fromCSR.toDecode := intExuBlock.io.csrToDecode.get 250 ctrlBlock.io.fromCSR.traceCSR := intExuBlock.io.csrio.get.traceCSR 251 ctrlBlock.io.fromWB.wbData <> wbDataPath.io.toCtrlBlock.writeback 252 ctrlBlock.io.fromMem.stIn <> io.mem.stIn 253 ctrlBlock.io.fromMem.violation <> io.mem.memoryViolation 254 ctrlBlock.io.lqCanAccept := io.mem.lqCanAccept 255 ctrlBlock.io.sqCanAccept := io.mem.sqCanAccept 256 ctrlBlock.io.csrCtrl <> intExuBlock.io.csrio.get.customCtrl 257 ctrlBlock.io.robio.csr.intrBitSet := intExuBlock.io.csrio.get.interrupt 258 ctrlBlock.io.robio.csr.trapTarget := intExuBlock.io.csrio.get.trapTarget 259 ctrlBlock.io.robio.csr.isXRet := intExuBlock.io.csrio.get.isXRet 260 ctrlBlock.io.robio.csr.wfiEvent := intExuBlock.io.csrio.get.wfi_event 261 ctrlBlock.io.robio.csr.criticalErrorState := intExuBlock.io.csrio.get.criticalErrorState 262 ctrlBlock.io.robio.lsq <> io.mem.robLsqIO 263 ctrlBlock.io.robio.lsTopdownInfo <> io.mem.lsTopdownInfo 264 ctrlBlock.io.robio.debug_ls <> io.mem.debugLS 265 ctrlBlock.io.debugEnqLsq.canAccept := io.mem.lsqEnqIO.canAccept 266 ctrlBlock.io.debugEnqLsq.resp := io.mem.lsqEnqIO.resp 267 ctrlBlock.io.debugEnqLsq.req := memScheduler.io.memIO.get.lsqEnqIO.req 268 ctrlBlock.io.debugEnqLsq.needAlloc := memScheduler.io.memIO.get.lsqEnqIO.needAlloc 269 ctrlBlock.io.debugEnqLsq.iqAccept := memScheduler.io.memIO.get.lsqEnqIO.iqAccept 270 ctrlBlock.io.fromVecExcpMod.busy := vecExcpMod.o.status.busy 271 272 intScheduler.io.fromTop.hartId := io.fromTop.hartId 273 intScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 274 intScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 275 intScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.intUops 276 intScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 277 intScheduler.io.fpWriteBack := 0.U.asTypeOf(intScheduler.io.fpWriteBack) 278 intScheduler.io.vfWriteBack := 0.U.asTypeOf(intScheduler.io.vfWriteBack) 279 intScheduler.io.v0WriteBack := 0.U.asTypeOf(intScheduler.io.v0WriteBack) 280 intScheduler.io.vlWriteBack := 0.U.asTypeOf(intScheduler.io.vlWriteBack) 281 intScheduler.io.fromDataPath.resp := dataPath.io.toIntIQ 282 intScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 283 intScheduler.io.fromDataPath.og0Cancel := og0Cancel 284 intScheduler.io.fromDataPath.og1Cancel := og1Cancel 285 intScheduler.io.ldCancel := io.mem.ldCancel 286 intScheduler.io.fromDataPath.replaceRCIdx.get := dataPath.io.toWakeupQueueRCIdx.take(params.getIntExuRCWriteSize) 287 intScheduler.io.vlWriteBackInfo.vlFromIntIsZero := false.B 288 intScheduler.io.vlWriteBackInfo.vlFromIntIsVlmax := false.B 289 intScheduler.io.vlWriteBackInfo.vlFromVfIsZero := false.B 290 intScheduler.io.vlWriteBackInfo.vlFromVfIsVlmax := false.B 291 292 fpScheduler.io.fromTop.hartId := io.fromTop.hartId 293 fpScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 294 fpScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 295 fpScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.fpUops 296 fpScheduler.io.intWriteBack := 0.U.asTypeOf(fpScheduler.io.intWriteBack) 297 fpScheduler.io.fpWriteBack := wbDataPath.io.toFpPreg 298 fpScheduler.io.vfWriteBack := 0.U.asTypeOf(fpScheduler.io.vfWriteBack) 299 fpScheduler.io.v0WriteBack := 0.U.asTypeOf(fpScheduler.io.v0WriteBack) 300 fpScheduler.io.vlWriteBack := 0.U.asTypeOf(fpScheduler.io.vlWriteBack) 301 fpScheduler.io.fromDataPath.resp := dataPath.io.toFpIQ 302 fpScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 303 fpScheduler.io.fromDataPath.og0Cancel := og0Cancel 304 fpScheduler.io.fromDataPath.og1Cancel := og1Cancel 305 fpScheduler.io.ldCancel := io.mem.ldCancel 306 fpScheduler.io.vlWriteBackInfo.vlFromIntIsZero := false.B 307 fpScheduler.io.vlWriteBackInfo.vlFromIntIsVlmax := false.B 308 fpScheduler.io.vlWriteBackInfo.vlFromVfIsZero := false.B 309 fpScheduler.io.vlWriteBackInfo.vlFromVfIsVlmax := false.B 310 311 memScheduler.io.fromTop.hartId := io.fromTop.hartId 312 memScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 313 memScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 314 memScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.memUops 315 memScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 316 memScheduler.io.fpWriteBack := wbDataPath.io.toFpPreg 317 memScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 318 memScheduler.io.v0WriteBack := wbDataPath.io.toV0Preg 319 memScheduler.io.vlWriteBack := wbDataPath.io.toVlPreg 320 memScheduler.io.fromMem.get.scommit := io.mem.sqDeq 321 memScheduler.io.fromMem.get.lcommit := io.mem.lqDeq 322 memScheduler.io.fromMem.get.wakeup := io.mem.wakeup 323 memScheduler.io.fromMem.get.sqDeqPtr := io.mem.sqDeqPtr 324 memScheduler.io.fromMem.get.lqDeqPtr := io.mem.lqDeqPtr 325 memScheduler.io.fromMem.get.sqCancelCnt := io.mem.sqCancelCnt 326 memScheduler.io.fromMem.get.lqCancelCnt := io.mem.lqCancelCnt 327 memScheduler.io.fromMem.get.stIssuePtr := io.mem.stIssuePtr 328 require(memScheduler.io.fromMem.get.memWaitUpdateReq.robIdx.length == io.mem.stIn.length) 329 memScheduler.io.fromMem.get.memWaitUpdateReq.robIdx.zip(io.mem.stIn).foreach { case (sink, source) => 330 sink.valid := source.valid 331 sink.bits := source.bits.robIdx 332 } 333 memScheduler.io.fromMem.get.memWaitUpdateReq.sqIdx := DontCare // TODO 334 memScheduler.io.fromDataPath.resp := dataPath.io.toMemIQ 335 memScheduler.io.fromMem.get.ldaFeedback := io.mem.ldaIqFeedback 336 memScheduler.io.fromMem.get.staFeedback := io.mem.staIqFeedback 337 memScheduler.io.fromMem.get.hyuFeedback := io.mem.hyuIqFeedback 338 memScheduler.io.fromMem.get.vstuFeedback := io.mem.vstuIqFeedback 339 memScheduler.io.fromMem.get.vlduFeedback := io.mem.vlduIqFeedback 340 memScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 341 memScheduler.io.fromDataPath.og0Cancel := og0Cancel 342 memScheduler.io.fromDataPath.og1Cancel := og1Cancel 343 memScheduler.io.ldCancel := io.mem.ldCancel 344 memScheduler.io.fromDataPath.replaceRCIdx.get := dataPath.io.toWakeupQueueRCIdx.takeRight(params.getMemExuRCWriteSize) 345 memScheduler.io.vlWriteBackInfo.vlFromIntIsZero := vlFromIntIsZero 346 memScheduler.io.vlWriteBackInfo.vlFromIntIsVlmax := vlFromIntIsVlmax 347 memScheduler.io.vlWriteBackInfo.vlFromVfIsZero := vlFromVfIsZero 348 memScheduler.io.vlWriteBackInfo.vlFromVfIsVlmax := vlFromVfIsVlmax 349 memScheduler.io.fromOg2Resp.get := og2ForVector.io.toMemIQOg2Resp 350 351 vfScheduler.io.fromTop.hartId := io.fromTop.hartId 352 vfScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 353 vfScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 354 vfScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.vfUops 355 vfScheduler.io.intWriteBack := 0.U.asTypeOf(vfScheduler.io.intWriteBack) 356 vfScheduler.io.fpWriteBack := 0.U.asTypeOf(vfScheduler.io.fpWriteBack) 357 vfScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 358 vfScheduler.io.v0WriteBack := wbDataPath.io.toV0Preg 359 vfScheduler.io.vlWriteBack := wbDataPath.io.toVlPreg 360 vfScheduler.io.fromDataPath.resp := dataPath.io.toVfIQ 361 vfScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 362 vfScheduler.io.fromDataPath.og0Cancel := og0Cancel 363 vfScheduler.io.fromDataPath.og1Cancel := og1Cancel 364 vfScheduler.io.ldCancel := io.mem.ldCancel 365 vfScheduler.io.vlWriteBackInfo.vlFromIntIsZero := vlFromIntIsZero 366 vfScheduler.io.vlWriteBackInfo.vlFromIntIsVlmax := vlFromIntIsVlmax 367 vfScheduler.io.vlWriteBackInfo.vlFromVfIsZero := vlFromVfIsZero 368 vfScheduler.io.vlWriteBackInfo.vlFromVfIsVlmax := vlFromVfIsVlmax 369 vfScheduler.io.fromOg2Resp.get := og2ForVector.io.toVfIQOg2Resp 370 371 dataPath.io.hartId := io.fromTop.hartId 372 dataPath.io.flush := ctrlBlock.io.toDataPath.flush 373 374 dataPath.io.fromIntIQ <> intScheduler.io.toDataPathAfterDelay 375 dataPath.io.fromFpIQ <> fpScheduler.io.toDataPathAfterDelay 376 dataPath.io.fromVfIQ <> vfScheduler.io.toDataPathAfterDelay 377 dataPath.io.fromMemIQ <> memScheduler.io.toDataPathAfterDelay 378 379 dataPath.io.ldCancel := io.mem.ldCancel 380 381 println(s"[Backend] wbDataPath.io.toIntPreg: ${wbDataPath.io.toIntPreg.size}, dataPath.io.fromIntWb: ${dataPath.io.fromIntWb.size}") 382 println(s"[Backend] wbDataPath.io.toVfPreg: ${wbDataPath.io.toVfPreg.size}, dataPath.io.fromFpWb: ${dataPath.io.fromVfWb.size}") 383 dataPath.io.fromIntWb := wbDataPath.io.toIntPreg 384 dataPath.io.fromFpWb := wbDataPath.io.toFpPreg 385 dataPath.io.fromVfWb := wbDataPath.io.toVfPreg 386 dataPath.io.fromV0Wb := wbDataPath.io.toV0Preg 387 dataPath.io.fromVlWb := wbDataPath.io.toVlPreg 388 dataPath.io.diffIntRat.foreach(_ := ctrlBlock.io.diff_int_rat.get) 389 dataPath.io.diffFpRat .foreach(_ := ctrlBlock.io.diff_fp_rat.get) 390 dataPath.io.diffVecRat.foreach(_ := ctrlBlock.io.diff_vec_rat.get) 391 dataPath.io.diffV0Rat .foreach(_ := ctrlBlock.io.diff_v0_rat.get) 392 dataPath.io.diffVlRat .foreach(_ := ctrlBlock.io.diff_vl_rat.get) 393 dataPath.io.fromBypassNetwork := bypassNetwork.io.toDataPath 394 dataPath.io.fromVecExcpMod.r := vecExcpMod.o.toVPRF.r 395 dataPath.io.fromVecExcpMod.w := vecExcpMod.o.toVPRF.w 396 397 og2ForVector.io.flush := ctrlBlock.io.toDataPath.flush 398 og2ForVector.io.ldCancel := io.mem.ldCancel 399 og2ForVector.io.fromOg1VfArith <> dataPath.io.toVecExu 400 og2ForVector.io.fromOg1VecMem.zip(dataPath.io.toMemExu.zip(params.memSchdParams.get.issueBlockParams).filter(_._2.needOg2Resp).map(_._1)) 401 .foreach { 402 case (og1Mem, datapathMem) => og1Mem <> datapathMem 403 } 404 og2ForVector.io.fromOg1ImmInfo := dataPath.io.og1ImmInfo.zip(params.allExuParams).filter(_._2.needOg2).map(_._1) 405 406 println(s"[Backend] BypassNetwork OG1 Mem Size: ${bypassNetwork.io.fromDataPath.mem.zip(params.memSchdParams.get.issueBlockParams).filterNot(_._2.needOg2Resp).size}") 407 println(s"[Backend] BypassNetwork OG2 Mem Size: ${bypassNetwork.io.fromDataPath.mem.zip(params.memSchdParams.get.issueBlockParams).filter(_._2.needOg2Resp).size}") 408 println(s"[Backend] bypassNetwork.io.fromDataPath.mem: ${bypassNetwork.io.fromDataPath.mem.size}, dataPath.io.toMemExu: ${dataPath.io.toMemExu.size}") 409 bypassNetwork.io.fromDataPath.int <> dataPath.io.toIntExu 410 bypassNetwork.io.fromDataPath.fp <> dataPath.io.toFpExu 411 bypassNetwork.io.fromDataPath.vf <> og2ForVector.io.toVfArithExu 412 bypassNetwork.io.fromDataPath.mem.lazyZip(params.memSchdParams.get.issueBlockParams).lazyZip(dataPath.io.toMemExu).filterNot(_._2.needOg2Resp) 413 .map(x => (x._1, x._3)).foreach { 414 case (bypassMem, datapathMem) => bypassMem <> datapathMem 415 } 416 bypassNetwork.io.fromDataPath.mem.zip(params.memSchdParams.get.issueBlockParams).filter(_._2.needOg2Resp).map(_._1) 417 .zip(og2ForVector.io.toVecMemExu).foreach { 418 case (bypassMem, og2Mem) => bypassMem <> og2Mem 419 } 420 bypassNetwork.io.fromDataPath.immInfo := dataPath.io.og1ImmInfo 421 bypassNetwork.io.fromDataPath.immInfo.zip(params.allExuParams).filter(_._2.needOg2).map(_._1) 422 .zip(og2ForVector.io.toBypassNetworkImmInfo).foreach { 423 case (immInfo, og2ImmInfo) => immInfo := og2ImmInfo 424 } 425 bypassNetwork.io.fromDataPath.rcData := dataPath.io.toBypassNetworkRCData 426 bypassNetwork.io.fromExus.connectExuOutput(_.int)(intExuBlock.io.out) 427 bypassNetwork.io.fromExus.connectExuOutput(_.fp)(fpExuBlock.io.out) 428 bypassNetwork.io.fromExus.connectExuOutput(_.vf)(vfExuBlock.io.out) 429 430 require(bypassNetwork.io.fromExus.mem.flatten.size == io.mem.writeBack.size, 431 s"bypassNetwork.io.fromExus.mem.flatten.size(${bypassNetwork.io.fromExus.mem.flatten.size}: ${bypassNetwork.io.fromExus.mem.map(_.size)}, " + 432 s"io.mem.writeback(${io.mem.writeBack.size})" 433 ) 434 bypassNetwork.io.fromExus.mem.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 435 sink.valid := source.valid 436 sink.bits.intWen := source.bits.uop.rfWen && source.bits.isFromLoadUnit 437 sink.bits.pdest := source.bits.uop.pdest 438 sink.bits.data := source.bits.data 439 } 440 441 442 intExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 443 for (i <- 0 until intExuBlock.io.in.length) { 444 for (j <- 0 until intExuBlock.io.in(i).length) { 445 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.int(i)(j).bits.loadDependency, io.mem.ldCancel) 446 NewPipelineConnect( 447 bypassNetwork.io.toExus.int(i)(j), intExuBlock.io.in(i)(j), intExuBlock.io.in(i)(j).fire, 448 Mux( 449 bypassNetwork.io.toExus.int(i)(j).fire, 450 bypassNetwork.io.toExus.int(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 451 intExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 452 ), 453 Option("bypassNetwork2intExuBlock") 454 ) 455 } 456 } 457 458 pcTargetMem.io.fromFrontendFtq := io.frontend.fromFtq 459 pcTargetMem.io.toDataPath <> dataPath.io.fromPcTargetMem 460 461 private val csrin = intExuBlock.io.csrin.get 462 csrin.hartId := io.fromTop.hartId 463 csrin.msiInfo.valid := RegNext(io.fromTop.msiInfo.valid) 464 csrin.msiInfo.bits := RegEnable(io.fromTop.msiInfo.bits, io.fromTop.msiInfo.valid) 465 csrin.clintTime.valid := RegNext(io.fromTop.clintTime.valid) 466 csrin.clintTime.bits := RegEnable(io.fromTop.clintTime.bits, io.fromTop.clintTime.valid) 467 csrin.trapInstInfo := ctrlBlock.io.toCSR.trapInstInfo 468 csrin.fromVecExcpMod.busy := vecExcpMod.o.status.busy 469 csrin.criticalErrorState := backendCriticalError 470 471 private val csrio = intExuBlock.io.csrio.get 472 csrio.hartId := io.fromTop.hartId 473 csrio.fpu.fflags := ctrlBlock.io.robio.csr.fflags 474 csrio.fpu.isIllegal := false.B // Todo: remove it 475 csrio.fpu.dirty_fs := ctrlBlock.io.robio.csr.dirty_fs 476 csrio.vpu <> WireDefault(0.U.asTypeOf(csrio.vpu)) // Todo 477 478 val fromIntExuVsetVType = intExuBlock.io.vtype.getOrElse(0.U.asTypeOf((Valid(new VType)))) 479 val fromVfExuVsetVType = vfExuBlock.io.vtype.getOrElse(0.U.asTypeOf((Valid(new VType)))) 480 val fromVsetVType = Mux(fromIntExuVsetVType.valid, fromIntExuVsetVType.bits, fromVfExuVsetVType.bits) 481 val vsetvlVType = RegEnable(fromVsetVType, 0.U.asTypeOf(new VType), fromIntExuVsetVType.valid || fromVfExuVsetVType.valid) 482 ctrlBlock.io.toDecode.vsetvlVType := vsetvlVType 483 484 val commitVType = ctrlBlock.io.robio.commitVType.vtype 485 val hasVsetvl = ctrlBlock.io.robio.commitVType.hasVsetvl 486 val vtype = VType.toVtypeStruct(Mux(hasVsetvl, vsetvlVType, commitVType.bits)).asUInt 487 488 // csr not store the value of vl, so when using difftest we assign the value of vl to debugVl 489 val debugVl_s0 = WireInit(UInt(VlData().dataWidth.W), 0.U) 490 val debugVl_s1 = WireInit(UInt(VlData().dataWidth.W), 0.U) 491 debugVl_s0 := dataPath.io.diffVl.getOrElse(0.U.asTypeOf(UInt(VlData().dataWidth.W))) 492 debugVl_s1 := RegNext(debugVl_s0) 493 csrio.vpu.set_vxsat := ctrlBlock.io.robio.csr.vxsat 494 csrio.vpu.set_vstart.valid := ctrlBlock.io.robio.csr.vstart.valid 495 csrio.vpu.set_vstart.bits := ctrlBlock.io.robio.csr.vstart.bits 496 ctrlBlock.io.toDecode.vstart := csrio.vpu.vstart 497 //Todo here need change design 498 csrio.vpu.set_vtype.valid := commitVType.valid 499 csrio.vpu.set_vtype.bits := ZeroExt(vtype, XLEN) 500 csrio.vpu.vl := ZeroExt(debugVl_s1, XLEN) 501 csrio.vpu.dirty_vs := ctrlBlock.io.robio.csr.dirty_vs 502 csrio.exception := ctrlBlock.io.robio.exception 503 csrio.robDeqPtr := ctrlBlock.io.robio.robDeqPtr 504 csrio.memExceptionVAddr := io.mem.exceptionAddr.vaddr 505 csrio.memExceptionGPAddr := io.mem.exceptionAddr.gpaddr 506 csrio.memExceptionIsForVSnonLeafPTE := io.mem.exceptionAddr.isForVSnonLeafPTE 507 csrio.externalInterrupt := RegNext(io.fromTop.externalInterrupt) 508 csrio.perf <> io.perf 509 csrio.perf.retiredInstr <> ctrlBlock.io.robio.csr.perfinfo.retiredInstr 510 csrio.perf.ctrlInfo <> ctrlBlock.io.perfInfo.ctrlInfo 511 private val fenceio = intExuBlock.io.fenceio.get 512 io.fenceio <> fenceio 513 514 // to fpExuBlock 515 fpExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 516 for (i <- 0 until fpExuBlock.io.in.length) { 517 for (j <- 0 until fpExuBlock.io.in(i).length) { 518 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.fp(i)(j).bits.loadDependency, io.mem.ldCancel) 519 NewPipelineConnect( 520 bypassNetwork.io.toExus.fp(i)(j), fpExuBlock.io.in(i)(j), fpExuBlock.io.in(i)(j).fire, 521 Mux( 522 bypassNetwork.io.toExus.fp(i)(j).fire, 523 bypassNetwork.io.toExus.fp(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 524 fpExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 525 ), 526 Option("bypassNetwork2fpExuBlock") 527 ) 528 } 529 } 530 531 vfExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 532 for (i <- 0 until vfExuBlock.io.in.size) { 533 for (j <- 0 until vfExuBlock.io.in(i).size) { 534 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.vf(i)(j).bits.loadDependency, io.mem.ldCancel) 535 NewPipelineConnect( 536 bypassNetwork.io.toExus.vf(i)(j), vfExuBlock.io.in(i)(j), vfExuBlock.io.in(i)(j).fire, 537 Mux( 538 bypassNetwork.io.toExus.vf(i)(j).fire, 539 bypassNetwork.io.toExus.vf(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 540 vfExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 541 ), 542 Option("bypassNetwork2vfExuBlock") 543 ) 544 545 } 546 } 547 548 intExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 549 fpExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 550 fpExuBlock.io.vxrm.foreach(_ := csrio.vpu.vxrm) 551 vfExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 552 vfExuBlock.io.vxrm.foreach(_ := csrio.vpu.vxrm) 553 554 wbDataPath.io.flush := ctrlBlock.io.redirect 555 wbDataPath.io.fromTop.hartId := io.fromTop.hartId 556 wbDataPath.io.fromIntExu <> intExuBlock.io.out 557 wbDataPath.io.fromFpExu <> fpExuBlock.io.out 558 wbDataPath.io.fromVfExu <> vfExuBlock.io.out 559 wbDataPath.io.fromMemExu.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 560 sink.valid := source.valid 561 source.ready := sink.ready 562 sink.bits.data := VecInit(Seq.fill(sink.bits.params.wbPathNum)(source.bits.data)) 563 sink.bits.pdest := source.bits.uop.pdest 564 sink.bits.robIdx := source.bits.uop.robIdx 565 sink.bits.intWen.foreach(_ := source.bits.uop.rfWen) 566 sink.bits.fpWen.foreach(_ := source.bits.uop.fpWen) 567 sink.bits.vecWen.foreach(_ := source.bits.uop.vecWen) 568 sink.bits.v0Wen.foreach(_ := source.bits.uop.v0Wen) 569 sink.bits.vlWen.foreach(_ := source.bits.uop.vlWen) 570 sink.bits.exceptionVec.foreach(_ := source.bits.uop.exceptionVec) 571 sink.bits.flushPipe.foreach(_ := source.bits.uop.flushPipe) 572 sink.bits.replay.foreach(_ := source.bits.uop.replayInst) 573 sink.bits.debug := source.bits.debug 574 sink.bits.debugInfo := source.bits.uop.debugInfo 575 sink.bits.lqIdx.foreach(_ := source.bits.uop.lqIdx) 576 sink.bits.sqIdx.foreach(_ := source.bits.uop.sqIdx) 577 sink.bits.predecodeInfo.foreach(_ := source.bits.uop.preDecodeInfo) 578 sink.bits.vls.foreach(x => { 579 x.vdIdx := source.bits.vdIdx.get 580 x.vdIdxInField := source.bits.vdIdxInField.get 581 x.vpu := source.bits.uop.vpu 582 x.oldVdPsrc := source.bits.uop.psrc(2) 583 x.isIndexed := VlduType.isIndexed(source.bits.uop.fuOpType) 584 x.isMasked := VlduType.isMasked(source.bits.uop.fuOpType) 585 x.isStrided := VlduType.isStrided(source.bits.uop.fuOpType) 586 x.isWhole := VlduType.isWhole(source.bits.uop.fuOpType) 587 x.isVecLoad := VlduType.isVecLd(source.bits.uop.fuOpType) 588 x.isVlm := VlduType.isMasked(source.bits.uop.fuOpType) && VlduType.isVecLd(source.bits.uop.fuOpType) 589 }) 590 sink.bits.trigger.foreach(_ := source.bits.uop.trigger) 591 } 592 wbDataPath.io.fromCSR.vstart := csrio.vpu.vstart 593 594 vecExcpMod.i.fromExceptionGen := ctrlBlock.io.toVecExcpMod.excpInfo 595 vecExcpMod.i.fromRab.logicPhyRegMap := ctrlBlock.io.toVecExcpMod.logicPhyRegMap 596 vecExcpMod.i.fromRat := ctrlBlock.io.toVecExcpMod.ratOldPest 597 vecExcpMod.i.fromVprf := dataPath.io.toVecExcpMod 598 599 // to mem 600 private val memIssueParams = params.memSchdParams.get.issueBlockParams 601 private val memExuBlocksHasLDU = memIssueParams.map(_.exuBlockParams.map(x => x.hasLoadFu || x.hasHyldaFu)) 602 private val memExuBlocksHasVecLoad = memIssueParams.map(_.exuBlockParams.map(x => x.hasVLoadFu)) 603 println(s"[Backend] memExuBlocksHasLDU: $memExuBlocksHasLDU") 604 println(s"[Backend] memExuBlocksHasVecLoad: $memExuBlocksHasVecLoad") 605 606 private val toMem = Wire(bypassNetwork.io.toExus.mem.cloneType) 607 for (i <- toMem.indices) { 608 for (j <- toMem(i).indices) { 609 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.mem(i)(j).bits.loadDependency, io.mem.ldCancel) 610 val needIssueTimeout = memExuBlocksHasLDU(i)(j) || memExuBlocksHasVecLoad(i)(j) 611 val issueTimeout = 612 if (needIssueTimeout) 613 Counter(0 until 16, toMem(i)(j).valid && !toMem(i)(j).fire, bypassNetwork.io.toExus.mem(i)(j).fire)._2 614 else 615 false.B 616 617 if (memScheduler.io.loadFinalIssueResp(i).nonEmpty && memExuBlocksHasLDU(i)(j)) { 618 memScheduler.io.loadFinalIssueResp(i)(j).valid := issueTimeout 619 memScheduler.io.loadFinalIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType 620 memScheduler.io.loadFinalIssueResp(i)(j).bits.resp := RespType.block 621 memScheduler.io.loadFinalIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx 622 memScheduler.io.loadFinalIssueResp(i)(j).bits.uopIdx.foreach(_ := toMem(i)(j).bits.vpu.get.vuopIdx) 623 memScheduler.io.loadFinalIssueResp(i)(j).bits.sqIdx.foreach(_ := toMem(i)(j).bits.sqIdx.get) 624 memScheduler.io.loadFinalIssueResp(i)(j).bits.lqIdx.foreach(_ := toMem(i)(j).bits.lqIdx.get) 625 } 626 627 if (memScheduler.io.vecLoadFinalIssueResp(i).nonEmpty && memExuBlocksHasVecLoad(i)(j)) { 628 memScheduler.io.vecLoadFinalIssueResp(i)(j).valid := issueTimeout 629 memScheduler.io.vecLoadFinalIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType 630 memScheduler.io.vecLoadFinalIssueResp(i)(j).bits.resp := RespType.block 631 memScheduler.io.vecLoadFinalIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx 632 memScheduler.io.vecLoadFinalIssueResp(i)(j).bits.uopIdx.foreach(_ := toMem(i)(j).bits.vpu.get.vuopIdx) 633 memScheduler.io.vecLoadFinalIssueResp(i)(j).bits.sqIdx.foreach(_ := toMem(i)(j).bits.sqIdx.get) 634 memScheduler.io.vecLoadFinalIssueResp(i)(j).bits.lqIdx.foreach(_ := toMem(i)(j).bits.lqIdx.get) 635 } 636 637 NewPipelineConnect( 638 bypassNetwork.io.toExus.mem(i)(j), toMem(i)(j), toMem(i)(j).fire, 639 Mux( 640 bypassNetwork.io.toExus.mem(i)(j).fire, 641 bypassNetwork.io.toExus.mem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 642 toMem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || issueTimeout 643 ), 644 Option("bypassNetwork2toMemExus") 645 ) 646 647 if (memScheduler.io.memAddrIssueResp(i).nonEmpty && memExuBlocksHasLDU(i)(j)) { 648 memScheduler.io.memAddrIssueResp(i)(j).valid := toMem(i)(j).fire && FuType.isLoad(toMem(i)(j).bits.fuType) 649 memScheduler.io.memAddrIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType 650 memScheduler.io.memAddrIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx 651 memScheduler.io.memAddrIssueResp(i)(j).bits.sqIdx.foreach(_ := toMem(i)(j).bits.sqIdx.get) 652 memScheduler.io.memAddrIssueResp(i)(j).bits.lqIdx.foreach(_ := toMem(i)(j).bits.lqIdx.get) 653 memScheduler.io.memAddrIssueResp(i)(j).bits.resp := RespType.success // for load inst, firing at toMem means issuing successfully 654 } 655 656 if (memScheduler.io.vecLoadIssueResp(i).nonEmpty && memExuBlocksHasVecLoad(i)(j)) { 657 memScheduler.io.vecLoadIssueResp(i)(j) match { 658 case resp => 659 resp.valid := toMem(i)(j).fire && VlduType.isVecLd(toMem(i)(j).bits.fuOpType) 660 resp.bits.fuType := toMem(i)(j).bits.fuType 661 resp.bits.robIdx := toMem(i)(j).bits.robIdx 662 resp.bits.uopIdx.get := toMem(i)(j).bits.vpu.get.vuopIdx 663 resp.bits.sqIdx.get := toMem(i)(j).bits.sqIdx.get 664 resp.bits.lqIdx.get := toMem(i)(j).bits.lqIdx.get 665 resp.bits.resp := RespType.success 666 } 667 if (backendParams.debugEn){ 668 dontTouch(memScheduler.io.vecLoadIssueResp(i)(j)) 669 } 670 } 671 } 672 } 673 674 io.mem.redirect := ctrlBlock.io.redirect 675 io.mem.issueUops.zip(toMem.flatten).foreach { case (sink, source) => 676 val enableMdp = Constantin.createRecord("EnableMdp", true) 677 sink.valid := source.valid 678 source.ready := sink.ready 679 sink.bits.iqIdx := source.bits.iqIdx 680 sink.bits.isFirstIssue := source.bits.isFirstIssue 681 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 682 sink.bits.src := 0.U.asTypeOf(sink.bits.src) 683 sink.bits.src.zip(source.bits.src).foreach { case (l, r) => l := r} 684 sink.bits.uop.fuType := source.bits.fuType 685 sink.bits.uop.fuOpType := source.bits.fuOpType 686 sink.bits.uop.imm := source.bits.imm 687 sink.bits.uop.robIdx := source.bits.robIdx 688 sink.bits.uop.pdest := source.bits.pdest 689 sink.bits.uop.rfWen := source.bits.rfWen.getOrElse(false.B) 690 sink.bits.uop.fpWen := source.bits.fpWen.getOrElse(false.B) 691 sink.bits.uop.vecWen := source.bits.vecWen.getOrElse(false.B) 692 sink.bits.uop.v0Wen := source.bits.v0Wen.getOrElse(false.B) 693 sink.bits.uop.vlWen := source.bits.vlWen.getOrElse(false.B) 694 sink.bits.uop.flushPipe := source.bits.flushPipe.getOrElse(false.B) 695 sink.bits.uop.pc := source.bits.pc.getOrElse(0.U) 696 sink.bits.uop.loadWaitBit := Mux(enableMdp, source.bits.loadWaitBit.getOrElse(false.B), false.B) 697 sink.bits.uop.waitForRobIdx := Mux(enableMdp, source.bits.waitForRobIdx.getOrElse(0.U.asTypeOf(new RobPtr)), 0.U.asTypeOf(new RobPtr)) 698 sink.bits.uop.storeSetHit := Mux(enableMdp, source.bits.storeSetHit.getOrElse(false.B), false.B) 699 sink.bits.uop.loadWaitStrict := Mux(enableMdp, source.bits.loadWaitStrict.getOrElse(false.B), false.B) 700 sink.bits.uop.ssid := Mux(enableMdp, source.bits.ssid.getOrElse(0.U(SSIDWidth.W)), 0.U(SSIDWidth.W)) 701 sink.bits.uop.lqIdx := source.bits.lqIdx.getOrElse(0.U.asTypeOf(new LqPtr)) 702 sink.bits.uop.sqIdx := source.bits.sqIdx.getOrElse(0.U.asTypeOf(new SqPtr)) 703 sink.bits.uop.ftqPtr := source.bits.ftqIdx.getOrElse(0.U.asTypeOf(new FtqPtr)) 704 sink.bits.uop.ftqOffset := source.bits.ftqOffset.getOrElse(0.U) 705 sink.bits.uop.debugInfo := source.bits.perfDebugInfo 706 sink.bits.uop.vpu := source.bits.vpu.getOrElse(0.U.asTypeOf(new VPUCtrlSignals)) 707 sink.bits.uop.preDecodeInfo := source.bits.preDecode.getOrElse(0.U.asTypeOf(new PreDecodeInfo)) 708 sink.bits.uop.numLsElem := source.bits.numLsElem.getOrElse(0.U) // Todo: remove this bundle, keep only the one below 709 sink.bits.flowNum.foreach(_ := source.bits.numLsElem.get) 710 } 711 io.mem.loadFastMatch := memScheduler.io.toMem.get.loadFastMatch.map(_.fastMatch) 712 io.mem.loadFastImm := memScheduler.io.toMem.get.loadFastMatch.map(_.fastImm) 713 io.mem.tlbCsr := csrio.tlb 714 io.mem.csrCtrl := csrio.customCtrl 715 io.mem.sfence := fenceio.sfence 716 io.mem.isStoreException := CommitType.lsInstIsStore(ctrlBlock.io.robio.exception.bits.commitType) 717 io.mem.isVlsException := ctrlBlock.io.robio.exception.bits.vls 718 require(io.mem.loadPcRead.size == params.LduCnt) 719 io.mem.loadPcRead.zipWithIndex.foreach { case (loadPcRead, i) => 720 loadPcRead := ctrlBlock.io.memLdPcRead(i).data 721 ctrlBlock.io.memLdPcRead(i).valid := io.mem.issueLda(i).valid 722 ctrlBlock.io.memLdPcRead(i).ptr := io.mem.issueLda(i).bits.uop.ftqPtr 723 ctrlBlock.io.memLdPcRead(i).offset := io.mem.issueLda(i).bits.uop.ftqOffset 724 } 725 726 io.mem.storePcRead.zipWithIndex.foreach { case (storePcRead, i) => 727 storePcRead := ctrlBlock.io.memStPcRead(i).data 728 ctrlBlock.io.memStPcRead(i).valid := io.mem.issueSta(i).valid 729 ctrlBlock.io.memStPcRead(i).ptr := io.mem.issueSta(i).bits.uop.ftqPtr 730 ctrlBlock.io.memStPcRead(i).offset := io.mem.issueSta(i).bits.uop.ftqOffset 731 } 732 733 io.mem.hyuPcRead.zipWithIndex.foreach( { case (hyuPcRead, i) => 734 hyuPcRead := ctrlBlock.io.memHyPcRead(i).data 735 ctrlBlock.io.memHyPcRead(i).valid := io.mem.issueHylda(i).valid 736 ctrlBlock.io.memHyPcRead(i).ptr := io.mem.issueHylda(i).bits.uop.ftqPtr 737 ctrlBlock.io.memHyPcRead(i).offset := io.mem.issueHylda(i).bits.uop.ftqOffset 738 }) 739 740 ctrlBlock.io.robio.robHeadLsIssue := io.mem.issueUops.map(deq => deq.fire && deq.bits.uop.robIdx === ctrlBlock.io.robio.robDeqPtr).reduce(_ || _) 741 742 // mem io 743 io.mem.lsqEnqIO <> memScheduler.io.memIO.get.lsqEnqIO 744 io.mem.robLsqIO <> ctrlBlock.io.robio.lsq 745 io.mem.storeDebugInfo <> ctrlBlock.io.robio.storeDebugInfo 746 747 io.frontendSfence := fenceio.sfence 748 io.frontendTlbCsr := csrio.tlb 749 io.frontendCsrCtrl := csrio.customCtrl 750 751 io.tlb <> csrio.tlb 752 753 io.csrCustomCtrl := csrio.customCtrl 754 755 io.toTop.cpuHalted := ctrlBlock.io.toTop.cpuHalt 756 757 io.traceCoreInterface <> ctrlBlock.io.traceCoreInterface 758 759 io.debugTopDown.fromRob := ctrlBlock.io.debugTopDown.fromRob 760 ctrlBlock.io.debugTopDown.fromCore := io.debugTopDown.fromCore 761 762 io.debugRolling := ctrlBlock.io.debugRolling 763 764 if(backendParams.debugEn) { 765 dontTouch(memScheduler.io) 766 dontTouch(dataPath.io.toMemExu) 767 dontTouch(wbDataPath.io.fromMemExu) 768 } 769 770 // reset tree 771 if (p(DebugOptionsKey).ResetGen) { 772 val rightResetTree = ResetGenNode(Seq( 773 ModuleNode(dataPath), 774 ModuleNode(intExuBlock), 775 ModuleNode(fpExuBlock), 776 ModuleNode(vfExuBlock), 777 ModuleNode(bypassNetwork), 778 ModuleNode(wbDataPath) 779 )) 780 val leftResetTree = ResetGenNode(Seq( 781 ModuleNode(pcTargetMem), 782 ModuleNode(intScheduler), 783 ModuleNode(fpScheduler), 784 ModuleNode(vfScheduler), 785 ModuleNode(memScheduler), 786 ModuleNode(og2ForVector), 787 ModuleNode(wbFuBusyTable), 788 ResetGenNode(Seq( 789 ModuleNode(ctrlBlock), 790 // ResetGenNode(Seq( 791 CellNode(io.frontendReset) 792 // )) 793 )) 794 )) 795 ResetGen(leftResetTree, reset, sim = false) 796 ResetGen(rightResetTree, reset, sim = false) 797 } else { 798 io.frontendReset := DontCare 799 } 800 801 // perf events 802 val pfevent = Module(new PFEvent) 803 pfevent.io.distribute_csr := RegNext(csrio.customCtrl.distribute_csr) 804 val csrevents = pfevent.io.hpmevent.slice(8,16) 805 806 val ctrlBlockPerf = ctrlBlock.getPerfEvents 807 val intSchedulerPerf = intScheduler.asInstanceOf[SchedulerArithImp].getPerfEvents 808 val fpSchedulerPerf = fpScheduler.asInstanceOf[SchedulerArithImp].getPerfEvents 809 val vecSchedulerPerf = vfScheduler.asInstanceOf[SchedulerArithImp].getPerfEvents 810 val memSchedulerPerf = memScheduler.asInstanceOf[SchedulerMemImp].getPerfEvents 811 812 val perfBackend = Seq() 813 // let index = 0 be no event 814 val allPerfEvents = Seq(("noEvent", 0.U)) ++ ctrlBlockPerf ++ intSchedulerPerf ++ fpSchedulerPerf ++ vecSchedulerPerf ++ memSchedulerPerf ++ perfBackend 815 816 817 if (printEventCoding) { 818 for (((name, inc), i) <- allPerfEvents.zipWithIndex) { 819 println("backend perfEvents Set", name, inc, i) 820 } 821 } 822 823 val allPerfInc = allPerfEvents.map(_._2.asTypeOf(new PerfEvent)) 824 val perfEvents = HPerfMonitor(csrevents, allPerfInc).getPerfEvents 825 csrio.perf.perfEventsBackend := VecInit(perfEvents.map(_._2.asTypeOf(new PerfEvent))) 826 827 val ctrlBlockError = ctrlBlock.getCriticalErrors 828 val intExuBlockError = intExuBlock.getCriticalErrors 829 val criticalErrors = ctrlBlockError ++ intExuBlockError 830 831 if (printCriticalError) { 832 for (((name, error), _) <- criticalErrors.zipWithIndex) { 833 XSError(error, s"critical error: $name \n") 834 } 835 } 836 837 // expand to collect frontend/memblock/L2 critical errors 838 backendCriticalError := criticalErrors.map(_._2).reduce(_ || _) 839 840 io.toTop.cpuCriticalError := csrio.criticalErrorState 841} 842 843class BackendMemIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 844 // Since fast load replay always use load unit 0, Backend flips two load port to avoid conflicts 845 val flippedLda = true 846 // params alias 847 private val LoadQueueSize = VirtualLoadQueueSize 848 // In/Out // Todo: split it into one-direction bundle 849 val lsqEnqIO = Flipped(new LsqEnqIO) 850 val robLsqIO = new RobLsqIO 851 val ldaIqFeedback = Vec(params.LduCnt, Flipped(new MemRSFeedbackIO)) 852 val staIqFeedback = Vec(params.StaCnt, Flipped(new MemRSFeedbackIO)) 853 val hyuIqFeedback = Vec(params.HyuCnt, Flipped(new MemRSFeedbackIO)) 854 val vstuIqFeedback = Flipped(Vec(params.VstuCnt, new MemRSFeedbackIO(isVector = true))) 855 val vlduIqFeedback = Flipped(Vec(params.VlduCnt, new MemRSFeedbackIO(isVector = true))) 856 val ldCancel = Vec(params.LdExuCnt, Input(new LoadCancelIO)) 857 val wakeup = Vec(params.LdExuCnt, Flipped(Valid(new DynInst))) 858 val loadPcRead = Vec(params.LduCnt, Output(UInt(VAddrBits.W))) 859 val storePcRead = Vec(params.StaCnt, Output(UInt(VAddrBits.W))) 860 val hyuPcRead = Vec(params.HyuCnt, Output(UInt(VAddrBits.W))) 861 // Input 862 val writebackLda = Vec(params.LduCnt, Flipped(DecoupledIO(new MemExuOutput))) 863 val writebackSta = Vec(params.StaCnt, Flipped(DecoupledIO(new MemExuOutput))) 864 val writebackStd = Vec(params.StdCnt, Flipped(DecoupledIO(new MemExuOutput))) 865 val writebackHyuLda = Vec(params.HyuCnt, Flipped(DecoupledIO(new MemExuOutput))) 866 val writebackHyuSta = Vec(params.HyuCnt, Flipped(DecoupledIO(new MemExuOutput))) 867 val writebackVldu = Vec(params.VlduCnt, Flipped(DecoupledIO(new MemExuOutput(true)))) 868 869 val s3_delayed_load_error = Input(Vec(LoadPipelineWidth, Bool())) 870 val stIn = Input(Vec(params.StaExuCnt, ValidIO(new DynInst()))) 871 val memoryViolation = Flipped(ValidIO(new Redirect)) 872 val exceptionAddr = Input(new Bundle { 873 val vaddr = UInt(XLEN.W) 874 val gpaddr = UInt(XLEN.W) 875 val isForVSnonLeafPTE = Bool() 876 }) 877 val sqDeq = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) 878 val lqDeq = Input(UInt(log2Up(CommitWidth + 1).W)) 879 val sqDeqPtr = Input(new SqPtr) 880 val lqDeqPtr = Input(new LqPtr) 881 882 val lqCancelCnt = Input(UInt(log2Up(VirtualLoadQueueSize + 1).W)) 883 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 884 885 val lqCanAccept = Input(Bool()) 886 val sqCanAccept = Input(Bool()) 887 888 val otherFastWakeup = Flipped(Vec(params.LduCnt + params.HyuCnt, ValidIO(new DynInst))) 889 val stIssuePtr = Input(new SqPtr()) 890 891 val debugLS = Flipped(Output(new DebugLSIO)) 892 893 val lsTopdownInfo = Vec(params.LduCnt + params.HyuCnt, Flipped(Output(new LsTopdownInfo))) 894 // Output 895 val redirect = ValidIO(new Redirect) // rob flush MemBlock 896 val issueLda = MixedVec(Seq.fill(params.LduCnt)(DecoupledIO(new MemExuInput()))) 897 val issueSta = MixedVec(Seq.fill(params.StaCnt)(DecoupledIO(new MemExuInput()))) 898 val issueStd = MixedVec(Seq.fill(params.StdCnt)(DecoupledIO(new MemExuInput()))) 899 val issueHylda = MixedVec(Seq.fill(params.HyuCnt)(DecoupledIO(new MemExuInput()))) 900 val issueHysta = MixedVec(Seq.fill(params.HyuCnt)(DecoupledIO(new MemExuInput()))) 901 val issueVldu = MixedVec(Seq.fill(params.VlduCnt)(DecoupledIO(new MemExuInput(true)))) 902 903 val loadFastMatch = Vec(params.LduCnt, Output(UInt(params.LduCnt.W))) 904 val loadFastImm = Vec(params.LduCnt, Output(UInt(12.W))) // Imm_I 905 906 val tlbCsr = Output(new TlbCsrBundle) 907 val csrCtrl = Output(new CustomCSRCtrlIO) 908 val sfence = Output(new SfenceBundle) 909 val isStoreException = Output(Bool()) 910 val isVlsException = Output(Bool()) 911 912 // ATTENTION: The issue ports' sequence order should be the same as IQs' deq config 913 private [backend] def issueUops: Seq[DecoupledIO[MemExuInput]] = { 914 issueSta ++ 915 issueHylda ++ issueHysta ++ 916 issueLda ++ 917 issueVldu ++ 918 issueStd 919 }.toSeq 920 921 // ATTENTION: The writeback ports' sequence order should be the same as IQs' deq config 922 private [backend] def writeBack: Seq[DecoupledIO[MemExuOutput]] = { 923 writebackSta ++ 924 writebackHyuLda ++ writebackHyuSta ++ 925 writebackLda ++ 926 writebackVldu ++ 927 writebackStd 928 } 929 930 // store event difftest information 931 val storeDebugInfo = Vec(EnsbufferWidth, new Bundle { 932 val robidx = Input(new RobPtr) 933 val pc = Output(UInt(VAddrBits.W)) 934 }) 935} 936 937class TopToBackendBundle(implicit p: Parameters) extends XSBundle { 938 val hartId = Output(UInt(hartIdLen.W)) 939 val externalInterrupt = Output(new ExternalInterruptIO) 940 val msiInfo = Output(ValidIO(new MsiInfoBundle)) 941 val clintTime = Output(ValidIO(UInt(64.W))) 942} 943 944class BackendToTopBundle extends Bundle { 945 val cpuHalted = Output(Bool()) 946 val cpuCriticalError = Output(Bool()) 947} 948 949class BackendIO(implicit p: Parameters, params: BackendParams) extends XSBundle with HasSoCParameter { 950 val fromTop = Flipped(new TopToBackendBundle) 951 952 val toTop = new BackendToTopBundle 953 954 val traceCoreInterface = new TraceCoreInterface 955 956 val fenceio = new FenceIO 957 // Todo: merge these bundles into BackendFrontendIO 958 val frontend = Flipped(new FrontendToCtrlIO) 959 val frontendSfence = Output(new SfenceBundle) 960 val frontendCsrCtrl = Output(new CustomCSRCtrlIO) 961 val frontendTlbCsr = Output(new TlbCsrBundle) 962 val frontendReset = Output(Reset()) 963 964 val mem = new BackendMemIO 965 966 val perf = Input(new PerfCounterIO) 967 968 val tlb = Output(new TlbCsrBundle) 969 970 val csrCustomCtrl = Output(new CustomCSRCtrlIO) 971 972 val debugTopDown = new Bundle { 973 val fromRob = new RobCoreTopDownIO 974 val fromCore = new CoreDispatchTopDownIO 975 } 976 val debugRolling = new RobDebugRollingIO 977} 978