1package xiangshan.backend 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utils.OptionWrapper 7import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 8import utility.{PipelineConnect, ZeroExt} 9import xiangshan._ 10import xiangshan.backend.Bundles.{DynInst, MemExuInput, MemExuOutput} 11import xiangshan.backend.ctrlblock.CtrlBlock 12import xiangshan.backend.datapath.WbConfig._ 13import xiangshan.backend.datapath.{DataPath, NewPipelineConnect, WbDataPath, WbFuBusyTable} 14import xiangshan.backend.exu.ExuBlock 15import xiangshan.backend.fu.vector.Bundles.{VConfig, VType} 16import xiangshan.backend.fu.{FenceIO, FenceToSbuffer, FuConfig, PerfCounterIO} 17import xiangshan.backend.issue.{Scheduler, IntScheduler, MemScheduler, VfScheduler} 18import xiangshan.backend.rob.RobLsqIO 19import xiangshan.frontend.{FtqPtr, FtqRead} 20import xiangshan.mem.{LqPtr, LsqEnqIO, SqPtr} 21 22class Backend(val params: BackendParams)(implicit p: Parameters) extends LazyModule 23 with HasXSParameter { 24 25 /* Only update the idx in mem-scheduler here 26 * Idx in other schedulers can be updated the same way if needed 27 * 28 * Also note that we filter out the 'stData issue-queues' when counting 29 */ 30 for ((ibp, idx) <- params.memSchdParams.get.issueBlockParams.filter(iq => iq.StdCnt == 0).zipWithIndex) { 31 ibp.updateIdx(idx) 32 } 33 34 println(params.iqWakeUpParams) 35 36 for ((exuCfg, i) <- params.allExuParams.zipWithIndex) { 37 exuCfg.updateIQWakeUpConfigs(params.iqWakeUpParams) 38 exuCfg.updateExuIdx(i) 39 } 40 41 println("[Backend] ExuConfigs:") 42 for (exuCfg <- params.allExuParams) { 43 val fuConfigs = exuCfg.fuConfigs 44 val wbPortConfigs = exuCfg.wbPortConfigs 45 val immType = exuCfg.immType 46 47 println("[Backend] " + 48 s"${exuCfg.name}: " + 49 s"${ fuConfigs.map(_.name).mkString("fu(s): {", ",", "}") }, " + 50 s"${ wbPortConfigs.mkString("wb: {", ",", "}") }, " + 51 s"${ immType.map(SelImm.mkString(_)).mkString("imm: {", "," , "}") }, " + 52 s"latMax(${exuCfg.latencyValMax}), ${exuCfg.fuLatancySet.mkString("lat: {",",","}")}, ") 53 require(wbPortConfigs.collectFirst { case x: IntWB => x }.nonEmpty == 54 fuConfigs.map(_.writeIntRf).reduce(_ || _), 55 "int wb port has no priority" ) 56 require(wbPortConfigs.collectFirst { case x: VfWB => x }.nonEmpty == 57 fuConfigs.map(x => x.writeFpRf || x.writeVecRf).reduce(_ || _), 58 "vec wb port has no priority" ) 59 } 60 61 for (cfg <- FuConfig.allConfigs) { 62 println(s"[Backend] $cfg") 63 } 64 65 val ctrlBlock = LazyModule(new CtrlBlock(params)) 66 val intScheduler = params.intSchdParams.map(x => LazyModule(new Scheduler(x))) 67 val vfScheduler = params.vfSchdParams.map(x => LazyModule(new Scheduler(x))) 68 val memScheduler = params.memSchdParams.map(x => LazyModule(new Scheduler(x))) 69 val dataPath = LazyModule(new DataPath(params)) 70 val intExuBlock = params.intSchdParams.map(x => LazyModule(new ExuBlock(x))) 71 val vfExuBlock = params.vfSchdParams.map(x => LazyModule(new ExuBlock(x))) 72 val wbFuBusyTable = LazyModule(new WbFuBusyTable(params)) 73 74 lazy val module = new BackendImp(this) 75} 76 77class BackendImp(override val wrapper: Backend)(implicit p: Parameters) extends LazyModuleImp(wrapper) 78 with HasXSParameter{ 79 implicit private val params = wrapper.params 80 val io = IO(new BackendIO()(p, wrapper.params)) 81 82 private val ctrlBlock = wrapper.ctrlBlock.module 83 private val intScheduler = wrapper.intScheduler.get.module 84 private val vfScheduler = wrapper.vfScheduler.get.module 85 private val memScheduler = wrapper.memScheduler.get.module 86 private val dataPath = wrapper.dataPath.module 87 private val intExuBlock = wrapper.intExuBlock.get.module 88 private val vfExuBlock = wrapper.vfExuBlock.get.module 89 private val wbDataPath = Module(new WbDataPath(params)) 90 private val wbFuBusyTable = wrapper.wbFuBusyTable.module 91 92 private val iqWakeUpMappedBundle: Map[String, ValidIO[Bundles.IssueQueueWakeUpBundle]] = ( 93 intScheduler.io.toSchedulers.wakeupVec ++ 94 vfScheduler.io.toSchedulers.wakeupVec ++ 95 memScheduler.io.toSchedulers.wakeupVec 96 ).map(x => (x.bits.wakeupSource, x)).toMap 97 98 println(s"[Backend] iq wake up keys: ${iqWakeUpMappedBundle.keys}") 99 100 wbFuBusyTable.io.in.intSchdBusyTable := intScheduler.io.wbFuBusyTable 101 wbFuBusyTable.io.in.vfSchdBusyTable := vfScheduler.io.wbFuBusyTable 102 wbFuBusyTable.io.in.memSchdBusyTable := memScheduler.io.wbFuBusyTable 103 intScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.intRespRead 104 vfScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.vfRespRead 105 memScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.memRespRead 106 dataPath.io.wbConfictRead := wbFuBusyTable.io.out.wbConflictRead 107 108 wbDataPath.io.fromIntExu.flatten.filter(x => x.bits.params.writeIntRf) 109 110 private val vconfig = dataPath.io.vconfigReadPort.data 111 112 ctrlBlock.io.fromTop.hartId := io.fromTop.hartId 113 ctrlBlock.io.frontend <> io.frontend 114 ctrlBlock.io.fromWB.wbData <> wbDataPath.io.toCtrlBlock.writeback 115 ctrlBlock.io.fromMem.stIn <> io.mem.stIn 116 ctrlBlock.io.fromMem.violation <> io.mem.memoryViolation 117 ctrlBlock.io.csrCtrl <> intExuBlock.io.csrio.get.customCtrl 118 ctrlBlock.io.robio.csr.intrBitSet := intExuBlock.io.csrio.get.interrupt 119 ctrlBlock.io.robio.csr.trapTarget := intExuBlock.io.csrio.get.trapTarget 120 ctrlBlock.io.robio.csr.isXRet := intExuBlock.io.csrio.get.isXRet 121 ctrlBlock.io.robio.csr.wfiEvent := intExuBlock.io.csrio.get.wfi_event 122 ctrlBlock.io.robio.lsq <> io.mem.robLsqIO 123 ctrlBlock.io.fromDataPath.vtype := vconfig(7, 0).asTypeOf(new VType) 124 125 intScheduler.io.fromTop.hartId := io.fromTop.hartId 126 intScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 127 intScheduler.io.fromCtrlBlock.pcVec := ctrlBlock.io.toIssueBlock.pcVec 128 intScheduler.io.fromCtrlBlock.targetVec := ctrlBlock.io.toIssueBlock.targetVec 129 intScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 130 intScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.intUops 131 intScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 132 intScheduler.io.vfWriteBack := 0.U.asTypeOf(intScheduler.io.vfWriteBack) 133 intScheduler.io.fromDataPath := dataPath.io.toIntIQ 134 intScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.wakeupSource) } 135 136 memScheduler.io.fromTop.hartId := io.fromTop.hartId 137 memScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 138 memScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 139 memScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.memUops 140 memScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 141 memScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 142 memScheduler.io.fromMem.get.scommit := io.mem.sqDeq 143 memScheduler.io.fromMem.get.lcommit := io.mem.lqDeq 144 memScheduler.io.fromMem.get.sqCancelCnt := io.mem.sqCancelCnt 145 memScheduler.io.fromMem.get.lqCancelCnt := io.mem.lqCancelCnt 146 memScheduler.io.fromMem.get.stIssuePtr := io.mem.stIssuePtr 147 memScheduler.io.fromMem.get.memWaitUpdateReq.staIssue.zip(io.mem.stIn).foreach { case (sink, source) => 148 sink.valid := source.valid 149 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 150 sink.bits.uop.robIdx := source.bits.robIdx 151 } 152 memScheduler.io.fromDataPath := dataPath.io.toMemIQ 153 memScheduler.io.fromMem.get.ldaFeedback := io.mem.ldaIqFeedback 154 memScheduler.io.fromMem.get.staFeedback := io.mem.staIqFeedback 155 memScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.wakeupSource) } 156 157 vfScheduler.io.fromTop.hartId := io.fromTop.hartId 158 vfScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 159 vfScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 160 vfScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.vfUops 161 vfScheduler.io.intWriteBack := 0.U.asTypeOf(vfScheduler.io.intWriteBack) 162 vfScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 163 vfScheduler.io.fromDataPath := dataPath.io.toVfIQ 164 vfScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.wakeupSource) } 165 166 dataPath.io.flush := ctrlBlock.io.toDataPath.flush 167 dataPath.io.vconfigReadPort.addr := ctrlBlock.io.toDataPath.vtypeAddr 168 169 for (i <- 0 until dataPath.io.fromIntIQ.length) { 170 for (j <- 0 until dataPath.io.fromIntIQ(i).length) { 171 NewPipelineConnect(intScheduler.io.toDataPath(i)(j), dataPath.io.fromIntIQ(i)(j), dataPath.io.fromIntIQ(i)(j).valid, 172 intScheduler.io.toDataPath(i)(j).bits.common.robIdx.needFlush(ctrlBlock.io.toDataPath.flush), Option("intScheduler2DataPathPipe")) 173 } 174 } 175 176 for (i <- 0 until dataPath.io.fromVfIQ.length) { 177 for (j <- 0 until dataPath.io.fromVfIQ(i).length) { 178 NewPipelineConnect(vfScheduler.io.toDataPath(i)(j), dataPath.io.fromVfIQ(i)(j), dataPath.io.fromVfIQ(i)(j).valid, 179 vfScheduler.io.toDataPath(i)(j).bits.common.robIdx.needFlush(ctrlBlock.io.toDataPath.flush), Option("vfScheduler2DataPathPipe")) 180 } 181 } 182 183 for (i <- 0 until dataPath.io.fromMemIQ.length) { 184 for (j <- 0 until dataPath.io.fromMemIQ(i).length) { 185 NewPipelineConnect(memScheduler.io.toDataPath(i)(j), dataPath.io.fromMemIQ(i)(j), dataPath.io.fromMemIQ(i)(j).valid, 186 memScheduler.io.toDataPath(i)(j).bits.common.robIdx.needFlush(ctrlBlock.io.toDataPath.flush), Option("memScheduler2DataPathPipe")) 187 } 188 } 189 190 println(s"[Backend] wbDataPath.io.toIntPreg: ${wbDataPath.io.toIntPreg.size}, dataPath.io.fromIntWb: ${dataPath.io.fromIntWb.size}") 191 println(s"[Backend] wbDataPath.io.toVfPreg: ${wbDataPath.io.toVfPreg.size}, dataPath.io.fromFpWb: ${dataPath.io.fromVfWb.size}") 192 dataPath.io.fromIntWb := wbDataPath.io.toIntPreg 193 dataPath.io.fromVfWb := wbDataPath.io.toVfPreg 194 dataPath.io.debugIntRat := ctrlBlock.io.debug_int_rat 195 dataPath.io.debugFpRat := ctrlBlock.io.debug_fp_rat 196 dataPath.io.debugVecRat := ctrlBlock.io.debug_vec_rat 197 dataPath.io.debugVconfigRat := ctrlBlock.io.debug_vconfig_rat 198 199 intExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 200 for (i <- 0 until intExuBlock.io.in.length) { 201 for (j <- 0 until intExuBlock.io.in(i).length) { 202 NewPipelineConnect(dataPath.io.toIntExu(i)(j), intExuBlock.io.in(i)(j), intExuBlock.io.in(i)(j).fire, 203 Mux(dataPath.io.toIntExu(i)(j).fire, 204 dataPath.io.toIntExu(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush), 205 intExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush))) 206 } 207 } 208 209 private val csrio = intExuBlock.io.csrio.get 210 csrio.hartId := io.fromTop.hartId 211 csrio.perf.retiredInstr <> ctrlBlock.io.robio.csr.perfinfo.retiredInstr 212 csrio.perf.ctrlInfo <> ctrlBlock.io.perfInfo.ctrlInfo 213 csrio.perf.perfEventsCtrl <> ctrlBlock.getPerf 214 csrio.fpu.fflags := ctrlBlock.io.robio.csr.fflags 215 csrio.fpu.isIllegal := false.B // Todo: remove it 216 csrio.fpu.dirty_fs := ctrlBlock.io.robio.csr.dirty_fs 217 csrio.vpu <> 0.U.asTypeOf(csrio.vpu) // Todo 218 219 val debugVconfig = dataPath.io.debugVconfig.asTypeOf(new VConfig) 220 val debugVtype = VType.toVtypeStruct(debugVconfig.vtype).asUInt 221 val debugVl = debugVconfig.vl 222 csrio.vpu.set_vxsat := ctrlBlock.io.robio.csr.vxsat 223 csrio.vpu.set_vstart.valid := ctrlBlock.io.robio.csr.vcsrFlag 224 csrio.vpu.set_vstart.bits := 0.U 225 csrio.vpu.set_vtype.valid := ctrlBlock.io.robio.csr.vcsrFlag 226 csrio.vpu.set_vtype.bits := ZeroExt(debugVtype, XLEN) 227 csrio.vpu.set_vl.valid := ctrlBlock.io.robio.csr.vcsrFlag 228 csrio.vpu.set_vl.bits := ZeroExt(debugVl, XLEN) 229 csrio.exception := ctrlBlock.io.robio.exception 230 csrio.memExceptionVAddr := io.mem.exceptionVAddr 231 csrio.externalInterrupt := io.fromTop.externalInterrupt 232 csrio.distributedUpdate(0) := io.mem.csrDistributedUpdate 233 csrio.distributedUpdate(1) := io.frontendCsrDistributedUpdate 234 csrio.perf <> io.perf 235 private val fenceio = intExuBlock.io.fenceio.get 236 fenceio.disableSfence := csrio.disableSfence 237 io.fenceio <> fenceio 238 239 vfExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 240 for (i <- 0 until vfExuBlock.io.in.size) { 241 for (j <- 0 until vfExuBlock.io.in(i).size) { 242 NewPipelineConnect(dataPath.io.toFpExu(i)(j), vfExuBlock.io.in(i)(j), vfExuBlock.io.in(i)(j).fire, 243 Mux(dataPath.io.toFpExu(i)(j).fire, 244 dataPath.io.toFpExu(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush), 245 vfExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush))) 246 } 247 } 248 vfExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 249 250 wbDataPath.io.flush := ctrlBlock.io.redirect 251 wbDataPath.io.fromTop.hartId := io.fromTop.hartId 252 wbDataPath.io.fromIntExu <> intExuBlock.io.out 253 wbDataPath.io.fromVfExu <> vfExuBlock.io.out 254 wbDataPath.io.fromMemExu.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 255 sink.valid := source.valid 256 source.ready := sink.ready 257 sink.bits.data := source.bits.data 258 sink.bits.pdest := source.bits.uop.pdest 259 sink.bits.robIdx := source.bits.uop.robIdx 260 sink.bits.intWen.foreach(_ := source.bits.uop.rfWen) 261 sink.bits.fpWen.foreach(_ := source.bits.uop.fpWen) 262 sink.bits.vecWen.foreach(_ := source.bits.uop.vecWen) 263 sink.bits.exceptionVec.foreach(_ := source.bits.uop.exceptionVec) 264 sink.bits.flushPipe.foreach(_ := source.bits.uop.flushPipe) 265 sink.bits.replay.foreach(_ := source.bits.uop.replayInst) 266 sink.bits.debug := source.bits.debug 267 sink.bits.debugInfo := 0.U.asTypeOf(sink.bits.debugInfo) 268 sink.bits.lqIdx.foreach(_ := source.bits.uop.lqIdx) 269 sink.bits.sqIdx.foreach(_ := source.bits.uop.sqIdx) 270 sink.bits.ftqIdx.foreach(_ := source.bits.uop.ftqPtr) 271 sink.bits.ftqOffset.foreach(_ := source.bits.uop.ftqOffset) 272 } 273 274 // to mem 275 io.mem.redirect := ctrlBlock.io.redirect 276 io.mem.issueUops.zip(dataPath.io.toMemExu.flatten).foreach { case (sink, source) => 277 sink.valid := source.valid 278 source.ready := sink.ready 279 sink.bits.iqIdx := source.bits.iqIdx 280 sink.bits.isFirstIssue := source.bits.isFirstIssue 281 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 282 sink.bits.src := 0.U.asTypeOf(sink.bits.src) 283 sink.bits.src.zip(source.bits.src).foreach { case (l, r) => l := r} 284 sink.bits.uop.fuType := source.bits.fuType 285 sink.bits.uop.fuOpType := source.bits.fuOpType 286 sink.bits.uop.imm := source.bits.imm 287 sink.bits.uop.robIdx := source.bits.robIdx 288 sink.bits.uop.pdest := source.bits.pdest 289 sink.bits.uop.rfWen := source.bits.rfWen.getOrElse(false.B) 290 sink.bits.uop.fpWen := source.bits.fpWen.getOrElse(false.B) 291 sink.bits.uop.vecWen := source.bits.vecWen.getOrElse(false.B) 292 sink.bits.uop.flushPipe := source.bits.flushPipe.getOrElse(false.B) 293 sink.bits.uop.pc := source.bits.pc.getOrElse(0.U) 294 sink.bits.uop.lqIdx := source.bits.lqIdx.getOrElse(0.U.asTypeOf(new LqPtr)) 295 sink.bits.uop.sqIdx := source.bits.sqIdx.getOrElse(0.U.asTypeOf(new SqPtr)) 296 sink.bits.uop.ftqPtr := source.bits.ftqIdx.getOrElse(0.U.asTypeOf(new FtqPtr)) 297 sink.bits.uop.ftqOffset := source.bits.ftqOffset.getOrElse(0.U) 298 } 299 io.mem.loadFastMatch := memScheduler.io.toMem.get.loadFastMatch.map(_.fastMatch) 300 io.mem.loadFastImm := memScheduler.io.toMem.get.loadFastMatch.map(_.fastImm) 301 io.mem.tlbCsr := csrio.tlb 302 io.mem.csrCtrl := csrio.customCtrl 303 io.mem.sfence := fenceio.sfence 304 io.mem.isStoreException := CommitType.lsInstIsStore(ctrlBlock.io.robio.exception.bits.commitType) 305 require(io.mem.loadPcRead.size == params.LduCnt) 306 io.mem.loadPcRead.zipWithIndex.foreach { case (loadPcRead, i) => 307 loadPcRead.data := ctrlBlock.io.memLdPcRead(i).data 308 ctrlBlock.io.memLdPcRead(i).ptr := loadPcRead.ptr 309 ctrlBlock.io.memLdPcRead(i).offset := loadPcRead.offset 310 } 311 // mem io 312 io.mem.lsqEnqIO <> memScheduler.io.memIO.get.lsqEnqIO 313 io.mem.robLsqIO <> ctrlBlock.io.robio.lsq 314 io.mem.toSbuffer <> fenceio.sbuffer 315 316 io.frontendSfence := fenceio.sfence 317 io.frontendTlbCsr := csrio.tlb 318 io.frontendCsrCtrl := csrio.customCtrl 319 320 io.tlb <> csrio.tlb 321 322 io.csrCustomCtrl := csrio.customCtrl 323 324 dontTouch(memScheduler.io) 325 dontTouch(io.mem) 326 dontTouch(dataPath.io.toMemExu) 327 dontTouch(wbDataPath.io.fromMemExu) 328} 329 330class BackendMemIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 331 // params alias 332 private val LoadQueueSize = VirtualLoadQueueSize 333 // In/Out // Todo: split it into one-direction bundle 334 val lsqEnqIO = Flipped(new LsqEnqIO) 335 val robLsqIO = new RobLsqIO 336 val toSbuffer = new FenceToSbuffer 337 val ldaIqFeedback = Vec(params.LduCnt, Flipped(new MemRSFeedbackIO)) 338 val staIqFeedback = Vec(params.StaCnt, Flipped(new MemRSFeedbackIO)) 339 val loadPcRead = Vec(params.LduCnt, Flipped(new FtqRead(UInt(VAddrBits.W)))) 340 341 // Input 342 val writeBack = MixedVec(Seq.fill(params.LduCnt + params.StaCnt * 2)(Flipped(DecoupledIO(new MemExuOutput()))) ++ Seq.fill(params.VlduCnt)(Flipped(DecoupledIO(new MemExuOutput(true))))) 343 344 val s3_delayed_load_error = Input(Vec(LoadPipelineWidth, Bool())) 345 val stIn = Input(Vec(params.StaCnt, ValidIO(new DynInst()))) 346 val memoryViolation = Flipped(ValidIO(new Redirect)) 347 val exceptionVAddr = Input(UInt(VAddrBits.W)) 348 val sqDeq = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) 349 val lqDeq = Input(UInt(log2Up(CommitWidth + 1).W)) 350 351 val lqCancelCnt = Input(UInt(log2Up(VirtualLoadQueueSize + 1).W)) 352 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 353 354 val otherFastWakeup = Flipped(Vec(params.LduCnt + 2 * params.StaCnt, ValidIO(new DynInst))) 355 val stIssuePtr = Input(new SqPtr()) 356 357 val csrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 358 359 // Output 360 val redirect = ValidIO(new Redirect) // rob flush MemBlock 361 val issueUops = MixedVec(Seq.fill(params.LduCnt + params.StaCnt * 2)(DecoupledIO(new MemExuInput())) ++ Seq.fill(params.VlduCnt)(DecoupledIO(new MemExuInput(true)))) 362 val loadFastMatch = Vec(params.LduCnt, Output(UInt(params.LduCnt.W))) 363 val loadFastImm = Vec(params.LduCnt, Output(UInt(12.W))) // Imm_I 364 365 val tlbCsr = Output(new TlbCsrBundle) 366 val csrCtrl = Output(new CustomCSRCtrlIO) 367 val sfence = Output(new SfenceBundle) 368 val isStoreException = Output(Bool()) 369} 370 371class BackendIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 372 val fromTop = new Bundle { 373 val hartId = Input(UInt(8.W)) 374 val externalInterrupt = new ExternalInterruptIO 375 } 376 377 val toTop = new Bundle { 378 val cpuHalted = Output(Bool()) 379 } 380 381 val fenceio = new FenceIO 382 // Todo: merge these bundles into BackendFrontendIO 383 val frontend = Flipped(new FrontendToCtrlIO) 384 val frontendSfence = Output(new SfenceBundle) 385 val frontendCsrCtrl = Output(new CustomCSRCtrlIO) 386 val frontendTlbCsr = Output(new TlbCsrBundle) 387 // distributed csr write 388 val frontendCsrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 389 390 val mem = new BackendMemIO 391 392 val perf = Input(new PerfCounterIO) 393 394 val tlb = Output(new TlbCsrBundle) 395 396 val csrCustomCtrl = Output(new CustomCSRCtrlIO) 397} 398