1package xiangshan.backend 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import utility.ZeroExt 8import xiangshan._ 9import xiangshan.backend.Bundles.{DynInst, IssueQueueIQWakeUpBundle, LoadShouldCancel, MemExuInput, MemExuOutput} 10import xiangshan.backend.ctrlblock.{DebugLSIO, LsTopdownInfo} 11import xiangshan.backend.datapath.DataConfig.{IntData, VecData} 12import xiangshan.backend.datapath.RdConfig.{IntRD, VfRD} 13import xiangshan.backend.datapath.WbConfig._ 14import xiangshan.backend.datapath._ 15import xiangshan.backend.dispatch.CoreDispatchTopDownIO 16import xiangshan.backend.exu.ExuBlock 17import xiangshan.backend.fu.vector.Bundles.{VConfig, VType} 18import xiangshan.backend.fu.{FenceIO, FenceToSbuffer, FuConfig, PerfCounterIO} 19import xiangshan.backend.issue.{CancelNetwork, Scheduler, SchedulerImpBase} 20import xiangshan.backend.rob.{RobCoreTopDownIO, RobDebugRollingIO, RobLsqIO} 21import xiangshan.frontend.{FtqPtr, FtqRead} 22import xiangshan.mem.{LqPtr, LsqEnqIO, SqPtr} 23 24class Backend(val params: BackendParams)(implicit p: Parameters) extends LazyModule 25 with HasXSParameter { 26 27 override def shouldBeInlined: Boolean = false 28 29 /* Only update the idx in mem-scheduler here 30 * Idx in other schedulers can be updated the same way if needed 31 * 32 * Also note that we filter out the 'stData issue-queues' when counting 33 */ 34 for ((ibp, idx) <- params.memSchdParams.get.issueBlockParams.filter(iq => iq.StdCnt == 0).zipWithIndex) { 35 ibp.updateIdx(idx) 36 } 37 38 println(params.iqWakeUpParams) 39 40 for ((schdCfg, i) <- params.allSchdParams.zipWithIndex) { 41 schdCfg.bindBackendParam(params) 42 } 43 44 for ((iqCfg, i) <- params.allIssueParams.zipWithIndex) { 45 iqCfg.bindBackendParam(params) 46 } 47 48 for ((exuCfg, i) <- params.allExuParams.zipWithIndex) { 49 exuCfg.bindBackendParam(params) 50 exuCfg.updateIQWakeUpConfigs(params.iqWakeUpParams) 51 exuCfg.updateExuIdx(i) 52 } 53 54 println("[Backend] ExuConfigs:") 55 for (exuCfg <- params.allExuParams) { 56 val fuConfigs = exuCfg.fuConfigs 57 val wbPortConfigs = exuCfg.wbPortConfigs 58 val immType = exuCfg.immType 59 60 println("[Backend] " + 61 s"${exuCfg.name}: " + 62 s"${fuConfigs.map(_.name).mkString("fu(s): {", ",", "}")}, " + 63 s"${wbPortConfigs.mkString("wb: {", ",", "}")}, " + 64 s"${immType.map(SelImm.mkString(_)).mkString("imm: {", ",", "}")}, " + 65 s"latMax(${exuCfg.latencyValMax}), ${exuCfg.fuLatancySet.mkString("lat: {", ",", "}")}, " 66 ) 67 require( 68 wbPortConfigs.collectFirst { case x: IntWB => x }.nonEmpty == 69 fuConfigs.map(_.writeIntRf).reduce(_ || _), 70 "int wb port has no priority" 71 ) 72 require( 73 wbPortConfigs.collectFirst { case x: VfWB => x }.nonEmpty == 74 fuConfigs.map(x => x.writeFpRf || x.writeVecRf).reduce(_ || _), 75 "vec wb port has no priority" 76 ) 77 } 78 79 println(s"[Backend] all fu configs") 80 for (cfg <- FuConfig.allConfigs) { 81 println(s"[Backend] $cfg") 82 } 83 84 println(s"[Backend] Int RdConfigs: ExuName(Priority)") 85 for ((port, seq) <- params.getRdPortParams(IntData())) { 86 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 87 } 88 89 println(s"[Backend] Int WbConfigs: ExuName(Priority)") 90 for ((port, seq) <- params.getWbPortParams(IntData())) { 91 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 92 } 93 94 println(s"[Backend] Vf RdConfigs: ExuName(Priority)") 95 for ((port, seq) <- params.getRdPortParams(VecData())) { 96 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 97 } 98 99 println(s"[Backend] Vf WbConfigs: ExuName(Priority)") 100 for ((port, seq) <- params.getWbPortParams(VecData())) { 101 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 102 } 103 104 val ctrlBlock = LazyModule(new CtrlBlock(params)) 105 val pcTargetMem = LazyModule(new PcTargetMem(params)) 106 val intScheduler = params.intSchdParams.map(x => LazyModule(new Scheduler(x))) 107 val vfScheduler = params.vfSchdParams.map(x => LazyModule(new Scheduler(x))) 108 val memScheduler = params.memSchdParams.map(x => LazyModule(new Scheduler(x))) 109 val cancelNetwork = LazyModule(new CancelNetwork(params)) 110 val dataPath = LazyModule(new DataPath(params)) 111 val intExuBlock = params.intSchdParams.map(x => LazyModule(new ExuBlock(x))) 112 val vfExuBlock = params.vfSchdParams.map(x => LazyModule(new ExuBlock(x))) 113 val wbFuBusyTable = LazyModule(new WbFuBusyTable(params)) 114 115 lazy val module = new BackendImp(this) 116} 117 118class BackendImp(override val wrapper: Backend)(implicit p: Parameters) extends LazyModuleImp(wrapper) 119 with HasXSParameter { 120 implicit private val params = wrapper.params 121 122 val io = IO(new BackendIO()(p, wrapper.params)) 123 124 private val ctrlBlock = wrapper.ctrlBlock.module 125 private val pcTargetMem = wrapper.pcTargetMem.module 126 private val intScheduler: SchedulerImpBase = wrapper.intScheduler.get.module 127 private val vfScheduler = wrapper.vfScheduler.get.module 128 private val memScheduler = wrapper.memScheduler.get.module 129 private val cancelNetwork = wrapper.cancelNetwork.module 130 private val dataPath = wrapper.dataPath.module 131 private val intExuBlock = wrapper.intExuBlock.get.module 132 private val vfExuBlock = wrapper.vfExuBlock.get.module 133 private val bypassNetwork = Module(new BypassNetwork) 134 private val wbDataPath = Module(new WbDataPath(params)) 135 private val wbFuBusyTable = wrapper.wbFuBusyTable.module 136 137 private val iqWakeUpMappedBundle: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = ( 138 intScheduler.io.toSchedulers.wakeupVec ++ 139 vfScheduler.io.toSchedulers.wakeupVec ++ 140 memScheduler.io.toSchedulers.wakeupVec 141 ).map(x => (x.bits.exuIdx, x)).toMap 142 143 println(s"[Backend] iq wake up keys: ${iqWakeUpMappedBundle.keys}") 144 145 wbFuBusyTable.io.in.intSchdBusyTable := intScheduler.io.wbFuBusyTable 146 wbFuBusyTable.io.in.vfSchdBusyTable := vfScheduler.io.wbFuBusyTable 147 wbFuBusyTable.io.in.memSchdBusyTable := memScheduler.io.wbFuBusyTable 148 intScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.intRespRead 149 vfScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.vfRespRead 150 memScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.memRespRead 151 dataPath.io.wbConfictRead := wbFuBusyTable.io.out.wbConflictRead 152 153 wbDataPath.io.fromIntExu.flatten.filter(x => x.bits.params.writeIntRf) 154 155 private val vconfig = dataPath.io.vconfigReadPort.data 156 private val og1CancelOH: UInt = dataPath.io.og1CancelOH 157 private val og0CancelOHFromDataPath: UInt = dataPath.io.og0CancelOH 158 private val og0CancelOHFromCancelNet: UInt = cancelNetwork.io.out.og0CancelOH 159 private val og0CancelOHFromFinalIssue: UInt = Wire(chiselTypeOf(dataPath.io.og0CancelOH)) 160 private val og0CancelOH: UInt = og0CancelOHFromDataPath | og0CancelOHFromCancelNet | og0CancelOHFromFinalIssue 161 private val cancelToBusyTable = dataPath.io.cancelToBusyTable 162 163 ctrlBlock.io.fromTop.hartId := io.fromTop.hartId 164 ctrlBlock.io.frontend <> io.frontend 165 ctrlBlock.io.fromWB.wbData <> wbDataPath.io.toCtrlBlock.writeback 166 ctrlBlock.io.fromMem.stIn <> io.mem.stIn 167 ctrlBlock.io.fromMem.violation <> io.mem.memoryViolation 168 ctrlBlock.io.lqCanAccept := io.mem.lqCanAccept 169 ctrlBlock.io.sqCanAccept := io.mem.sqCanAccept 170 ctrlBlock.io.csrCtrl <> intExuBlock.io.csrio.get.customCtrl 171 ctrlBlock.io.robio.csr.intrBitSet := intExuBlock.io.csrio.get.interrupt 172 ctrlBlock.io.robio.csr.trapTarget := intExuBlock.io.csrio.get.trapTarget 173 ctrlBlock.io.robio.csr.isXRet := intExuBlock.io.csrio.get.isXRet 174 ctrlBlock.io.robio.csr.wfiEvent := intExuBlock.io.csrio.get.wfi_event 175 ctrlBlock.io.robio.lsq <> io.mem.robLsqIO 176 ctrlBlock.io.robio.lsTopdownInfo <> io.mem.lsTopdownInfo 177 ctrlBlock.io.robio.debug_ls <> io.mem.debugLS 178 ctrlBlock.io.fromDataPath.vtype := vconfig(7, 0).asTypeOf(new VType) 179 ctrlBlock.perfinfo := DontCare // TODO: Implement backend hpm 180 ctrlBlock.io.debugEnqLsq.canAccept := io.mem.lsqEnqIO.canAccept 181 ctrlBlock.io.debugEnqLsq.resp := io.mem.lsqEnqIO.resp 182 ctrlBlock.io.debugEnqLsq.req := memScheduler.io.memIO.get.lsqEnqIO.req 183 ctrlBlock.io.debugEnqLsq.needAlloc := memScheduler.io.memIO.get.lsqEnqIO.needAlloc 184 185 186 intScheduler.io.fromTop.hartId := io.fromTop.hartId 187 intScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 188 intScheduler.io.fromCtrlBlock.pcVec := ctrlBlock.io.toIssueBlock.pcVec 189 intScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 190 intScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.intUops 191 intScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 192 intScheduler.io.vfWriteBack := 0.U.asTypeOf(intScheduler.io.vfWriteBack) 193 intScheduler.io.fromDataPath.resp := dataPath.io.toIntIQ 194 intScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 195 intScheduler.io.fromDataPath.og0Cancel := og0CancelOH 196 intScheduler.io.fromDataPath.og1Cancel := og1CancelOH 197 intScheduler.io.ldCancel := io.mem.ldCancel 198 intScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 199 200 memScheduler.io.fromTop.hartId := io.fromTop.hartId 201 memScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 202 memScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 203 memScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.memUops 204 memScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 205 memScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 206 memScheduler.io.fromMem.get.scommit := io.mem.sqDeq 207 memScheduler.io.fromMem.get.lcommit := io.mem.lqDeq 208 memScheduler.io.fromMem.get.sqCancelCnt := io.mem.sqCancelCnt 209 memScheduler.io.fromMem.get.lqCancelCnt := io.mem.lqCancelCnt 210 memScheduler.io.fromMem.get.stIssuePtr := io.mem.stIssuePtr 211 memScheduler.io.fromMem.get.memWaitUpdateReq.robIdx.zip(io.mem.stIn).foreach { case (sink, source) => 212 sink.valid := source.valid 213 sink.bits := source.bits.robIdx 214 } 215 memScheduler.io.fromMem.get.memWaitUpdateReq.sqIdx := DontCare // TODO 216 memScheduler.io.fromDataPath.resp := dataPath.io.toMemIQ 217 memScheduler.io.fromMem.get.ldaFeedback := io.mem.ldaIqFeedback 218 memScheduler.io.fromMem.get.staFeedback := io.mem.staIqFeedback 219 memScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 220 memScheduler.io.fromDataPath.og0Cancel := og0CancelOH 221 memScheduler.io.fromDataPath.og1Cancel := og1CancelOH 222 memScheduler.io.ldCancel := io.mem.ldCancel 223 memScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 224 225 vfScheduler.io.fromTop.hartId := io.fromTop.hartId 226 vfScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 227 vfScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 228 vfScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.vfUops 229 vfScheduler.io.intWriteBack := 0.U.asTypeOf(vfScheduler.io.intWriteBack) 230 vfScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 231 vfScheduler.io.fromDataPath.resp := dataPath.io.toVfIQ 232 vfScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 233 vfScheduler.io.fromDataPath.og0Cancel := og0CancelOH 234 vfScheduler.io.fromDataPath.og1Cancel := og1CancelOH 235 vfScheduler.io.ldCancel := io.mem.ldCancel 236 vfScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 237 238 cancelNetwork.io.in.int <> intScheduler.io.toDataPath 239 cancelNetwork.io.in.vf <> vfScheduler.io.toDataPath 240 cancelNetwork.io.in.mem <> memScheduler.io.toDataPath 241 cancelNetwork.io.in.og0CancelOH := og0CancelOHFromDataPath | og0CancelOHFromFinalIssue 242 cancelNetwork.io.in.og1CancelOH := og1CancelOH 243 intScheduler.io.fromCancelNetwork <> cancelNetwork.io.out.int 244 vfScheduler.io.fromCancelNetwork <> cancelNetwork.io.out.vf 245 memScheduler.io.fromCancelNetwork <> cancelNetwork.io.out.mem 246 247 dataPath.io.hartId := io.fromTop.hartId 248 dataPath.io.flush := ctrlBlock.io.toDataPath.flush 249 dataPath.io.vconfigReadPort.addr := ctrlBlock.io.toDataPath.vtypeAddr 250 251 dataPath.io.fromIntIQ <> intScheduler.io.toDataPathAfterDelay 252 dataPath.io.fromVfIQ <> vfScheduler.io.toDataPathAfterDelay 253 dataPath.io.fromMemIQ <> memScheduler.io.toDataPathAfterDelay 254 255 dataPath.io.ldCancel := io.mem.ldCancel 256 257 println(s"[Backend] wbDataPath.io.toIntPreg: ${wbDataPath.io.toIntPreg.size}, dataPath.io.fromIntWb: ${dataPath.io.fromIntWb.size}") 258 println(s"[Backend] wbDataPath.io.toVfPreg: ${wbDataPath.io.toVfPreg.size}, dataPath.io.fromFpWb: ${dataPath.io.fromVfWb.size}") 259 dataPath.io.fromIntWb := wbDataPath.io.toIntPreg 260 dataPath.io.fromVfWb := wbDataPath.io.toVfPreg 261 dataPath.io.debugIntRat .foreach(_ := ctrlBlock.io.debug_int_rat.get) 262 dataPath.io.debugFpRat .foreach(_ := ctrlBlock.io.debug_fp_rat.get) 263 dataPath.io.debugVecRat .foreach(_ := ctrlBlock.io.debug_vec_rat.get) 264 dataPath.io.debugVconfigRat.foreach(_ := ctrlBlock.io.debug_vconfig_rat.get) 265 266 bypassNetwork.io.fromDataPath.int <> dataPath.io.toIntExu 267 bypassNetwork.io.fromDataPath.vf <> dataPath.io.toFpExu 268 bypassNetwork.io.fromDataPath.mem <> dataPath.io.toMemExu 269 bypassNetwork.io.fromExus.connectExuOutput(_.int)(intExuBlock.io.out) 270 bypassNetwork.io.fromExus.connectExuOutput(_.vf)(vfExuBlock.io.out) 271 bypassNetwork.io.fromExus.mem.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 272 sink.valid := source.valid 273 sink.bits.pdest := source.bits.uop.pdest 274 sink.bits.data := source.bits.data 275 } 276 277 278 intExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 279 for (i <- 0 until intExuBlock.io.in.length) { 280 for (j <- 0 until intExuBlock.io.in(i).length) { 281 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.int(i)(j).bits.loadDependency, io.mem.ldCancel) 282 NewPipelineConnect( 283 bypassNetwork.io.toExus.int(i)(j), intExuBlock.io.in(i)(j), intExuBlock.io.in(i)(j).fire, 284 Mux( 285 bypassNetwork.io.toExus.int(i)(j).fire, 286 bypassNetwork.io.toExus.int(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 287 intExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 288 ) 289 ) 290 } 291 } 292 293 pcTargetMem.io.fromFrontendFtq := io.frontend.fromFtq 294 pcTargetMem.io.fromDataPathFtq := bypassNetwork.io.toExus.int.flatten.filter(_.bits.params.hasPredecode).map(_.bits.ftqIdx.get).toSeq 295 intExuBlock.io.in.flatten.filter(_.bits.params.hasPredecode).map(_.bits.predictInfo.get.target).zipWithIndex.foreach { 296 case (sink, i) => 297 sink := pcTargetMem.io.toExus(i) 298 } 299 300 private val csrio = intExuBlock.io.csrio.get 301 csrio.hartId := io.fromTop.hartId 302 csrio.fpu.fflags := ctrlBlock.io.robio.csr.fflags 303 csrio.fpu.isIllegal := false.B // Todo: remove it 304 csrio.fpu.dirty_fs := ctrlBlock.io.robio.csr.dirty_fs 305 csrio.vpu <> 0.U.asTypeOf(csrio.vpu) // Todo 306 307 val debugVconfig = dataPath.io.debugVconfig.get.asTypeOf(new VConfig) 308 val debugVtype = VType.toVtypeStruct(debugVconfig.vtype).asUInt 309 val debugVl = debugVconfig.vl 310 csrio.vpu.set_vxsat := ctrlBlock.io.robio.csr.vxsat 311 csrio.vpu.set_vstart.valid := ctrlBlock.io.robio.csr.vcsrFlag 312 csrio.vpu.set_vstart.bits := 0.U 313 csrio.vpu.set_vtype.valid := ctrlBlock.io.robio.csr.vcsrFlag 314 //Todo here need change design 315 csrio.vpu.set_vtype.bits := ZeroExt(debugVtype, XLEN) 316 csrio.vpu.set_vl.valid := ctrlBlock.io.robio.csr.vcsrFlag 317 csrio.vpu.set_vl.bits := ZeroExt(debugVl, XLEN) 318 csrio.exception := ctrlBlock.io.robio.exception 319 csrio.memExceptionVAddr := io.mem.exceptionVAddr 320 csrio.externalInterrupt := io.fromTop.externalInterrupt 321 csrio.distributedUpdate(0) := io.mem.csrDistributedUpdate 322 csrio.distributedUpdate(1) := io.frontendCsrDistributedUpdate 323 csrio.perf <> io.perf 324 csrio.perf.retiredInstr <> ctrlBlock.io.robio.csr.perfinfo.retiredInstr 325 csrio.perf.ctrlInfo <> ctrlBlock.io.perfInfo.ctrlInfo 326 csrio.perf.perfEventsCtrl <> ctrlBlock.getPerf 327 private val fenceio = intExuBlock.io.fenceio.get 328 io.fenceio <> fenceio 329 fenceio.disableSfence := csrio.disableSfence 330 331 vfExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 332 for (i <- 0 until vfExuBlock.io.in.size) { 333 for (j <- 0 until vfExuBlock.io.in(i).size) { 334 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.vf(i)(j).bits.loadDependency, io.mem.ldCancel) 335 NewPipelineConnect( 336 bypassNetwork.io.toExus.vf(i)(j), vfExuBlock.io.in(i)(j), vfExuBlock.io.in(i)(j).fire, 337 Mux( 338 bypassNetwork.io.toExus.vf(i)(j).fire, 339 bypassNetwork.io.toExus.vf(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 340 vfExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 341 ) 342 ) 343 344 vfExuBlock.io.in(i)(j).bits.vpu.foreach(_.vstart := csrio.vpu.vstart) 345 } 346 } 347 348 intExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 349 vfExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 350 351 wbDataPath.io.flush := ctrlBlock.io.redirect 352 wbDataPath.io.fromTop.hartId := io.fromTop.hartId 353 wbDataPath.io.fromIntExu <> intExuBlock.io.out 354 wbDataPath.io.fromVfExu <> vfExuBlock.io.out 355 wbDataPath.io.fromMemExu.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 356 sink.valid := source.valid 357 source.ready := sink.ready 358 sink.bits.data := source.bits.data 359 sink.bits.pdest := source.bits.uop.pdest 360 sink.bits.robIdx := source.bits.uop.robIdx 361 sink.bits.intWen.foreach(_ := source.bits.uop.rfWen) 362 sink.bits.fpWen.foreach(_ := source.bits.uop.fpWen) 363 sink.bits.vecWen.foreach(_ := source.bits.uop.vecWen) 364 sink.bits.exceptionVec.foreach(_ := source.bits.uop.exceptionVec) 365 sink.bits.flushPipe.foreach(_ := source.bits.uop.flushPipe) 366 sink.bits.replay.foreach(_ := source.bits.uop.replayInst) 367 sink.bits.debug := source.bits.debug 368 sink.bits.debugInfo := source.bits.uop.debugInfo 369 sink.bits.lqIdx.foreach(_ := source.bits.uop.lqIdx) 370 sink.bits.sqIdx.foreach(_ := source.bits.uop.sqIdx) 371 } 372 373 // to mem 374 private val memIssueParams = params.memSchdParams.get.issueBlockParams 375 private val memExuBlocksHasLDU = memIssueParams.map(_.exuBlockParams.map(_.fuConfigs.contains(FuConfig.LduCfg))) 376 println(s"[Backend] memExuBlocksHasLDU: $memExuBlocksHasLDU") 377 378 private val toMem = Wire(bypassNetwork.io.toExus.mem.cloneType) 379 for (i <- toMem.indices) { 380 for (j <- toMem(i).indices) { 381 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.mem(i)(j).bits.loadDependency, io.mem.ldCancel) 382 val issueTimeout = 383 if (memExuBlocksHasLDU(i)(j)) 384 Counter(0 until 16, toMem(i)(j).valid && !toMem(i)(j).fire, bypassNetwork.io.toExus.mem(i)(j).fire)._2 385 else 386 false.B 387 388 if (memScheduler.io.loadFinalIssueResp(i).nonEmpty) { 389 memScheduler.io.loadFinalIssueResp(i)(j).valid := issueTimeout 390 memScheduler.io.loadFinalIssueResp(i)(j).bits.dataInvalidSqIdx := DontCare 391 memScheduler.io.loadFinalIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType 392 memScheduler.io.loadFinalIssueResp(i)(j).bits.respType := RSFeedbackType.fuBusy 393 memScheduler.io.loadFinalIssueResp(i)(j).bits.rfWen := toMem(i)(j).bits.rfWen.getOrElse(false.B) 394 memScheduler.io.loadFinalIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx 395 } 396 397 NewPipelineConnect( 398 bypassNetwork.io.toExus.mem(i)(j), toMem(i)(j), toMem(i)(j).fire, 399 Mux( 400 bypassNetwork.io.toExus.mem(i)(j).fire, 401 bypassNetwork.io.toExus.mem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 402 toMem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || issueTimeout 403 ) 404 ) 405 406 if (memScheduler.io.memAddrIssueResp(i).nonEmpty) { 407 memScheduler.io.memAddrIssueResp(i)(j).valid := toMem(i)(j).fire 408 memScheduler.io.memAddrIssueResp(i)(j).bits.dataInvalidSqIdx := DontCare 409 memScheduler.io.memAddrIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType 410 memScheduler.io.memAddrIssueResp(i)(j).bits.respType := RSFeedbackType.fuIdle 411 memScheduler.io.memAddrIssueResp(i)(j).bits.rfWen := toMem(i)(j).bits.rfWen.getOrElse(false.B) 412 memScheduler.io.memAddrIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx 413 } 414 } 415 } 416 417 io.mem.redirect := ctrlBlock.io.redirect 418 private val memIssueUops = io.mem.issueLda ++ io.mem.issueHya ++ io.mem.issueSta ++ io.mem.issueStd ++ io.mem.issueHyd ++ io.mem.issueVldu 419 memIssueUops.zip(toMem.flatten).foreach { case (sink, source) => 420 sink.valid := source.valid 421 source.ready := sink.ready 422 sink.bits.iqIdx := source.bits.iqIdx 423 sink.bits.isFirstIssue := source.bits.isFirstIssue 424 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 425 sink.bits.src := 0.U.asTypeOf(sink.bits.src) 426 sink.bits.src.zip(source.bits.src).foreach { case (l, r) => l := r} 427 sink.bits.deqPortIdx := source.bits.deqPortIdx.getOrElse(0.U) 428 sink.bits.uop.fuType := source.bits.fuType 429 sink.bits.uop.fuOpType := source.bits.fuOpType 430 sink.bits.uop.imm := source.bits.imm 431 sink.bits.uop.robIdx := source.bits.robIdx 432 sink.bits.uop.pdest := source.bits.pdest 433 sink.bits.uop.rfWen := source.bits.rfWen.getOrElse(false.B) 434 sink.bits.uop.fpWen := source.bits.fpWen.getOrElse(false.B) 435 sink.bits.uop.vecWen := source.bits.vecWen.getOrElse(false.B) 436 sink.bits.uop.flushPipe := source.bits.flushPipe.getOrElse(false.B) 437 sink.bits.uop.pc := source.bits.pc.getOrElse(0.U) 438 sink.bits.uop.lqIdx := source.bits.lqIdx.getOrElse(0.U.asTypeOf(new LqPtr)) 439 sink.bits.uop.sqIdx := source.bits.sqIdx.getOrElse(0.U.asTypeOf(new SqPtr)) 440 sink.bits.uop.ftqPtr := source.bits.ftqIdx.getOrElse(0.U.asTypeOf(new FtqPtr)) 441 sink.bits.uop.ftqOffset := source.bits.ftqOffset.getOrElse(0.U) 442 sink.bits.uop.debugInfo := source.bits.perfDebugInfo 443 } 444 io.mem.loadFastMatch := memScheduler.io.toMem.get.loadFastMatch.map(_.fastMatch) 445 io.mem.loadFastImm := memScheduler.io.toMem.get.loadFastMatch.map(_.fastImm) 446 io.mem.tlbCsr := csrio.tlb 447 io.mem.csrCtrl := csrio.customCtrl 448 io.mem.sfence := fenceio.sfence 449 io.mem.isStoreException := CommitType.lsInstIsStore(ctrlBlock.io.robio.exception.bits.commitType) 450 require(io.mem.loadPcRead.size == params.LduCnt) 451 io.mem.loadPcRead.zipWithIndex.foreach { case (loadPcRead, i) => 452 loadPcRead := ctrlBlock.io.memLdPcRead(i).data 453 ctrlBlock.io.memLdPcRead(i).ptr := io.mem.issueLda(i).bits.uop.ftqPtr 454 ctrlBlock.io.memLdPcRead(i).offset := io.mem.issueLda(i).bits.uop.ftqOffset 455 require(toMem.head(i).bits.ftqIdx.isDefined && toMem.head(i).bits.ftqOffset.isDefined) 456 } 457 458 io.mem.storePcRead.zipWithIndex.foreach { case (storePcRead, i) => 459 storePcRead := ctrlBlock.io.memStPcRead(i).data 460 ctrlBlock.io.memStPcRead(i).ptr := io.mem.issueSta(i).bits.uop.ftqPtr 461 ctrlBlock.io.memStPcRead(i).offset := io.mem.issueSta(i).bits.uop.ftqOffset 462 require(toMem(1)(i).bits.ftqIdx.isDefined && toMem(1)(i).bits.ftqOffset.isDefined) 463 } 464 465 io.mem.hyuPcRead.zipWithIndex.foreach( { case (hyuPcRead, i) => 466 hyuPcRead := ctrlBlock.io.memHyPcRead(i).data 467 ctrlBlock.io.memHyPcRead(i).ptr := io.mem.issueHya(i).bits.uop.ftqPtr 468 ctrlBlock.io.memHyPcRead(i).offset := io.mem.issueHya(i).bits.uop.ftqOffset 469 require(toMem(2)(i).bits.ftqIdx.isDefined && toMem(2)(i).bits.ftqOffset.isDefined) 470 }) 471 472 ctrlBlock.io.robio.robHeadLsIssue := io.mem.issueUops.map(deq => deq.fire && deq.bits.uop.robIdx === ctrlBlock.io.robio.robDeqPtr).reduce(_ || _) 473 474 // mem io 475 io.mem.lsqEnqIO <> memScheduler.io.memIO.get.lsqEnqIO 476 io.mem.robLsqIO <> ctrlBlock.io.robio.lsq 477 478 private val intFinalIssueBlock = intExuBlock.io.in.flatten.toSeq.map(_ => false.B) 479 private val vfFinalIssueBlock = vfExuBlock.io.in.flatten.toSeq.map(_ => false.B) 480 private val memFinalIssueBlock = io.mem.issueUops.toSeq zip memExuBlocksHasLDU.flatten.toSeq map { 481 case (out, true) => RegNext(out.valid && !out.ready, false.B) 482 case (_, false) => false.B 483 } 484 println(s"[backend]: width of [int|vf|mem]FinalIssueBlock: ${intFinalIssueBlock.size}|${vfFinalIssueBlock.size}|${memFinalIssueBlock.size}") 485 og0CancelOHFromFinalIssue := VecInit(intFinalIssueBlock ++ vfFinalIssueBlock ++ memFinalIssueBlock).asUInt 486 487 io.frontendSfence := fenceio.sfence 488 io.frontendTlbCsr := csrio.tlb 489 io.frontendCsrCtrl := csrio.customCtrl 490 491 io.tlb <> csrio.tlb 492 493 io.csrCustomCtrl := csrio.customCtrl 494 495 io.toTop.cpuHalted := false.B // TODO: implement cpu halt 496 497 io.debugTopDown.fromRob := ctrlBlock.io.debugTopDown.fromRob 498 ctrlBlock.io.debugTopDown.fromCore := io.debugTopDown.fromCore 499 500 io.debugRolling := ctrlBlock.io.debugRolling 501 502 dontTouch(memScheduler.io) 503 dontTouch(dataPath.io.toMemExu) 504 dontTouch(wbDataPath.io.fromMemExu) 505} 506 507class BackendMemIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 508 // Since fast load replay always use load unit 0, Backend flips two load port to avoid conflicts 509 val flippedLda = true 510 // params alias 511 private val LoadQueueSize = VirtualLoadQueueSize 512 // In/Out // Todo: split it into one-direction bundle 513 val lsqEnqIO = Flipped(new LsqEnqIO) 514 val robLsqIO = new RobLsqIO 515 val ldaIqFeedback = Vec(params.LduCnt, Flipped(new MemRSFeedbackIO)) 516 val staIqFeedback = Vec(params.StaCnt, Flipped(new MemRSFeedbackIO)) 517 val ldCancel = Vec(params.LduCnt, Flipped(new LoadCancelIO)) 518 val loadPcRead = Vec(params.LduCnt, Output(UInt(VAddrBits.W))) 519 val storePcRead = Vec(params.StaCnt, Output(UInt(VAddrBits.W))) 520 val hyuPcRead = Vec(params.HyuCnt, Output(UInt(VAddrBits.W))) 521 // Input 522 val writebackLdas = MixedVec(Seq.fill(params.LduCnt)(Flipped(DecoupledIO(new MemExuOutput())))) 523 val writebackStas = MixedVec(Seq.fill(params.StaCnt)(Flipped(DecoupledIO(new MemExuOutput())))) 524 val writebackStds = MixedVec(Seq.fill(params.StdCnt)(Flipped(DecoupledIO(new MemExuOutput())))) 525 val writebackVldus = MixedVec(Seq.fill(params.VlduCnt)(Flipped(DecoupledIO(new MemExuOutput(true))))) 526 527 val s3_delayed_load_error = Input(Vec(LoadPipelineWidth, Bool())) 528 val stIn = Input(Vec(params.StaCnt, ValidIO(new DynInst()))) 529 val memoryViolation = Flipped(ValidIO(new Redirect)) 530 val exceptionVAddr = Input(UInt(VAddrBits.W)) 531 val sqDeq = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) 532 val lqDeq = Input(UInt(log2Up(CommitWidth + 1).W)) 533 534 val lqCancelCnt = Input(UInt(log2Up(VirtualLoadQueueSize + 1).W)) 535 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 536 537 val lqCanAccept = Input(Bool()) 538 val sqCanAccept = Input(Bool()) 539 540 val otherFastWakeup = Flipped(Vec(params.LduCnt + params.HyuCnt, ValidIO(new DynInst))) 541 val stIssuePtr = Input(new SqPtr()) 542 543 val csrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 544 545 val debugLS = Flipped(Output(new DebugLSIO)) 546 547 val lsTopdownInfo = Vec(params.LduCnt, Flipped(Output(new LsTopdownInfo))) 548 // Output 549 val redirect = ValidIO(new Redirect) // rob flush MemBlock 550 val issueLda = MixedVec(Seq.fill(params.LduCnt)(DecoupledIO(new MemExuInput()))) 551 val issueSta = MixedVec(Seq.fill(params.StaCnt)(DecoupledIO(new MemExuInput()))) 552 val issueStd = MixedVec(Seq.fill(params.StaCnt)(DecoupledIO(new MemExuInput()))) 553 val issueHya = MixedVec(Seq.fill(params.HyuCnt)(DecoupledIO(new MemExuInput()))) 554 val issueHyd = MixedVec(Seq.fill(params.HyuCnt)(DecoupledIO(new MemExuInput()))) 555 val issueVldu = MixedVec(Seq.fill(params.VlduCnt)(DecoupledIO(new MemExuInput(isVector = true)))) 556 def issueUops = issueLda ++ issueSta ++ issueStd ++ issueHya ++ issueHyd ++ issueVldu 557 558 val loadFastMatch = Vec(params.LduCnt, Output(UInt(params.LduCnt.W))) 559 val loadFastImm = Vec(params.LduCnt, Output(UInt(12.W))) // Imm_I 560 561 val tlbCsr = Output(new TlbCsrBundle) 562 val csrCtrl = Output(new CustomCSRCtrlIO) 563 val sfence = Output(new SfenceBundle) 564 val isStoreException = Output(Bool()) 565 566 // make this function private to avoid flip twice, both in Backend and XSCore 567 private [backend] def issueUops: Seq[DecoupledIO[MemExuInput]] = { 568 val issLdas = if (flippedLda) Seq(issueLdas(1), issueLdas(0)) else issueLdas 569 (issLdas ++ issueStas ++ issueStds ++ issueVldus).toSeq 570 } 571 572 // make this function private to avoid flip twice, both in Backend and XSCore 573 private [backend] def writeBack: Seq[DecoupledIO[MemExuOutput]] = { 574 val wbLdas = if (flippedLda) Seq(writebackLdas(1), writebackLdas(0)) else writebackLdas 575 (wbLdas ++ writebackStas ++ writebackStds ++ writebackVldus).toSeq 576 } 577 578 def issueUopsToMem: Seq[DecoupledIO[MemExuInput]] = { 579 (issueLdas ++ issueStas ++ issueStds ++ issueVldus).toSeq 580 } 581 582 def writeBackToBackend: Seq[DecoupledIO[MemExuOutput]] = { 583 (writebackLdas ++ writebackStas ++ writebackStds ++ writebackVldus).toSeq 584 } 585} 586 587class BackendIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 588 val fromTop = new Bundle { 589 val hartId = Input(UInt(8.W)) 590 val externalInterrupt = new ExternalInterruptIO 591 } 592 593 val toTop = new Bundle { 594 val cpuHalted = Output(Bool()) 595 } 596 597 val fenceio = new FenceIO 598 // Todo: merge these bundles into BackendFrontendIO 599 val frontend = Flipped(new FrontendToCtrlIO) 600 val frontendSfence = Output(new SfenceBundle) 601 val frontendCsrCtrl = Output(new CustomCSRCtrlIO) 602 val frontendTlbCsr = Output(new TlbCsrBundle) 603 // distributed csr write 604 val frontendCsrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 605 606 val mem = new BackendMemIO 607 608 val perf = Input(new PerfCounterIO) 609 610 val tlb = Output(new TlbCsrBundle) 611 612 val csrCustomCtrl = Output(new CustomCSRCtrlIO) 613 614 val debugTopDown = new Bundle { 615 val fromRob = new RobCoreTopDownIO 616 val fromCore = new CoreDispatchTopDownIO 617 } 618 val debugRolling = new RobDebugRollingIO 619} 620