1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import device.MsiInfoBundle 23import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 24import system.HasSoCParameter 25import utility.{Constantin, ZeroExt} 26import utils.{HPerfMonitor, HasPerfEvents, PerfEvent} 27import xiangshan._ 28import xiangshan.backend.Bundles.{DynInst, IssueQueueIQWakeUpBundle, LoadShouldCancel, MemExuInput, MemExuOutput, VPUCtrlSignals} 29import xiangshan.backend.ctrlblock.{DebugLSIO, LsTopdownInfo} 30import xiangshan.backend.datapath.DataConfig.{IntData, VecData, FpData} 31import xiangshan.backend.datapath.RdConfig.{IntRD, VfRD} 32import xiangshan.backend.datapath.WbConfig._ 33import xiangshan.backend.datapath.DataConfig._ 34import xiangshan.backend.datapath._ 35import xiangshan.backend.dispatch.CoreDispatchTopDownIO 36import xiangshan.backend.exu.ExuBlock 37import xiangshan.backend.fu.vector.Bundles.{VConfig, VType} 38import xiangshan.backend.fu.{FenceIO, FenceToSbuffer, FuConfig, FuType, PFEvent, PerfCounterIO} 39import xiangshan.backend.issue.EntryBundles._ 40import xiangshan.backend.issue.{CancelNetwork, Scheduler, SchedulerArithImp, SchedulerImpBase, SchedulerMemImp} 41import xiangshan.backend.rob.{RobCoreTopDownIO, RobDebugRollingIO, RobLsqIO, RobPtr} 42import xiangshan.frontend.{FtqPtr, FtqRead, PreDecodeInfo} 43import xiangshan.mem.{LqPtr, LsqEnqIO, SqPtr} 44 45import scala.collection.mutable 46 47class Backend(val params: BackendParams)(implicit p: Parameters) extends LazyModule 48 with HasXSParameter { 49 50 override def shouldBeInlined: Boolean = false 51 52 // check read & write port config 53 params.configChecks 54 55 /* Only update the idx in mem-scheduler here 56 * Idx in other schedulers can be updated the same way if needed 57 * 58 * Also note that we filter out the 'stData issue-queues' when counting 59 */ 60 for ((ibp, idx) <- params.memSchdParams.get.issueBlockParams.filter(iq => iq.StdCnt == 0).zipWithIndex) { 61 ibp.updateIdx(idx) 62 } 63 64 println(params.iqWakeUpParams) 65 66 for ((schdCfg, i) <- params.allSchdParams.zipWithIndex) { 67 schdCfg.bindBackendParam(params) 68 } 69 70 for ((iqCfg, i) <- params.allIssueParams.zipWithIndex) { 71 iqCfg.bindBackendParam(params) 72 } 73 74 for ((exuCfg, i) <- params.allExuParams.zipWithIndex) { 75 exuCfg.bindBackendParam(params) 76 exuCfg.updateIQWakeUpConfigs(params.iqWakeUpParams) 77 exuCfg.updateExuIdx(i) 78 } 79 80 println("[Backend] ExuConfigs:") 81 for (exuCfg <- params.allExuParams) { 82 val fuConfigs = exuCfg.fuConfigs 83 val wbPortConfigs = exuCfg.wbPortConfigs 84 val immType = exuCfg.immType 85 86 println("[Backend] " + 87 s"${exuCfg.name}: " + 88 (if (exuCfg.fakeUnit) "fake, " else "") + 89 (if (exuCfg.hasLoadFu || exuCfg.hasHyldaFu) s"LdExuIdx(${backendParams.getLdExuIdx(exuCfg)})" else "") + 90 s"${fuConfigs.map(_.name).mkString("fu(s): {", ",", "}")}, " + 91 s"${wbPortConfigs.mkString("wb: {", ",", "}")}, " + 92 s"${immType.map(SelImm.mkString(_)).mkString("imm: {", ",", "}")}, " + 93 s"latMax(${exuCfg.latencyValMax}), ${exuCfg.fuLatancySet.mkString("lat: {", ",", "}")}, " + 94 s"srcReg(${exuCfg.numRegSrc})" 95 ) 96 require( 97 wbPortConfigs.collectFirst { case x: IntWB => x }.nonEmpty == 98 fuConfigs.map(_.writeIntRf).reduce(_ || _), 99 s"${exuCfg.name} int wb port has no priority" 100 ) 101 require( 102 wbPortConfigs.collectFirst { case x: FpWB => x }.nonEmpty == 103 fuConfigs.map(x => x.writeFpRf).reduce(_ || _), 104 s"${exuCfg.name} fp wb port has no priority" 105 ) 106 require( 107 wbPortConfigs.collectFirst { case x: VfWB => x }.nonEmpty == 108 fuConfigs.map(x => x.writeVecRf).reduce(_ || _), 109 s"${exuCfg.name} vec wb port has no priority" 110 ) 111 } 112 113 println(s"[Backend] all fu configs") 114 for (cfg <- FuConfig.allConfigs) { 115 println(s"[Backend] $cfg") 116 } 117 118 println(s"[Backend] Int RdConfigs: ExuName(Priority)") 119 for ((port, seq) <- params.getRdPortParams(IntData())) { 120 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 121 } 122 123 println(s"[Backend] Int WbConfigs: ExuName(Priority)") 124 for ((port, seq) <- params.getWbPortParams(IntData())) { 125 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 126 } 127 128 println(s"[Backend] Fp RdConfigs: ExuName(Priority)") 129 for ((port, seq) <- params.getRdPortParams(FpData())) { 130 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 131 } 132 133 println(s"[Backend] Fp WbConfigs: ExuName(Priority)") 134 for ((port, seq) <- params.getWbPortParams(FpData())) { 135 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 136 } 137 138 println(s"[Backend] Vf RdConfigs: ExuName(Priority)") 139 for ((port, seq) <- params.getRdPortParams(VecData())) { 140 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 141 } 142 143 println(s"[Backend] Vf WbConfigs: ExuName(Priority)") 144 for ((port, seq) <- params.getWbPortParams(VecData())) { 145 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 146 } 147 148 println(s"[Backend] Dispatch Configs:") 149 println(s"[Backend] Load IQ enq width(${params.numLoadDp}), Store IQ enq width(${params.numStoreDp})") 150 println(s"[Backend] Load DP width(${LSQLdEnqWidth}), Store DP width(${LSQStEnqWidth})") 151 152 params.updateCopyPdestInfo 153 println(s"[Backend] copyPdestInfo ${params.copyPdestInfo}") 154 params.allExuParams.map(_.copyNum) 155 val ctrlBlock = LazyModule(new CtrlBlock(params)) 156 val pcTargetMem = LazyModule(new PcTargetMem(params)) 157 val intScheduler = params.intSchdParams.map(x => LazyModule(new Scheduler(x))) 158 val fpScheduler = params.fpSchdParams.map(x => LazyModule(new Scheduler(x))) 159 val vfScheduler = params.vfSchdParams.map(x => LazyModule(new Scheduler(x))) 160 val memScheduler = params.memSchdParams.map(x => LazyModule(new Scheduler(x))) 161 val dataPath = LazyModule(new DataPath(params)) 162 val intExuBlock = params.intSchdParams.map(x => LazyModule(new ExuBlock(x))) 163 val fpExuBlock = params.fpSchdParams.map(x => LazyModule(new ExuBlock(x))) 164 val vfExuBlock = params.vfSchdParams.map(x => LazyModule(new ExuBlock(x))) 165 val wbFuBusyTable = LazyModule(new WbFuBusyTable(params)) 166 167 lazy val module = new BackendImp(this) 168} 169 170class BackendImp(override val wrapper: Backend)(implicit p: Parameters) extends LazyModuleImp(wrapper) 171 with HasXSParameter 172 with HasPerfEvents { 173 implicit private val params: BackendParams = wrapper.params 174 175 val io = IO(new BackendIO()(p, wrapper.params)) 176 177 private val ctrlBlock = wrapper.ctrlBlock.module 178 private val pcTargetMem = wrapper.pcTargetMem.module 179 private val intScheduler: SchedulerImpBase = wrapper.intScheduler.get.module 180 private val fpScheduler = wrapper.fpScheduler.get.module 181 private val vfScheduler = wrapper.vfScheduler.get.module 182 private val memScheduler = wrapper.memScheduler.get.module 183 private val dataPath = wrapper.dataPath.module 184 private val intExuBlock = wrapper.intExuBlock.get.module 185 private val fpExuBlock = wrapper.fpExuBlock.get.module 186 private val vfExuBlock = wrapper.vfExuBlock.get.module 187 private val og2ForVector = Module(new Og2ForVector(params)) 188 private val bypassNetwork = Module(new BypassNetwork) 189 private val wbDataPath = Module(new WbDataPath(params)) 190 private val wbFuBusyTable = wrapper.wbFuBusyTable.module 191 192 private val iqWakeUpMappedBundle: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = ( 193 intScheduler.io.toSchedulers.wakeupVec ++ 194 fpScheduler.io.toSchedulers.wakeupVec ++ 195 vfScheduler.io.toSchedulers.wakeupVec ++ 196 memScheduler.io.toSchedulers.wakeupVec 197 ).map(x => (x.bits.exuIdx, x)).toMap 198 199 println(s"[Backend] iq wake up keys: ${iqWakeUpMappedBundle.keys}") 200 201 wbFuBusyTable.io.in.intSchdBusyTable := intScheduler.io.wbFuBusyTable 202 wbFuBusyTable.io.in.fpSchdBusyTable := fpScheduler.io.wbFuBusyTable 203 wbFuBusyTable.io.in.vfSchdBusyTable := vfScheduler.io.wbFuBusyTable 204 wbFuBusyTable.io.in.memSchdBusyTable := memScheduler.io.wbFuBusyTable 205 intScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.intRespRead 206 fpScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.fpRespRead 207 vfScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.vfRespRead 208 memScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.memRespRead 209 dataPath.io.wbConfictRead := wbFuBusyTable.io.out.wbConflictRead 210 211 private val og1Cancel = dataPath.io.og1Cancel 212 private val og0Cancel = dataPath.io.og0Cancel 213 private val vlIsZero = intExuBlock.io.vlIsZero.get 214 private val vlIsVlmax = intExuBlock.io.vlIsVlmax.get 215 216 ctrlBlock.io.intIQValidNumVec := intScheduler.io.intIQValidNumVec 217 ctrlBlock.io.fpIQValidNumVec := fpScheduler.io.fpIQValidNumVec 218 ctrlBlock.io.fromTop.hartId := io.fromTop.hartId 219 ctrlBlock.io.frontend <> io.frontend 220 ctrlBlock.io.fromCSR.toDecode := intExuBlock.io.csrToDecode.get 221 ctrlBlock.io.fromWB.wbData <> wbDataPath.io.toCtrlBlock.writeback 222 ctrlBlock.io.fromMem.stIn <> io.mem.stIn 223 ctrlBlock.io.fromMem.violation <> io.mem.memoryViolation 224 ctrlBlock.io.lqCanAccept := io.mem.lqCanAccept 225 ctrlBlock.io.sqCanAccept := io.mem.sqCanAccept 226 ctrlBlock.io.csrCtrl <> intExuBlock.io.csrio.get.customCtrl 227 ctrlBlock.io.robio.csr.intrBitSet := intExuBlock.io.csrio.get.interrupt 228 ctrlBlock.io.robio.csr.trapTarget := intExuBlock.io.csrio.get.trapTarget 229 ctrlBlock.io.robio.csr.isXRet := intExuBlock.io.csrio.get.isXRet 230 ctrlBlock.io.robio.csr.wfiEvent := intExuBlock.io.csrio.get.wfi_event 231 ctrlBlock.io.robio.lsq <> io.mem.robLsqIO 232 ctrlBlock.io.robio.lsTopdownInfo <> io.mem.lsTopdownInfo 233 ctrlBlock.io.robio.debug_ls <> io.mem.debugLS 234 ctrlBlock.io.debugEnqLsq.canAccept := io.mem.lsqEnqIO.canAccept 235 ctrlBlock.io.debugEnqLsq.resp := io.mem.lsqEnqIO.resp 236 ctrlBlock.io.debugEnqLsq.req := memScheduler.io.memIO.get.lsqEnqIO.req 237 ctrlBlock.io.debugEnqLsq.needAlloc := memScheduler.io.memIO.get.lsqEnqIO.needAlloc 238 239 intScheduler.io.fromTop.hartId := io.fromTop.hartId 240 intScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 241 intScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 242 intScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.intUops 243 intScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 244 intScheduler.io.fpWriteBack := 0.U.asTypeOf(intScheduler.io.fpWriteBack) 245 intScheduler.io.vfWriteBack := 0.U.asTypeOf(intScheduler.io.vfWriteBack) 246 intScheduler.io.v0WriteBack := 0.U.asTypeOf(intScheduler.io.v0WriteBack) 247 intScheduler.io.vlWriteBack := 0.U.asTypeOf(intScheduler.io.vlWriteBack) 248 intScheduler.io.fromDataPath.resp := dataPath.io.toIntIQ 249 intScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 250 intScheduler.io.fromDataPath.og0Cancel := og0Cancel 251 intScheduler.io.fromDataPath.og1Cancel := og1Cancel 252 intScheduler.io.ldCancel := io.mem.ldCancel 253 intScheduler.io.vlWriteBackInfo.vlIsZero := false.B 254 intScheduler.io.vlWriteBackInfo.vlIsVlmax := false.B 255 256 fpScheduler.io.fromTop.hartId := io.fromTop.hartId 257 fpScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 258 fpScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 259 fpScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.fpUops 260 fpScheduler.io.intWriteBack := 0.U.asTypeOf(fpScheduler.io.intWriteBack) 261 fpScheduler.io.fpWriteBack := wbDataPath.io.toFpPreg 262 fpScheduler.io.vfWriteBack := 0.U.asTypeOf(fpScheduler.io.vfWriteBack) 263 fpScheduler.io.v0WriteBack := 0.U.asTypeOf(fpScheduler.io.v0WriteBack) 264 fpScheduler.io.vlWriteBack := 0.U.asTypeOf(fpScheduler.io.vlWriteBack) 265 fpScheduler.io.fromDataPath.resp := dataPath.io.toFpIQ 266 fpScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 267 fpScheduler.io.fromDataPath.og0Cancel := og0Cancel 268 fpScheduler.io.fromDataPath.og1Cancel := og1Cancel 269 fpScheduler.io.ldCancel := io.mem.ldCancel 270 fpScheduler.io.vlWriteBackInfo.vlIsZero := false.B 271 fpScheduler.io.vlWriteBackInfo.vlIsVlmax := false.B 272 273 memScheduler.io.fromTop.hartId := io.fromTop.hartId 274 memScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 275 memScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 276 memScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.memUops 277 memScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 278 memScheduler.io.fpWriteBack := wbDataPath.io.toFpPreg 279 memScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 280 memScheduler.io.v0WriteBack := wbDataPath.io.toV0Preg 281 memScheduler.io.vlWriteBack := wbDataPath.io.toVlPreg 282 memScheduler.io.fromMem.get.scommit := io.mem.sqDeq 283 memScheduler.io.fromMem.get.lcommit := io.mem.lqDeq 284 memScheduler.io.fromMem.get.wakeup := io.mem.wakeup 285 memScheduler.io.fromMem.get.sqDeqPtr := io.mem.sqDeqPtr 286 memScheduler.io.fromMem.get.lqDeqPtr := io.mem.lqDeqPtr 287 memScheduler.io.fromMem.get.sqCancelCnt := io.mem.sqCancelCnt 288 memScheduler.io.fromMem.get.lqCancelCnt := io.mem.lqCancelCnt 289 memScheduler.io.fromMem.get.stIssuePtr := io.mem.stIssuePtr 290 require(memScheduler.io.fromMem.get.memWaitUpdateReq.robIdx.length == io.mem.stIn.length) 291 memScheduler.io.fromMem.get.memWaitUpdateReq.robIdx.zip(io.mem.stIn).foreach { case (sink, source) => 292 sink.valid := source.valid 293 sink.bits := source.bits.robIdx 294 } 295 memScheduler.io.fromMem.get.memWaitUpdateReq.sqIdx := DontCare // TODO 296 memScheduler.io.fromDataPath.resp := dataPath.io.toMemIQ 297 memScheduler.io.fromMem.get.ldaFeedback := io.mem.ldaIqFeedback 298 memScheduler.io.fromMem.get.staFeedback := io.mem.staIqFeedback 299 memScheduler.io.fromMem.get.hyuFeedback := io.mem.hyuIqFeedback 300 memScheduler.io.fromMem.get.vstuFeedback := io.mem.vstuIqFeedback 301 memScheduler.io.fromMem.get.vlduFeedback := io.mem.vlduIqFeedback 302 memScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 303 memScheduler.io.fromDataPath.og0Cancel := og0Cancel 304 memScheduler.io.fromDataPath.og1Cancel := og1Cancel 305 memScheduler.io.ldCancel := io.mem.ldCancel 306 memScheduler.io.vlWriteBackInfo.vlIsZero := vlIsZero 307 memScheduler.io.vlWriteBackInfo.vlIsVlmax := vlIsVlmax 308 309 vfScheduler.io.fromTop.hartId := io.fromTop.hartId 310 vfScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 311 vfScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 312 vfScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.vfUops 313 vfScheduler.io.intWriteBack := 0.U.asTypeOf(vfScheduler.io.intWriteBack) 314 vfScheduler.io.fpWriteBack := 0.U.asTypeOf(vfScheduler.io.fpWriteBack) 315 vfScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 316 vfScheduler.io.v0WriteBack := wbDataPath.io.toV0Preg 317 vfScheduler.io.vlWriteBack := wbDataPath.io.toVlPreg 318 vfScheduler.io.fromDataPath.resp := dataPath.io.toVfIQ 319 vfScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 320 vfScheduler.io.fromDataPath.og0Cancel := og0Cancel 321 vfScheduler.io.fromDataPath.og1Cancel := og1Cancel 322 vfScheduler.io.ldCancel := io.mem.ldCancel 323 vfScheduler.io.vlWriteBackInfo.vlIsZero := vlIsZero 324 vfScheduler.io.vlWriteBackInfo.vlIsVlmax := vlIsVlmax 325 vfScheduler.io.fromOg2.get := og2ForVector.io.toVfIQ 326 327 dataPath.io.hartId := io.fromTop.hartId 328 dataPath.io.flush := ctrlBlock.io.toDataPath.flush 329 330 dataPath.io.fromIntIQ <> intScheduler.io.toDataPathAfterDelay 331 dataPath.io.fromFpIQ <> fpScheduler.io.toDataPathAfterDelay 332 dataPath.io.fromVfIQ <> vfScheduler.io.toDataPathAfterDelay 333 dataPath.io.fromMemIQ <> memScheduler.io.toDataPathAfterDelay 334 335 dataPath.io.ldCancel := io.mem.ldCancel 336 337 println(s"[Backend] wbDataPath.io.toIntPreg: ${wbDataPath.io.toIntPreg.size}, dataPath.io.fromIntWb: ${dataPath.io.fromIntWb.size}") 338 println(s"[Backend] wbDataPath.io.toVfPreg: ${wbDataPath.io.toVfPreg.size}, dataPath.io.fromFpWb: ${dataPath.io.fromVfWb.size}") 339 dataPath.io.fromIntWb := wbDataPath.io.toIntPreg 340 dataPath.io.fromFpWb := wbDataPath.io.toFpPreg 341 dataPath.io.fromVfWb := wbDataPath.io.toVfPreg 342 dataPath.io.fromV0Wb := wbDataPath.io.toV0Preg 343 dataPath.io.fromVlWb := wbDataPath.io.toVlPreg 344 dataPath.io.debugIntRat .foreach(_ := ctrlBlock.io.debug_int_rat.get) 345 dataPath.io.debugFpRat .foreach(_ := ctrlBlock.io.debug_fp_rat.get) 346 dataPath.io.debugVecRat .foreach(_ := ctrlBlock.io.debug_vec_rat.get) 347 dataPath.io.debugV0Rat .foreach(_ := ctrlBlock.io.debug_v0_rat.get) 348 dataPath.io.debugVlRat .foreach(_ := ctrlBlock.io.debug_vl_rat.get) 349 350 og2ForVector.io.flush := ctrlBlock.io.toDataPath.flush 351 og2ForVector.io.ldCancel := io.mem.ldCancel 352 og2ForVector.io.fromOg1NoReg <> dataPath.io.toVecExu 353 og2ForVector.io.fromOg1ImmInfo := dataPath.io.og1ImmInfo.zip(params.allExuParams).filter(_._2.isVfExeUnit).map(_._1) 354 355 bypassNetwork.io.fromDataPath.int <> dataPath.io.toIntExu 356 bypassNetwork.io.fromDataPath.fp <> dataPath.io.toFpExu 357 bypassNetwork.io.fromDataPath.vf <> og2ForVector.io.toVfExu 358 bypassNetwork.io.fromDataPath.mem <> dataPath.io.toMemExu 359 bypassNetwork.io.fromDataPath.immInfo := dataPath.io.og1ImmInfo 360 bypassNetwork.io.fromDataPath.immInfo.zip(params.allExuParams).filter(_._2.isVfExeUnit).map(_._1).zip(og2ForVector.io.toVfImmInfo).map{ 361 case (vfImmInfo, og2ImmInfo) => vfImmInfo := og2ImmInfo 362 } 363 bypassNetwork.io.fromExus.connectExuOutput(_.int)(intExuBlock.io.out) 364 bypassNetwork.io.fromExus.connectExuOutput(_.fp)(fpExuBlock.io.out) 365 bypassNetwork.io.fromExus.connectExuOutput(_.vf)(vfExuBlock.io.out) 366 367 require(bypassNetwork.io.fromExus.mem.flatten.size == io.mem.writeBack.size, 368 s"bypassNetwork.io.fromExus.mem.flatten.size(${bypassNetwork.io.fromExus.mem.flatten.size}: ${bypassNetwork.io.fromExus.mem.map(_.size)}, " + 369 s"io.mem.writeback(${io.mem.writeBack.size})" 370 ) 371 bypassNetwork.io.fromExus.mem.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 372 sink.valid := source.valid 373 sink.bits.pdest := source.bits.uop.pdest 374 sink.bits.data := source.bits.data 375 } 376 377 378 intExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 379 for (i <- 0 until intExuBlock.io.in.length) { 380 for (j <- 0 until intExuBlock.io.in(i).length) { 381 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.int(i)(j).bits.loadDependency, io.mem.ldCancel) 382 NewPipelineConnect( 383 bypassNetwork.io.toExus.int(i)(j), intExuBlock.io.in(i)(j), intExuBlock.io.in(i)(j).fire, 384 Mux( 385 bypassNetwork.io.toExus.int(i)(j).fire, 386 bypassNetwork.io.toExus.int(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 387 intExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 388 ), 389 Option("bypassNetwork2intExuBlock") 390 ) 391 } 392 } 393 394 pcTargetMem.io.fromFrontendFtq := io.frontend.fromFtq 395 pcTargetMem.io.toDataPath <> dataPath.io.fromPcTargetMem 396 397 private val csrin = intExuBlock.io.csrin.get 398 csrin.hartId := io.fromTop.hartId 399 csrin.msiInfo.valid := RegNext(io.fromTop.msiInfo.valid) 400 csrin.msiInfo.bits := RegEnable(io.fromTop.msiInfo.bits, io.fromTop.msiInfo.valid) 401 csrin.clintTime.valid := RegNext(io.fromTop.clintTime.valid) 402 csrin.clintTime.bits := RegEnable(io.fromTop.clintTime.bits, io.fromTop.clintTime.valid) 403 404 private val csrio = intExuBlock.io.csrio.get 405 csrio.hartId := io.fromTop.hartId 406 csrio.fpu.fflags := ctrlBlock.io.robio.csr.fflags 407 csrio.fpu.isIllegal := false.B // Todo: remove it 408 csrio.fpu.dirty_fs := ctrlBlock.io.robio.csr.dirty_fs 409 csrio.vpu <> WireDefault(0.U.asTypeOf(csrio.vpu)) // Todo 410 411 val fromIntExuVsetVType = intExuBlock.io.vtype.getOrElse(0.U.asTypeOf((Valid(new VType)))) 412 val fromVfExuVsetVType = vfExuBlock.io.vtype.getOrElse(0.U.asTypeOf((Valid(new VType)))) 413 val fromVsetVType = Mux(fromIntExuVsetVType.valid, fromIntExuVsetVType.bits, fromVfExuVsetVType.bits) 414 val vsetvlVType = RegEnable(fromVsetVType, 0.U.asTypeOf(new VType), fromIntExuVsetVType.valid || fromVfExuVsetVType.valid) 415 ctrlBlock.io.toDecode.vsetvlVType := vsetvlVType 416 417 val commitVType = ctrlBlock.io.robio.commitVType.vtype 418 val hasVsetvl = ctrlBlock.io.robio.commitVType.hasVsetvl 419 val vtype = VType.toVtypeStruct(Mux(hasVsetvl, vsetvlVType, commitVType.bits)).asUInt 420 421 // csr not store the value of vl, so when using difftest we assign the value of vl to debugVl 422 val debugVl_s0 = WireInit(UInt(VlData().dataWidth.W), 0.U) 423 val debugVl_s1 = WireInit(UInt(VlData().dataWidth.W), 0.U) 424 debugVl_s0 := dataPath.io.debugVl.getOrElse(0.U.asTypeOf(UInt(VlData().dataWidth.W))) 425 debugVl_s1 := RegNext(debugVl_s0) 426 csrio.vpu.set_vxsat := ctrlBlock.io.robio.csr.vxsat 427 csrio.vpu.set_vstart.valid := ctrlBlock.io.robio.csr.vstart.valid 428 csrio.vpu.set_vstart.bits := ctrlBlock.io.robio.csr.vstart.bits 429 ctrlBlock.io.toDecode.vstart := csrio.vpu.vstart 430 //Todo here need change design 431 csrio.vpu.set_vtype.valid := commitVType.valid 432 csrio.vpu.set_vtype.bits := ZeroExt(vtype, XLEN) 433 csrio.vpu.vl := ZeroExt(debugVl_s1, XLEN) 434 csrio.vpu.dirty_vs := ctrlBlock.io.robio.csr.dirty_vs 435 csrio.exception := ctrlBlock.io.robio.exception 436 csrio.memExceptionVAddr := io.mem.exceptionAddr.vaddr 437 csrio.memExceptionGPAddr := io.mem.exceptionAddr.gpaddr 438 csrio.externalInterrupt := RegNext(io.fromTop.externalInterrupt) 439 csrio.distributedUpdate(0) := io.mem.csrDistributedUpdate 440 csrio.distributedUpdate(1) := io.frontendCsrDistributedUpdate 441 csrio.perf <> io.perf 442 csrio.perf.retiredInstr <> ctrlBlock.io.robio.csr.perfinfo.retiredInstr 443 csrio.perf.ctrlInfo <> ctrlBlock.io.perfInfo.ctrlInfo 444 private val fenceio = intExuBlock.io.fenceio.get 445 io.fenceio <> fenceio 446 447 // to fpExuBlock 448 fpExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 449 for (i <- 0 until fpExuBlock.io.in.length) { 450 for (j <- 0 until fpExuBlock.io.in(i).length) { 451 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.fp(i)(j).bits.loadDependency, io.mem.ldCancel) 452 NewPipelineConnect( 453 bypassNetwork.io.toExus.fp(i)(j), fpExuBlock.io.in(i)(j), fpExuBlock.io.in(i)(j).fire, 454 Mux( 455 bypassNetwork.io.toExus.fp(i)(j).fire, 456 bypassNetwork.io.toExus.fp(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 457 fpExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 458 ), 459 Option("bypassNetwork2fpExuBlock") 460 ) 461 } 462 } 463 464 vfExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 465 for (i <- 0 until vfExuBlock.io.in.size) { 466 for (j <- 0 until vfExuBlock.io.in(i).size) { 467 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.vf(i)(j).bits.loadDependency, io.mem.ldCancel) 468 NewPipelineConnect( 469 bypassNetwork.io.toExus.vf(i)(j), vfExuBlock.io.in(i)(j), vfExuBlock.io.in(i)(j).fire, 470 Mux( 471 bypassNetwork.io.toExus.vf(i)(j).fire, 472 bypassNetwork.io.toExus.vf(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 473 vfExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 474 ), 475 Option("bypassNetwork2vfExuBlock") 476 ) 477 478 } 479 } 480 481 intExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 482 fpExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 483 fpExuBlock.io.vxrm.foreach(_ := csrio.vpu.vxrm) 484 vfExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 485 vfExuBlock.io.vxrm.foreach(_ := csrio.vpu.vxrm) 486 487 wbDataPath.io.flush := ctrlBlock.io.redirect 488 wbDataPath.io.fromTop.hartId := io.fromTop.hartId 489 wbDataPath.io.fromIntExu <> intExuBlock.io.out 490 wbDataPath.io.fromFpExu <> fpExuBlock.io.out 491 wbDataPath.io.fromVfExu <> vfExuBlock.io.out 492 wbDataPath.io.fromMemExu.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 493 sink.valid := source.valid 494 source.ready := sink.ready 495 sink.bits.data := VecInit(Seq.fill(sink.bits.params.wbPathNum)(source.bits.data)) 496 sink.bits.pdest := source.bits.uop.pdest 497 sink.bits.robIdx := source.bits.uop.robIdx 498 sink.bits.intWen.foreach(_ := source.bits.uop.rfWen) 499 sink.bits.fpWen.foreach(_ := source.bits.uop.fpWen) 500 sink.bits.vecWen.foreach(_ := source.bits.uop.vecWen) 501 sink.bits.v0Wen.foreach(_ := source.bits.uop.v0Wen) 502 sink.bits.vlWen.foreach(_ := source.bits.uop.vlWen) 503 sink.bits.exceptionVec.foreach(_ := source.bits.uop.exceptionVec) 504 sink.bits.flushPipe.foreach(_ := source.bits.uop.flushPipe) 505 sink.bits.replay.foreach(_ := source.bits.uop.replayInst) 506 sink.bits.debug := source.bits.debug 507 sink.bits.debugInfo := source.bits.uop.debugInfo 508 sink.bits.lqIdx.foreach(_ := source.bits.uop.lqIdx) 509 sink.bits.sqIdx.foreach(_ := source.bits.uop.sqIdx) 510 sink.bits.predecodeInfo.foreach(_ := source.bits.uop.preDecodeInfo) 511 sink.bits.vls.foreach(x => { 512 x.vdIdx := source.bits.vdIdx.get 513 x.vdIdxInField := source.bits.vdIdxInField.get 514 x.vpu := source.bits.uop.vpu 515 x.oldVdPsrc := source.bits.uop.psrc(2) 516 x.isIndexed := VlduType.isIndexed(source.bits.uop.fuOpType) 517 x.isMasked := VlduType.isMasked(source.bits.uop.fuOpType) 518 }) 519 sink.bits.trigger.foreach(_ := source.bits.uop.trigger) 520 } 521 522 // to mem 523 private val memIssueParams = params.memSchdParams.get.issueBlockParams 524 private val memExuBlocksHasLDU = memIssueParams.map(_.exuBlockParams.map(x => x.hasLoadFu || x.hasHyldaFu)) 525 private val memExuBlocksHasVecLoad = memIssueParams.map(_.exuBlockParams.map(x => x.hasVLoadFu)) 526 println(s"[Backend] memExuBlocksHasLDU: $memExuBlocksHasLDU") 527 println(s"[Backend] memExuBlocksHasVecLoad: $memExuBlocksHasVecLoad") 528 529 private val toMem = Wire(bypassNetwork.io.toExus.mem.cloneType) 530 for (i <- toMem.indices) { 531 for (j <- toMem(i).indices) { 532 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.mem(i)(j).bits.loadDependency, io.mem.ldCancel) 533 val issueTimeout = 534 if (memExuBlocksHasLDU(i)(j)) 535 Counter(0 until 16, toMem(i)(j).valid && !toMem(i)(j).fire, bypassNetwork.io.toExus.mem(i)(j).fire)._2 536 else 537 false.B 538 539 if (memScheduler.io.loadFinalIssueResp(i).nonEmpty && memExuBlocksHasLDU(i)(j)) { 540 memScheduler.io.loadFinalIssueResp(i)(j).valid := issueTimeout 541 memScheduler.io.loadFinalIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType 542 memScheduler.io.loadFinalIssueResp(i)(j).bits.resp := RespType.block 543 memScheduler.io.loadFinalIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx 544 memScheduler.io.loadFinalIssueResp(i)(j).bits.uopIdx.foreach(_ := toMem(i)(j).bits.vpu.get.vuopIdx) 545 memScheduler.io.loadFinalIssueResp(i)(j).bits.sqIdx.foreach(_ := toMem(i)(j).bits.sqIdx.get) 546 memScheduler.io.loadFinalIssueResp(i)(j).bits.lqIdx.foreach(_ := toMem(i)(j).bits.lqIdx.get) 547 } 548 549 NewPipelineConnect( 550 bypassNetwork.io.toExus.mem(i)(j), toMem(i)(j), toMem(i)(j).fire, 551 Mux( 552 bypassNetwork.io.toExus.mem(i)(j).fire, 553 bypassNetwork.io.toExus.mem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 554 toMem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || issueTimeout 555 ), 556 Option("bypassNetwork2toMemExus") 557 ) 558 559 if (memScheduler.io.memAddrIssueResp(i).nonEmpty && memExuBlocksHasLDU(i)(j)) { 560 memScheduler.io.memAddrIssueResp(i)(j).valid := toMem(i)(j).fire && FuType.isLoad(toMem(i)(j).bits.fuType) 561 memScheduler.io.memAddrIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType 562 memScheduler.io.memAddrIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx 563 memScheduler.io.memAddrIssueResp(i)(j).bits.sqIdx.foreach(_ := toMem(i)(j).bits.sqIdx.get) 564 memScheduler.io.memAddrIssueResp(i)(j).bits.lqIdx.foreach(_ := toMem(i)(j).bits.lqIdx.get) 565 memScheduler.io.memAddrIssueResp(i)(j).bits.resp := RespType.success // for load inst, firing at toMem means issuing successfully 566 } 567 568 if (memScheduler.io.vecLoadIssueResp(i).nonEmpty && memExuBlocksHasVecLoad(i)(j)) { 569 memScheduler.io.vecLoadIssueResp(i)(j) match { 570 case resp => 571 resp.valid := toMem(i)(j).fire && VlduType.isVecLd(toMem(i)(j).bits.fuOpType) 572 resp.bits.fuType := toMem(i)(j).bits.fuType 573 resp.bits.robIdx := toMem(i)(j).bits.robIdx 574 resp.bits.uopIdx.get := toMem(i)(j).bits.vpu.get.vuopIdx 575 resp.bits.sqIdx.get := toMem(i)(j).bits.sqIdx.get 576 resp.bits.lqIdx.get := toMem(i)(j).bits.lqIdx.get 577 resp.bits.resp := RespType.success 578 } 579 if (backendParams.debugEn){ 580 dontTouch(memScheduler.io.vecLoadIssueResp(i)(j)) 581 } 582 } 583 } 584 } 585 586 io.mem.redirect := ctrlBlock.io.redirect 587 io.mem.issueUops.zip(toMem.flatten).foreach { case (sink, source) => 588 val enableMdp = Constantin.createRecord("EnableMdp", true) 589 sink.valid := source.valid 590 source.ready := sink.ready 591 sink.bits.iqIdx := source.bits.iqIdx 592 sink.bits.isFirstIssue := source.bits.isFirstIssue 593 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 594 sink.bits.src := 0.U.asTypeOf(sink.bits.src) 595 sink.bits.src.zip(source.bits.src).foreach { case (l, r) => l := r} 596 sink.bits.uop.fuType := source.bits.fuType 597 sink.bits.uop.fuOpType := source.bits.fuOpType 598 sink.bits.uop.imm := source.bits.imm 599 sink.bits.uop.robIdx := source.bits.robIdx 600 sink.bits.uop.pdest := source.bits.pdest 601 sink.bits.uop.rfWen := source.bits.rfWen.getOrElse(false.B) 602 sink.bits.uop.fpWen := source.bits.fpWen.getOrElse(false.B) 603 sink.bits.uop.vecWen := source.bits.vecWen.getOrElse(false.B) 604 sink.bits.uop.v0Wen := source.bits.v0Wen.getOrElse(false.B) 605 sink.bits.uop.vlWen := source.bits.vlWen.getOrElse(false.B) 606 sink.bits.uop.flushPipe := source.bits.flushPipe.getOrElse(false.B) 607 sink.bits.uop.pc := source.bits.pc.getOrElse(0.U) 608 sink.bits.uop.loadWaitBit := Mux(enableMdp, source.bits.loadWaitBit.getOrElse(false.B), false.B) 609 sink.bits.uop.waitForRobIdx := Mux(enableMdp, source.bits.waitForRobIdx.getOrElse(0.U.asTypeOf(new RobPtr)), 0.U.asTypeOf(new RobPtr)) 610 sink.bits.uop.storeSetHit := Mux(enableMdp, source.bits.storeSetHit.getOrElse(false.B), false.B) 611 sink.bits.uop.loadWaitStrict := Mux(enableMdp, source.bits.loadWaitStrict.getOrElse(false.B), false.B) 612 sink.bits.uop.ssid := Mux(enableMdp, source.bits.ssid.getOrElse(0.U(SSIDWidth.W)), 0.U(SSIDWidth.W)) 613 sink.bits.uop.lqIdx := source.bits.lqIdx.getOrElse(0.U.asTypeOf(new LqPtr)) 614 sink.bits.uop.sqIdx := source.bits.sqIdx.getOrElse(0.U.asTypeOf(new SqPtr)) 615 sink.bits.uop.ftqPtr := source.bits.ftqIdx.getOrElse(0.U.asTypeOf(new FtqPtr)) 616 sink.bits.uop.ftqOffset := source.bits.ftqOffset.getOrElse(0.U) 617 sink.bits.uop.debugInfo := source.bits.perfDebugInfo 618 sink.bits.uop.vpu := source.bits.vpu.getOrElse(0.U.asTypeOf(new VPUCtrlSignals)) 619 sink.bits.uop.preDecodeInfo := source.bits.preDecode.getOrElse(0.U.asTypeOf(new PreDecodeInfo)) 620 sink.bits.uop.numLsElem := source.bits.numLsElem.getOrElse(0.U) // Todo: remove this bundle, keep only the one below 621 sink.bits.flowNum.foreach(_ := source.bits.numLsElem.get) 622 } 623 io.mem.loadFastMatch := memScheduler.io.toMem.get.loadFastMatch.map(_.fastMatch) 624 io.mem.loadFastImm := memScheduler.io.toMem.get.loadFastMatch.map(_.fastImm) 625 io.mem.tlbCsr := csrio.tlb 626 io.mem.csrCtrl := csrio.customCtrl 627 io.mem.sfence := fenceio.sfence 628 io.mem.isStoreException := CommitType.lsInstIsStore(ctrlBlock.io.robio.exception.bits.commitType) 629 io.mem.isVlsException := ctrlBlock.io.robio.exception.bits.vls 630 require(io.mem.loadPcRead.size == params.LduCnt) 631 io.mem.loadPcRead.zipWithIndex.foreach { case (loadPcRead, i) => 632 loadPcRead := ctrlBlock.io.memLdPcRead(i).data 633 ctrlBlock.io.memLdPcRead(i).vld := io.mem.issueLda(i).valid 634 ctrlBlock.io.memLdPcRead(i).ptr := io.mem.issueLda(i).bits.uop.ftqPtr 635 ctrlBlock.io.memLdPcRead(i).offset := io.mem.issueLda(i).bits.uop.ftqOffset 636 } 637 638 io.mem.storePcRead.zipWithIndex.foreach { case (storePcRead, i) => 639 storePcRead := ctrlBlock.io.memStPcRead(i).data 640 ctrlBlock.io.memStPcRead(i).vld := io.mem.issueSta(i).valid 641 ctrlBlock.io.memStPcRead(i).ptr := io.mem.issueSta(i).bits.uop.ftqPtr 642 ctrlBlock.io.memStPcRead(i).offset := io.mem.issueSta(i).bits.uop.ftqOffset 643 } 644 645 io.mem.hyuPcRead.zipWithIndex.foreach( { case (hyuPcRead, i) => 646 hyuPcRead := ctrlBlock.io.memHyPcRead(i).data 647 ctrlBlock.io.memHyPcRead(i).vld := io.mem.issueHylda(i).valid 648 ctrlBlock.io.memHyPcRead(i).ptr := io.mem.issueHylda(i).bits.uop.ftqPtr 649 ctrlBlock.io.memHyPcRead(i).offset := io.mem.issueHylda(i).bits.uop.ftqOffset 650 }) 651 652 ctrlBlock.io.robio.robHeadLsIssue := io.mem.issueUops.map(deq => deq.fire && deq.bits.uop.robIdx === ctrlBlock.io.robio.robDeqPtr).reduce(_ || _) 653 654 // mem io 655 io.mem.lsqEnqIO <> memScheduler.io.memIO.get.lsqEnqIO 656 io.mem.robLsqIO <> ctrlBlock.io.robio.lsq 657 658 io.frontendSfence := fenceio.sfence 659 io.frontendTlbCsr := csrio.tlb 660 io.frontendCsrCtrl := csrio.customCtrl 661 662 io.tlb <> csrio.tlb 663 664 io.csrCustomCtrl := csrio.customCtrl 665 666 io.toTop.cpuHalted := false.B // TODO: implement cpu halt 667 668 io.debugTopDown.fromRob := ctrlBlock.io.debugTopDown.fromRob 669 ctrlBlock.io.debugTopDown.fromCore := io.debugTopDown.fromCore 670 671 io.debugRolling := ctrlBlock.io.debugRolling 672 673 if(backendParams.debugEn) { 674 dontTouch(memScheduler.io) 675 dontTouch(dataPath.io.toMemExu) 676 dontTouch(wbDataPath.io.fromMemExu) 677 } 678 679 val pfevent = Module(new PFEvent) 680 pfevent.io.distribute_csr := RegNext(csrio.customCtrl.distribute_csr) 681 val csrevents = pfevent.io.hpmevent.slice(8,16) 682 683 val ctrlBlockPerf = ctrlBlock.getPerfEvents 684 val intSchedulerPerf = intScheduler.asInstanceOf[SchedulerArithImp].getPerfEvents 685 val fpSchedulerPerf = fpScheduler.asInstanceOf[SchedulerArithImp].getPerfEvents 686 val vecSchedulerPerf = vfScheduler.asInstanceOf[SchedulerArithImp].getPerfEvents 687 val memSchedulerPerf = memScheduler.asInstanceOf[SchedulerMemImp].getPerfEvents 688 689 val perfBackend = Seq() 690 // let index = 0 be no event 691 val allPerfEvents = Seq(("noEvent", 0.U)) ++ ctrlBlockPerf ++ intSchedulerPerf ++ fpSchedulerPerf ++ vecSchedulerPerf ++ memSchedulerPerf ++ perfBackend 692 693 694 if (printEventCoding) { 695 for (((name, inc), i) <- allPerfEvents.zipWithIndex) { 696 println("backend perfEvents Set", name, inc, i) 697 } 698 } 699 700 val allPerfInc = allPerfEvents.map(_._2.asTypeOf(new PerfEvent)) 701 val perfEvents = HPerfMonitor(csrevents, allPerfInc).getPerfEvents 702 csrio.perf.perfEventsBackend := VecInit(perfEvents.map(_._2.asTypeOf(new PerfEvent))) 703 generatePerfEvent() 704} 705 706class BackendMemIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 707 // Since fast load replay always use load unit 0, Backend flips two load port to avoid conflicts 708 val flippedLda = true 709 // params alias 710 private val LoadQueueSize = VirtualLoadQueueSize 711 // In/Out // Todo: split it into one-direction bundle 712 val lsqEnqIO = Flipped(new LsqEnqIO) 713 val robLsqIO = new RobLsqIO 714 val ldaIqFeedback = Vec(params.LduCnt, Flipped(new MemRSFeedbackIO)) 715 val staIqFeedback = Vec(params.StaCnt, Flipped(new MemRSFeedbackIO)) 716 val hyuIqFeedback = Vec(params.HyuCnt, Flipped(new MemRSFeedbackIO)) 717 val vstuIqFeedback = Flipped(Vec(params.VstuCnt, new MemRSFeedbackIO(isVector = true))) 718 val vlduIqFeedback = Flipped(Vec(params.VlduCnt, new MemRSFeedbackIO(isVector = true))) 719 val ldCancel = Vec(params.LdExuCnt, Flipped(new LoadCancelIO)) 720 val wakeup = Vec(params.LdExuCnt, Flipped(Valid(new DynInst))) 721 val loadPcRead = Vec(params.LduCnt, Output(UInt(VAddrBits.W))) 722 val storePcRead = Vec(params.StaCnt, Output(UInt(VAddrBits.W))) 723 val hyuPcRead = Vec(params.HyuCnt, Output(UInt(VAddrBits.W))) 724 // Input 725 val writebackLda = Vec(params.LduCnt, Flipped(DecoupledIO(new MemExuOutput))) 726 val writebackSta = Vec(params.StaCnt, Flipped(DecoupledIO(new MemExuOutput))) 727 val writebackStd = Vec(params.StdCnt, Flipped(DecoupledIO(new MemExuOutput))) 728 val writebackHyuLda = Vec(params.HyuCnt, Flipped(DecoupledIO(new MemExuOutput))) 729 val writebackHyuSta = Vec(params.HyuCnt, Flipped(DecoupledIO(new MemExuOutput))) 730 val writebackVldu = Vec(params.VlduCnt, Flipped(DecoupledIO(new MemExuOutput(true)))) 731 732 val s3_delayed_load_error = Input(Vec(LoadPipelineWidth, Bool())) 733 val stIn = Input(Vec(params.StaExuCnt, ValidIO(new DynInst()))) 734 val memoryViolation = Flipped(ValidIO(new Redirect)) 735 val exceptionAddr = Input(new Bundle { 736 val vaddr = UInt(VAddrBits.W) 737 val gpaddr = UInt(GPAddrBits.W) 738 }) 739 val sqDeq = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) 740 val lqDeq = Input(UInt(log2Up(CommitWidth + 1).W)) 741 val sqDeqPtr = Input(new SqPtr) 742 val lqDeqPtr = Input(new LqPtr) 743 744 val lqCancelCnt = Input(UInt(log2Up(VirtualLoadQueueSize + 1).W)) 745 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 746 747 val lqCanAccept = Input(Bool()) 748 val sqCanAccept = Input(Bool()) 749 750 val otherFastWakeup = Flipped(Vec(params.LduCnt + params.HyuCnt, ValidIO(new DynInst))) 751 val stIssuePtr = Input(new SqPtr()) 752 753 val csrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 754 755 val debugLS = Flipped(Output(new DebugLSIO)) 756 757 val lsTopdownInfo = Vec(params.LduCnt + params.HyuCnt, Flipped(Output(new LsTopdownInfo))) 758 // Output 759 val redirect = ValidIO(new Redirect) // rob flush MemBlock 760 val issueLda = MixedVec(Seq.fill(params.LduCnt)(DecoupledIO(new MemExuInput()))) 761 val issueSta = MixedVec(Seq.fill(params.StaCnt)(DecoupledIO(new MemExuInput()))) 762 val issueStd = MixedVec(Seq.fill(params.StdCnt)(DecoupledIO(new MemExuInput()))) 763 val issueHylda = MixedVec(Seq.fill(params.HyuCnt)(DecoupledIO(new MemExuInput()))) 764 val issueHysta = MixedVec(Seq.fill(params.HyuCnt)(DecoupledIO(new MemExuInput()))) 765 val issueVldu = MixedVec(Seq.fill(params.VlduCnt)(DecoupledIO(new MemExuInput(true)))) 766 767 val loadFastMatch = Vec(params.LduCnt, Output(UInt(params.LduCnt.W))) 768 val loadFastImm = Vec(params.LduCnt, Output(UInt(12.W))) // Imm_I 769 770 val tlbCsr = Output(new TlbCsrBundle) 771 val csrCtrl = Output(new CustomCSRCtrlIO) 772 val sfence = Output(new SfenceBundle) 773 val isStoreException = Output(Bool()) 774 val isVlsException = Output(Bool()) 775 776 // ATTENTION: The issue ports' sequence order should be the same as IQs' deq config 777 private [backend] def issueUops: Seq[DecoupledIO[MemExuInput]] = { 778 issueSta ++ 779 issueHylda ++ issueHysta ++ 780 issueLda ++ 781 issueVldu ++ 782 issueStd 783 }.toSeq 784 785 // ATTENTION: The writeback ports' sequence order should be the same as IQs' deq config 786 private [backend] def writeBack: Seq[DecoupledIO[MemExuOutput]] = { 787 writebackSta ++ 788 writebackHyuLda ++ writebackHyuSta ++ 789 writebackLda ++ 790 writebackVldu ++ 791 writebackStd 792 } 793} 794 795class BackendIO(implicit p: Parameters, params: BackendParams) extends XSBundle with HasSoCParameter { 796 val fromTop = new Bundle { 797 val hartId = Input(UInt(hartIdLen.W)) 798 val externalInterrupt = Input(new ExternalInterruptIO) 799 val msiInfo = Input(ValidIO(new MsiInfoBundle)) 800 val clintTime = Input(ValidIO(UInt(64.W))) 801 } 802 803 val toTop = new Bundle { 804 val cpuHalted = Output(Bool()) 805 } 806 807 val fenceio = new FenceIO 808 // Todo: merge these bundles into BackendFrontendIO 809 val frontend = Flipped(new FrontendToCtrlIO) 810 val frontendSfence = Output(new SfenceBundle) 811 val frontendCsrCtrl = Output(new CustomCSRCtrlIO) 812 val frontendTlbCsr = Output(new TlbCsrBundle) 813 // distributed csr write 814 val frontendCsrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 815 816 val mem = new BackendMemIO 817 818 val perf = Input(new PerfCounterIO) 819 820 val tlb = Output(new TlbCsrBundle) 821 822 val csrCustomCtrl = Output(new CustomCSRCtrlIO) 823 824 val debugTopDown = new Bundle { 825 val fromRob = new RobCoreTopDownIO 826 val fromCore = new CoreDispatchTopDownIO 827 } 828 val debugRolling = new RobDebugRollingIO 829} 830