1package xiangshan.backend 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utils.OptionWrapper 7import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 8import utility.{PipelineConnect, ZeroExt} 9import xiangshan._ 10import xiangshan.backend.Bundles.{DynInst, MemExuInput, MemExuOutput} 11import xiangshan.backend.ctrlblock.CtrlBlock 12import xiangshan.backend.datapath.WbConfig._ 13import xiangshan.backend.datapath.{DataPath, NewPipelineConnect, WbDataPath, WbFuBusyTable} 14import xiangshan.backend.exu.ExuBlock 15import xiangshan.backend.fu.vector.Bundles.{VConfig, VType} 16import xiangshan.backend.fu.{FenceIO, FenceToSbuffer, FuConfig, PerfCounterIO} 17import xiangshan.backend.issue.{Scheduler, IntScheduler, MemScheduler, VfScheduler} 18import xiangshan.backend.rob.RobLsqIO 19import xiangshan.frontend.{FtqPtr, FtqRead} 20import xiangshan.mem.{LqPtr, LsqEnqIO, SqPtr} 21 22class Backend(val params: BackendParams)(implicit p: Parameters) extends LazyModule 23 with HasXSParameter { 24 25 /* Only update the idx in mem-scheduler here 26 * Idx in other schedulers can be updated the same way if needed 27 * 28 * Also note that we filter out the 'stData issue-queues' when counting 29 */ 30 for ((ibp, idx) <- params.memSchdParams.get.issueBlockParams.filter(iq => iq.StdCnt == 0).zipWithIndex) { 31 ibp.updateIdx(idx) 32 } 33 34 println("[Backend] ExuConfigs:") 35 for (exuCfg <- params.allExuParams) { 36 val fuConfigs = exuCfg.fuConfigs 37 val wbPortConfigs = exuCfg.wbPortConfigs 38 val immType = exuCfg.immType 39 40 println("[Backend] " + 41 s"${exuCfg.name}: " + 42 s"${ fuConfigs.map(_.name).mkString("fu(s): {", ",", "}") }, " + 43 s"${ wbPortConfigs.mkString("wb: {", ",", "}") }, " + 44 s"${ immType.map(SelImm.mkString(_)).mkString("imm: {", "," , "}") }, " + 45 s"latMax(${exuCfg.latencyValMax}), ${exuCfg.fuLatancySet.mkString("lat: {",",","}")}, ") 46 require(wbPortConfigs.collectFirst { case x: IntWB => x }.nonEmpty == 47 fuConfigs.map(_.writeIntRf).reduce(_ || _), 48 "int wb port has no priority" ) 49 require(wbPortConfigs.collectFirst { case x: VfWB => x }.nonEmpty == 50 fuConfigs.map(x => x.writeFpRf || x.writeVecRf).reduce(_ || _), 51 "vec wb port has no priority" ) 52 } 53 54 for (cfg <- FuConfig.allConfigs) { 55 println(s"[Backend] $cfg") 56 } 57 58 val ctrlBlock = LazyModule(new CtrlBlock(params)) 59 val intScheduler = params.intSchdParams.map(x => LazyModule(new Scheduler(x))) 60 val vfScheduler = params.vfSchdParams.map(x => LazyModule(new Scheduler(x))) 61 val memScheduler = params.memSchdParams.map(x => LazyModule(new Scheduler(x))) 62 val dataPath = LazyModule(new DataPath(params)) 63 val intExuBlock = params.intSchdParams.map(x => LazyModule(new ExuBlock(x))) 64 val vfExuBlock = params.vfSchdParams.map(x => LazyModule(new ExuBlock(x))) 65 val wbFuBusyTable = LazyModule(new WbFuBusyTable(params)) 66 67 lazy val module = new BackendImp(this) 68} 69 70class BackendImp(override val wrapper: Backend)(implicit p: Parameters) extends LazyModuleImp(wrapper) 71 with HasXSParameter{ 72 implicit private val params = wrapper.params 73 val io = IO(new BackendIO()(p, wrapper.params)) 74 75 private val ctrlBlock = wrapper.ctrlBlock.module 76 private val intScheduler = wrapper.intScheduler.get.module 77 private val vfScheduler = wrapper.vfScheduler.get.module 78 private val memScheduler = wrapper.memScheduler.get.module 79 private val dataPath = wrapper.dataPath.module 80 private val intExuBlock = wrapper.intExuBlock.get.module 81 private val vfExuBlock = wrapper.vfExuBlock.get.module 82 private val wbDataPath = Module(new WbDataPath(params)) 83 private val wbFuBusyTable = wrapper.wbFuBusyTable.module 84 85 wbFuBusyTable.io.in.intSchdBusyTable := intScheduler.io.wbFuBusyTable 86 wbFuBusyTable.io.in.vfSchdBusyTable := vfScheduler.io.wbFuBusyTable 87 wbFuBusyTable.io.in.memSchdBusyTable := memScheduler.io.wbFuBusyTable 88 intScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.intRespRead 89 vfScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.vfRespRead 90 memScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.memRespRead 91 dataPath.io.wbConfictRead := wbFuBusyTable.io.out.wbConflictRead 92 93 wbDataPath.io.fromIntExu.flatten.filter(x => x.bits.params.writeIntRf) 94 95 private val vconfig = dataPath.io.vconfigReadPort.data 96 97 ctrlBlock.io.fromTop.hartId := io.fromTop.hartId 98 ctrlBlock.io.frontend <> io.frontend 99 ctrlBlock.io.fromWB.wbData <> wbDataPath.io.toCtrlBlock.writeback 100 ctrlBlock.io.fromMem.stIn <> io.mem.stIn 101 ctrlBlock.io.fromMem.violation <> io.mem.memoryViolation 102 ctrlBlock.io.csrCtrl <> intExuBlock.io.csrio.get.customCtrl 103 ctrlBlock.io.robio.csr.intrBitSet := intExuBlock.io.csrio.get.interrupt 104 ctrlBlock.io.robio.csr.trapTarget := intExuBlock.io.csrio.get.trapTarget 105 ctrlBlock.io.robio.csr.isXRet := intExuBlock.io.csrio.get.isXRet 106 ctrlBlock.io.robio.csr.wfiEvent := intExuBlock.io.csrio.get.wfi_event 107 ctrlBlock.io.robio.lsq <> io.mem.robLsqIO 108 ctrlBlock.io.fromDataPath.vtype := vconfig(7, 0).asTypeOf(new VType) 109 110 intScheduler.io.fromTop.hartId := io.fromTop.hartId 111 intScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 112 intScheduler.io.fromCtrlBlock.pcVec := ctrlBlock.io.toIssueBlock.pcVec 113 intScheduler.io.fromCtrlBlock.targetVec := ctrlBlock.io.toIssueBlock.targetVec 114 intScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 115 intScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.intUops 116 intScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 117 intScheduler.io.vfWriteBack := 0.U.asTypeOf(intScheduler.io.vfWriteBack) 118 intScheduler.io.fromDataPath := dataPath.io.toIntIQ 119 120 memScheduler.io.fromTop.hartId := io.fromTop.hartId 121 memScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 122 memScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 123 memScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.memUops 124 memScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 125 memScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 126 memScheduler.io.fromMem.get.scommit := io.mem.sqDeq 127 memScheduler.io.fromMem.get.lcommit := io.mem.lqDeq 128 memScheduler.io.fromMem.get.sqCancelCnt := io.mem.sqCancelCnt 129 memScheduler.io.fromMem.get.lqCancelCnt := io.mem.lqCancelCnt 130 memScheduler.io.fromMem.get.stIssuePtr := io.mem.stIssuePtr 131 memScheduler.io.fromMem.get.memWaitUpdateReq.staIssue.zip(io.mem.stIn).foreach { case (sink, source) => 132 sink.valid := source.valid 133 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 134 sink.bits.uop.robIdx := source.bits.robIdx 135 } 136 memScheduler.io.fromDataPath := dataPath.io.toMemIQ 137 memScheduler.io.fromMem.get.ldaFeedback := io.mem.ldaIqFeedback 138 memScheduler.io.fromMem.get.staFeedback := io.mem.staIqFeedback 139 140 vfScheduler.io.fromTop.hartId := io.fromTop.hartId 141 vfScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 142 vfScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 143 vfScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.vfUops 144 vfScheduler.io.intWriteBack := 0.U.asTypeOf(vfScheduler.io.intWriteBack) 145 vfScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 146 vfScheduler.io.fromDataPath := dataPath.io.toVfIQ 147 148 dataPath.io.flush := ctrlBlock.io.toDataPath.flush 149 dataPath.io.vconfigReadPort.addr := ctrlBlock.io.toDataPath.vtypeAddr 150 151 for (i <- 0 until dataPath.io.fromIntIQ.length) { 152 for (j <- 0 until dataPath.io.fromIntIQ(i).length) { 153 NewPipelineConnect(intScheduler.io.toDataPath(i)(j), dataPath.io.fromIntIQ(i)(j), dataPath.io.fromIntIQ(i)(j).valid, 154 intScheduler.io.toDataPath(i)(j).bits.common.robIdx.needFlush(ctrlBlock.io.toDataPath.flush), Option("intScheduler2DataPathPipe")) 155 } 156 } 157 158 for (i <- 0 until dataPath.io.fromVfIQ.length) { 159 for (j <- 0 until dataPath.io.fromVfIQ(i).length) { 160 NewPipelineConnect(vfScheduler.io.toDataPath(i)(j), dataPath.io.fromVfIQ(i)(j), dataPath.io.fromVfIQ(i)(j).valid, 161 vfScheduler.io.toDataPath(i)(j).bits.common.robIdx.needFlush(ctrlBlock.io.toDataPath.flush), Option("vfScheduler2DataPathPipe")) 162 } 163 } 164 165 for (i <- 0 until dataPath.io.fromMemIQ.length) { 166 for (j <- 0 until dataPath.io.fromMemIQ(i).length) { 167 NewPipelineConnect(memScheduler.io.toDataPath(i)(j), dataPath.io.fromMemIQ(i)(j), dataPath.io.fromMemIQ(i)(j).valid, 168 memScheduler.io.toDataPath(i)(j).bits.common.robIdx.needFlush(ctrlBlock.io.toDataPath.flush), Option("memScheduler2DataPathPipe")) 169 } 170 } 171 172 println(s"[Backend] wbDataPath.io.toIntPreg: ${wbDataPath.io.toIntPreg.size}, dataPath.io.fromIntWb: ${dataPath.io.fromIntWb.size}") 173 println(s"[Backend] wbDataPath.io.toVfPreg: ${wbDataPath.io.toVfPreg.size}, dataPath.io.fromFpWb: ${dataPath.io.fromVfWb.size}") 174 dataPath.io.fromIntWb := wbDataPath.io.toIntPreg 175 dataPath.io.fromVfWb := wbDataPath.io.toVfPreg 176 dataPath.io.debugIntRat := ctrlBlock.io.debug_int_rat 177 dataPath.io.debugFpRat := ctrlBlock.io.debug_fp_rat 178 dataPath.io.debugVecRat := ctrlBlock.io.debug_vec_rat 179 dataPath.io.debugVconfigRat := ctrlBlock.io.debug_vconfig_rat 180 181 intExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 182 for (i <- 0 until intExuBlock.io.in.length) { 183 for (j <- 0 until intExuBlock.io.in(i).length) { 184 NewPipelineConnect(dataPath.io.toIntExu(i)(j), intExuBlock.io.in(i)(j), intExuBlock.io.in(i)(j).fire, 185 Mux(dataPath.io.toIntExu(i)(j).fire, 186 dataPath.io.toIntExu(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush), 187 intExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush))) 188 } 189 } 190 191 private val csrio = intExuBlock.io.csrio.get 192 csrio.hartId := io.fromTop.hartId 193 csrio.perf.retiredInstr <> ctrlBlock.io.robio.csr.perfinfo.retiredInstr 194 csrio.perf.ctrlInfo <> ctrlBlock.io.perfInfo.ctrlInfo 195 csrio.perf.perfEventsCtrl <> ctrlBlock.getPerf 196 csrio.fpu.fflags := ctrlBlock.io.robio.csr.fflags 197 csrio.fpu.isIllegal := false.B // Todo: remove it 198 csrio.fpu.dirty_fs := ctrlBlock.io.robio.csr.dirty_fs 199 csrio.vpu <> 0.U.asTypeOf(csrio.vpu) // Todo 200 201 val debugVconfig = dataPath.io.debugVconfig.asTypeOf(new VConfig) 202 val debugVtype = VType.toVtypeStruct(debugVconfig.vtype).asUInt 203 val debugVl = debugVconfig.vl 204 csrio.vpu.set_vxsat := ctrlBlock.io.robio.csr.vxsat 205 csrio.vpu.set_vstart.valid := ctrlBlock.io.robio.csr.vcsrFlag 206 csrio.vpu.set_vstart.bits := 0.U 207 csrio.vpu.set_vtype.valid := ctrlBlock.io.robio.csr.vcsrFlag 208 csrio.vpu.set_vtype.bits := ZeroExt(debugVtype, XLEN) 209 csrio.vpu.set_vl.valid := ctrlBlock.io.robio.csr.vcsrFlag 210 csrio.vpu.set_vl.bits := ZeroExt(debugVl, XLEN) 211 csrio.exception := ctrlBlock.io.robio.exception 212 csrio.memExceptionVAddr := io.mem.exceptionVAddr 213 csrio.externalInterrupt := io.fromTop.externalInterrupt 214 csrio.distributedUpdate(0) := io.mem.csrDistributedUpdate 215 csrio.distributedUpdate(1) := io.frontendCsrDistributedUpdate 216 csrio.perf <> io.perf 217 private val fenceio = intExuBlock.io.fenceio.get 218 fenceio.disableSfence := csrio.disableSfence 219 io.fenceio <> fenceio 220 221 vfExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 222 for (i <- 0 until vfExuBlock.io.in.size) { 223 for (j <- 0 until vfExuBlock.io.in(i).size) { 224 NewPipelineConnect(dataPath.io.toFpExu(i)(j), vfExuBlock.io.in(i)(j), vfExuBlock.io.in(i)(j).fire, 225 Mux(dataPath.io.toFpExu(i)(j).fire, 226 dataPath.io.toFpExu(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush), 227 vfExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush))) 228 } 229 } 230 vfExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 231 232 wbDataPath.io.flush := ctrlBlock.io.redirect 233 wbDataPath.io.fromTop.hartId := io.fromTop.hartId 234 wbDataPath.io.fromIntExu <> intExuBlock.io.out 235 wbDataPath.io.fromVfExu <> vfExuBlock.io.out 236 wbDataPath.io.fromMemExu.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 237 sink.valid := source.valid 238 source.ready := sink.ready 239 sink.bits.data := source.bits.data 240 sink.bits.pdest := source.bits.uop.pdest 241 sink.bits.robIdx := source.bits.uop.robIdx 242 sink.bits.intWen.foreach(_ := source.bits.uop.rfWen) 243 sink.bits.fpWen.foreach(_ := source.bits.uop.fpWen) 244 sink.bits.vecWen.foreach(_ := source.bits.uop.vecWen) 245 sink.bits.exceptionVec.foreach(_ := source.bits.uop.exceptionVec) 246 sink.bits.flushPipe.foreach(_ := source.bits.uop.flushPipe) 247 sink.bits.replay.foreach(_ := source.bits.uop.replayInst) 248 sink.bits.debug := source.bits.debug 249 sink.bits.debugInfo := 0.U.asTypeOf(sink.bits.debugInfo) 250 sink.bits.lqIdx.foreach(_ := source.bits.uop.lqIdx) 251 sink.bits.sqIdx.foreach(_ := source.bits.uop.sqIdx) 252 sink.bits.ftqIdx.foreach(_ := source.bits.uop.ftqPtr) 253 sink.bits.ftqOffset.foreach(_ := source.bits.uop.ftqOffset) 254 } 255 256 // to mem 257 io.mem.redirect := ctrlBlock.io.redirect 258 io.mem.issueUops.zip(dataPath.io.toMemExu.flatten).foreach { case (sink, source) => 259 sink.valid := source.valid 260 source.ready := sink.ready 261 sink.bits.iqIdx := source.bits.iqIdx 262 sink.bits.isFirstIssue := source.bits.isFirstIssue 263 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 264 sink.bits.src := 0.U.asTypeOf(sink.bits.src) 265 sink.bits.src.zip(source.bits.src).foreach { case (l, r) => l := r} 266 sink.bits.uop.fuType := source.bits.fuType 267 sink.bits.uop.fuOpType := source.bits.fuOpType 268 sink.bits.uop.imm := source.bits.imm 269 sink.bits.uop.robIdx := source.bits.robIdx 270 sink.bits.uop.pdest := source.bits.pdest 271 sink.bits.uop.rfWen := source.bits.rfWen.getOrElse(false.B) 272 sink.bits.uop.fpWen := source.bits.fpWen.getOrElse(false.B) 273 sink.bits.uop.vecWen := source.bits.vecWen.getOrElse(false.B) 274 sink.bits.uop.flushPipe := source.bits.flushPipe.getOrElse(false.B) 275 sink.bits.uop.pc := source.bits.pc.getOrElse(0.U) 276 sink.bits.uop.lqIdx := source.bits.lqIdx.getOrElse(0.U.asTypeOf(new LqPtr)) 277 sink.bits.uop.sqIdx := source.bits.sqIdx.getOrElse(0.U.asTypeOf(new SqPtr)) 278 sink.bits.uop.ftqPtr := source.bits.ftqIdx.getOrElse(0.U.asTypeOf(new FtqPtr)) 279 sink.bits.uop.ftqOffset := source.bits.ftqOffset.getOrElse(0.U) 280 } 281 io.mem.loadFastMatch := memScheduler.io.toMem.get.loadFastMatch.map(_.fastMatch) 282 io.mem.loadFastImm := memScheduler.io.toMem.get.loadFastMatch.map(_.fastImm) 283 io.mem.tlbCsr := csrio.tlb 284 io.mem.csrCtrl := csrio.customCtrl 285 io.mem.sfence := fenceio.sfence 286 io.mem.isStoreException := CommitType.lsInstIsStore(ctrlBlock.io.robio.exception.bits.commitType) 287 require(io.mem.loadPcRead.size == params.LduCnt) 288 io.mem.loadPcRead.zipWithIndex.foreach { case (loadPcRead, i) => 289 loadPcRead.data := ctrlBlock.io.memLdPcRead(i).data 290 ctrlBlock.io.memLdPcRead(i).ptr := loadPcRead.ptr 291 ctrlBlock.io.memLdPcRead(i).offset := loadPcRead.offset 292 } 293 // mem io 294 io.mem.lsqEnqIO <> memScheduler.io.memIO.get.lsqEnqIO 295 io.mem.robLsqIO <> ctrlBlock.io.robio.lsq 296 io.mem.toSbuffer <> fenceio.sbuffer 297 298 io.frontendSfence := fenceio.sfence 299 io.frontendTlbCsr := csrio.tlb 300 io.frontendCsrCtrl := csrio.customCtrl 301 302 io.tlb <> csrio.tlb 303 304 io.csrCustomCtrl := csrio.customCtrl 305 306 dontTouch(memScheduler.io) 307 dontTouch(io.mem) 308 dontTouch(dataPath.io.toMemExu) 309 dontTouch(wbDataPath.io.fromMemExu) 310} 311 312class BackendMemIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 313 // params alias 314 private val LoadQueueSize = VirtualLoadQueueSize 315 // In/Out // Todo: split it into one-direction bundle 316 val lsqEnqIO = Flipped(new LsqEnqIO) 317 val robLsqIO = new RobLsqIO 318 val toSbuffer = new FenceToSbuffer 319 val ldaIqFeedback = Vec(params.LduCnt, Flipped(new MemRSFeedbackIO)) 320 val staIqFeedback = Vec(params.StaCnt, Flipped(new MemRSFeedbackIO)) 321 val loadPcRead = Vec(params.LduCnt, Flipped(new FtqRead(UInt(VAddrBits.W)))) 322 323 // Input 324 val writeBack = MixedVec(Seq.fill(params.LduCnt + params.StaCnt * 2)(Flipped(DecoupledIO(new MemExuOutput()))) ++ Seq.fill(params.VlduCnt)(Flipped(DecoupledIO(new MemExuOutput(true))))) 325 326 val s3_delayed_load_error = Input(Vec(LoadPipelineWidth, Bool())) 327 val stIn = Input(Vec(params.StaCnt, ValidIO(new DynInst()))) 328 val memoryViolation = Flipped(ValidIO(new Redirect)) 329 val exceptionVAddr = Input(UInt(VAddrBits.W)) 330 val sqDeq = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) 331 val lqDeq = Input(UInt(log2Up(CommitWidth + 1).W)) 332 333 val lqCancelCnt = Input(UInt(log2Up(VirtualLoadQueueSize + 1).W)) 334 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 335 336 val otherFastWakeup = Flipped(Vec(params.LduCnt + 2 * params.StaCnt, ValidIO(new DynInst))) 337 val stIssuePtr = Input(new SqPtr()) 338 339 val csrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 340 341 // Output 342 val redirect = ValidIO(new Redirect) // rob flush MemBlock 343 val issueUops = MixedVec(Seq.fill(params.LduCnt + params.StaCnt * 2)(DecoupledIO(new MemExuInput())) ++ Seq.fill(params.VlduCnt)(DecoupledIO(new MemExuInput(true)))) 344 val loadFastMatch = Vec(params.LduCnt, Output(UInt(params.LduCnt.W))) 345 val loadFastImm = Vec(params.LduCnt, Output(UInt(12.W))) // Imm_I 346 347 val tlbCsr = Output(new TlbCsrBundle) 348 val csrCtrl = Output(new CustomCSRCtrlIO) 349 val sfence = Output(new SfenceBundle) 350 val isStoreException = Output(Bool()) 351} 352 353class BackendIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 354 val fromTop = new Bundle { 355 val hartId = Input(UInt(8.W)) 356 val externalInterrupt = new ExternalInterruptIO 357 } 358 359 val toTop = new Bundle { 360 val cpuHalted = Output(Bool()) 361 } 362 363 val fenceio = new FenceIO 364 // Todo: merge these bundles into BackendFrontendIO 365 val frontend = Flipped(new FrontendToCtrlIO) 366 val frontendSfence = Output(new SfenceBundle) 367 val frontendCsrCtrl = Output(new CustomCSRCtrlIO) 368 val frontendTlbCsr = Output(new TlbCsrBundle) 369 // distributed csr write 370 val frontendCsrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 371 372 val mem = new BackendMemIO 373 374 val perf = Input(new PerfCounterIO) 375 376 val tlb = Output(new TlbCsrBundle) 377 378 val csrCustomCtrl = Output(new CustomCSRCtrlIO) 379} 380