1package xiangshan.backend 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import utility.{PipelineConnect, ZeroExt} 8import xiangshan._ 9import xiangshan.backend.Bundles.{DynInst, MemExuInput, MemExuOutput, FuBusyTableWriteBundle} 10import xiangshan.backend.ctrlblock.CtrlBlock 11import xiangshan.backend.datapath.WbConfig._ 12import xiangshan.backend.datapath.{DataPath, WbDataPath} 13import xiangshan.backend.exu.ExuBlock 14import xiangshan.backend.fu.vector.Bundles.{VConfig, VType} 15import xiangshan.backend.fu.{FenceIO, FenceToSbuffer, PerfCounterIO, FuConfig} 16import xiangshan.backend.issue.{Scheduler, IntScheduler, MemScheduler, VfScheduler} 17import xiangshan.backend.rob.RobLsqIO 18import xiangshan.frontend.{FtqPtr, FtqRead} 19import xiangshan.mem.{LqPtr, LsqEnqIO, SqPtr} 20 21class Backend(val params: BackendParams)(implicit p: Parameters) extends LazyModule 22 with HasXSParameter { 23 24 for (exuCfg <- params.allExuParams) { 25 val fuConfigs = exuCfg.fuConfigs 26 val wbPortConfigs = exuCfg.wbPortConfigs 27 val immType = exuCfg.immType 28 println(s"exu: ${fuConfigs.map(_.name)}, wb: ${wbPortConfigs}, imm: ${immType}") 29 require(wbPortConfigs.collectFirst { case x: IntWB => x }.nonEmpty == 30 fuConfigs.map(_.writeIntRf).reduce(_ || _), 31 "int wb port has no priority" ) 32 require(wbPortConfigs.collectFirst { case x: VfWB => x }.nonEmpty == 33 fuConfigs.map(x => x.writeFpRf || x.writeVecRf).reduce(_ || _), 34 "vec wb port has no priority" ) 35 } 36 37 println(s"Function Unit: Alu(${params.AluCnt}), Brh(${params.BrhCnt}), Jmp(${params.JmpCnt}), " + 38 s"Ldu(${params.LduCnt}), Sta(${params.StaCnt}), Std(${params.StdCnt})") 39 40 for (cfg <- FuConfig.allConfigs) { 41 println(s"[Backend] $cfg") 42 } 43 44 val ctrlBlock = LazyModule(new CtrlBlock(params)) 45 val intScheduler = params.intSchdParams.map(x => LazyModule(new Scheduler(x))) 46 val vfScheduler = params.vfSchdParams.map(x => LazyModule(new Scheduler(x))) 47 val memScheduler = params.memSchdParams.map(x => LazyModule(new Scheduler(x))) 48 val dataPath = LazyModule(new DataPath(params)) 49 val intExuBlock = params.intSchdParams.map(x => LazyModule(new ExuBlock(x))) 50 val vfExuBlock = params.vfSchdParams.map(x => LazyModule(new ExuBlock(x))) 51 52 lazy val module = new BackendImp(this) 53} 54 55class BackendImp(override val wrapper: Backend)(implicit p: Parameters) extends LazyModuleImp(wrapper) 56 with HasXSParameter{ 57 implicit private val params = wrapper.params 58 val io = IO(new BackendIO()(p, wrapper.params)) 59 60 private val ctrlBlock = wrapper.ctrlBlock.module 61 private val intScheduler = wrapper.intScheduler.get.module 62 private val vfScheduler = wrapper.vfScheduler.get.module 63 private val memScheduler = wrapper.memScheduler.get.module 64 private val dataPath = wrapper.dataPath.module 65 private val intExuBlock = wrapper.intExuBlock.get.module 66 private val vfExuBlock = wrapper.vfExuBlock.get.module 67 private val wbDataPath = Module(new WbDataPath(params)) 68 69 private val (intRespWrite, vfRespWrite, memRespWrite) = (intScheduler.io.wbFuBusyTable.fuBusyTableWrite, 70 vfScheduler.io.wbFuBusyTable.fuBusyTableWrite, 71 memScheduler.io.wbFuBusyTable.fuBusyTableWrite) 72 private val (intRespRead, vfRespRead, memRespRead) = (intScheduler.io.wbFuBusyTable.fuBusyTableRead, 73 vfScheduler.io.wbFuBusyTable.fuBusyTableRead, 74 memScheduler.io.wbFuBusyTable.fuBusyTableRead) 75 private val allRespWrite = (intRespWrite ++ vfRespWrite ++ memRespWrite).flatten 76 private val allRespRead = (intRespRead ++ vfRespRead ++ memRespRead).flatten 77 wbDataPath.io.fromIntExu.flatten.filter(x => x.bits.params.writeIntRf) 78 private val allExuParams = params.allExuParams 79 private val respWriteWithParams = allRespWrite.zip(allExuParams) 80 81 private val intWBFuGroup = params.getIntWBExeGroup.map{case(groupId, exeUnit) => (groupId, exeUnit.flatMap(_.fuConfigs))} 82 private val intLatencyCertains = intWBFuGroup.map{case (k,v) => (k, v.map(_.latency.latencyVal.nonEmpty).reduce(_ && _))} 83 private val intWBFuLatencyMap = intLatencyCertains.map{case (k, latencyCertain) => 84 if (latencyCertain) Some(intWBFuGroup(k).map(y => (y.fuType, y.latency.latencyVal.get))) 85 else None 86 }.toSeq 87 private val intWBFuLatencyValMax = intWBFuLatencyMap.map(latencyMap=> latencyMap.map(x => x.map(_._2).max)) 88 89 private val vfWBFuGroup = params.getVfWBExeGroup.map{case(groupId, exeUnit) => (groupId, exeUnit.flatMap(_.fuConfigs))} 90 private val vfLatencyCertains = vfWBFuGroup.map{case (k,v) => (k, v.map(_.latency.latencyVal.nonEmpty).reduce(_ && _))} 91 val vfWBFuLatencyMap = vfLatencyCertains.map { case (k, latencyCertain) => 92 if (latencyCertain) Some(vfWBFuGroup(k).map(y => (y.fuType, y.latency.latencyVal.get))) 93 else None 94 }.toSeq 95 private val vfWBFuLatencyValMax = vfWBFuLatencyMap.map(latencyMap => latencyMap.map(x => x.map(_._2).max)) 96 97 private val intWBFuBusyTable = intWBFuLatencyValMax.map { case y => if (y.getOrElse(0)>0) Some(Reg(UInt(y.getOrElse(1).W))) else None } 98 private val vfWBFuBusyTable = vfWBFuLatencyValMax.map { case y => if (y.getOrElse(0)>0) Some(Reg(UInt(y.getOrElse(1).W))) else None } 99 100 // intWBFuBusyTable write 101 for (i <- 0 until intWBFuGroup.size) { 102 if (intWBFuBusyTable(i).nonEmpty){ 103 val deqIsLatencyNumMask = respWriteWithParams.zipWithIndex.map{ case((r, p), idx) => 104 val resps = p.schdType match { 105 case IntScheduler() => Seq(r.deqResp, r.og0Resp, r.og1Resp) 106 case MemScheduler() => Seq(r.deqResp, r.og1Resp) 107 case VfScheduler() => Seq(r.deqResp, r.og1Resp) 108 case _ => null 109 } 110 val matchI = (p.wbPortConfigs.collectFirst{ case x: IntWB => x }.getOrElse(-1)) == i 111 if(matchI){ 112 Mux(resps(0).valid && resps(0).bits.respType === RSFeedbackType.issueSuccess, 113 Cat((0 until intWBFuLatencyValMax(i).get).map { case num => 114 val latencyNumFuType = p.fuConfigs.filter(_.latency.latencyVal.getOrElse(-1) == num+1).map(_.fuType) 115 val isLatencyNum = Cat(latencyNumFuType.map(futype => resps(0).bits.fuType === futype.U)).asUInt().orR() // The latency of the deqResp inst is Num 116 isLatencyNum 117 }), 118 0.U) 119 } else 0.U 120 }.reduce(_|_) 121 val og0IsLatencyNumMask = WireInit(-1.S.asTypeOf(deqIsLatencyNumMask)) 122 og0IsLatencyNumMask := respWriteWithParams.zipWithIndex.map { case ((r, p), idx) => 123 val resps = p.schdType match { 124 case IntScheduler() => Seq(r.deqResp, r.og0Resp, r.og1Resp) 125 case MemScheduler() => Seq(r.deqResp, r.og1Resp) 126 case VfScheduler() => Seq(r.deqResp, r.og1Resp) 127 case _ => null 128 } 129 val matchI = (p.wbPortConfigs.collectFirst { case x: IntWB => x }.getOrElse(-1)) == i 130 if (matchI) { 131 Mux(resps(1).valid && resps(1).bits.respType === RSFeedbackType.issueSuccess, 132 ~(Cat(Cat((0 until intWBFuLatencyValMax(i).get).map { case num => 133 val latencyNumFuType = p.fuConfigs.filter(_.latency.latencyVal.getOrElse(-1) == num + 1).map(_.fuType) 134 val isLatencyNum = Cat(latencyNumFuType.map(futype => resps(1).bits.fuType === futype.U)).asUInt().orR() // The latency of the deqResp inst is Num 135 isLatencyNum 136 }), 0.U(1.W))), 137 -1.S.asTypeOf(deqIsLatencyNumMask)).asTypeOf(deqIsLatencyNumMask) 138 } else -1.S.asTypeOf(deqIsLatencyNumMask) 139 }.reduce(_|_) 140 val og1IsLatencyNumMask = WireInit(-1.S.asTypeOf(deqIsLatencyNumMask)) 141 og1IsLatencyNumMask := respWriteWithParams.zipWithIndex.map { case ((r, p), idx) => 142 val resps = p.schdType match { 143 case IntScheduler() => Seq(r.deqResp, r.og0Resp, r.og1Resp) 144 case MemScheduler() => Seq(r.deqResp, r.og1Resp) 145 case VfScheduler() => Seq(r.deqResp, r.og1Resp) 146 case _ => null 147 } 148 val matchI = (p.wbPortConfigs.collectFirst { case x: IntWB => x }.getOrElse(-1)) == i 149 if (matchI && resps.length==3) { 150 Mux(resps(2).valid && resps(2).bits.respType === RSFeedbackType.issueSuccess, 151 ~(Cat(Cat((0 until intWBFuLatencyValMax(i).get).map { case num => 152 val latencyNumFuType = p.fuConfigs.filter(_.latency.latencyVal.getOrElse(-1) == num + 1).map(_.fuType) 153 val isLatencyNum = Cat(latencyNumFuType.map(futype => resps(2).bits.fuType === futype.U)).asUInt().orR() // The latency of the deqResp inst is Num 154 isLatencyNum 155 }), 0.U(1.W))), 156 -1.S.asTypeOf(deqIsLatencyNumMask)).asTypeOf(deqIsLatencyNumMask) 157 } else -1.S.asTypeOf(deqIsLatencyNumMask) 158 }.reduce(_ | _) 159 intWBFuBusyTable(i).get := ((intWBFuBusyTable(i).get << 1.U).asUInt() | deqIsLatencyNumMask) & og0IsLatencyNumMask.asUInt() & og1IsLatencyNumMask.asUInt() 160 } 161 } 162 // intWBFuBusyTable read 163 for(i <- 0 until allRespRead.size){ 164 allRespRead(i) := intWBFuBusyTable.zipWithIndex.map{ case (ele, idx) => 165 val matchI = (allExuParams(i).wbPortConfigs.collectFirst { case x: IntWB => x }.getOrElse(-1)) == idx 166 if(ele.nonEmpty && matchI){ 167 ele.get.asTypeOf(allRespRead(i)) 168 }else{ 169 0.U.asTypeOf(allRespRead(i)) 170 } 171 }.reduce(_|_) 172 } 173 174 ctrlBlock.io.fromTop.hartId := io.fromTop.hartId 175 ctrlBlock.io.frontend <> io.frontend 176 ctrlBlock.io.fromWB.wbData <> wbDataPath.io.toCtrlBlock.writeback 177 ctrlBlock.io.fromMem.stIn <> io.mem.stIn 178 ctrlBlock.io.fromMem.violation <> io.mem.memoryViolation 179 ctrlBlock.io.csrCtrl <> intExuBlock.io.csrio.get.customCtrl 180 ctrlBlock.io.robio.csr.intrBitSet := intExuBlock.io.csrio.get.interrupt 181 ctrlBlock.io.robio.csr.trapTarget := intExuBlock.io.csrio.get.trapTarget 182 ctrlBlock.io.robio.csr.isXRet := intExuBlock.io.csrio.get.isXRet 183 ctrlBlock.io.robio.csr.wfiEvent := intExuBlock.io.csrio.get.wfi_event 184 ctrlBlock.io.robio.lsq <> io.mem.robLsqIO 185 186 intScheduler.io.fromTop.hartId := io.fromTop.hartId 187 intScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 188 intScheduler.io.fromCtrlBlock.pcVec := ctrlBlock.io.toIssueBlock.pcVec 189 intScheduler.io.fromCtrlBlock.targetVec := ctrlBlock.io.toIssueBlock.targetVec 190 intScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 191 intScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.intUops 192 intScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 193 intScheduler.io.vfWriteBack := 0.U.asTypeOf(intScheduler.io.vfWriteBack) 194 195 memScheduler.io.fromTop.hartId := io.fromTop.hartId 196 memScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 197 memScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 198 memScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.memUops 199 memScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 200 memScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 201 memScheduler.io.fromMem.get.scommit := io.mem.sqDeq 202 memScheduler.io.fromMem.get.lcommit := io.mem.lqDeq 203 memScheduler.io.fromMem.get.sqCancelCnt := io.mem.sqCancelCnt 204 memScheduler.io.fromMem.get.lqCancelCnt := io.mem.lqCancelCnt 205 memScheduler.io.fromMem.get.stIssuePtr := io.mem.stIssuePtr 206 memScheduler.io.fromMem.get.memWaitUpdateReq.staIssue.zip(io.mem.stIn).foreach { case (sink, source) => 207 sink.valid := source.valid 208 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 209 sink.bits.uop.robIdx := source.bits.robIdx 210 } 211 io.mem.ldaIqFeedback <> memScheduler.io.fromMem.get.ldaFeedback 212 io.mem.staIqFeedback <> memScheduler.io.fromMem.get.staFeedback 213 214 vfScheduler.io.fromTop.hartId := io.fromTop.hartId 215 vfScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 216 vfScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 217 vfScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.vfUops 218 vfScheduler.io.intWriteBack := 0.U.asTypeOf(vfScheduler.io.intWriteBack) 219 vfScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 220 221 dataPath.io.flush := ctrlBlock.io.toDataPath.flush 222 dataPath.io.vconfigReadPort.addr := ctrlBlock.io.toDataPath.vtypeAddr 223 val vconfig = dataPath.io.vconfigReadPort.data 224 ctrlBlock.io.fromDataPath.vtype := vconfig(7, 0).asTypeOf(new VType) 225 for (i <- 0 until dataPath.io.fromIntIQ.length) { 226 for (j <- 0 until dataPath.io.fromIntIQ(i).length) { 227 PipelineConnect(intScheduler.io.toDataPath(i)(j), dataPath.io.fromIntIQ(i)(j), dataPath.io.fromIntIQ(i)(j).valid, 228 intScheduler.io.toDataPath(i)(j).bits.common.robIdx.needFlush(ctrlBlock.io.toDataPath.flush)) 229 intScheduler.io.fromDataPath(i)(j) := dataPath.io.toIntIQ(i)(j) 230 } 231 } 232 233 dataPath.io.fromVfIQ <> vfScheduler.io.toDataPath 234 vfScheduler.io.fromDataPath := dataPath.io.toVfIQ 235 dataPath.io.fromMemIQ <> memScheduler.io.toDataPath 236 memScheduler.io.fromDataPath := dataPath.io.toMemIQ 237 238 println(s"[Backend] wbDataPath.io.toIntPreg: ${wbDataPath.io.toIntPreg.size}, dataPath.io.fromIntWb: ${dataPath.io.fromIntWb.size}") 239 println(s"[Backend] wbDataPath.io.toVfPreg: ${wbDataPath.io.toVfPreg.size}, dataPath.io.fromFpWb: ${dataPath.io.fromVfWb.size}") 240 dataPath.io.fromIntWb := wbDataPath.io.toIntPreg 241 dataPath.io.fromVfWb := wbDataPath.io.toVfPreg 242 dataPath.io.debugIntRat := ctrlBlock.io.debug_int_rat 243 dataPath.io.debugFpRat := ctrlBlock.io.debug_fp_rat 244 dataPath.io.debugVecRat := ctrlBlock.io.debug_vec_rat 245 dataPath.io.debugVconfigRat := ctrlBlock.io.debug_vconfig_rat 246 247 intExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 248 for (i <- 0 until intExuBlock.io.in.length) { 249 for (j <- 0 until intExuBlock.io.in(i).length) { 250 PipelineConnect(dataPath.io.toIntExu(i)(j), intExuBlock.io.in(i)(j), intExuBlock.io.in(i)(j).fire, 251 Mux(dataPath.io.toIntExu(i)(j).fire, 252 dataPath.io.toIntExu(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush), 253 intExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush))) 254 } 255 } 256 257 private val csrio = intExuBlock.io.csrio.get 258 csrio.hartId := io.fromTop.hartId 259 csrio.perf.retiredInstr <> ctrlBlock.io.robio.csr.perfinfo.retiredInstr 260 csrio.perf.ctrlInfo <> ctrlBlock.io.perfInfo.ctrlInfo 261 csrio.perf.perfEventsCtrl <> ctrlBlock.getPerf 262 csrio.fpu.fflags := ctrlBlock.io.robio.csr.fflags 263 csrio.fpu.isIllegal := false.B // Todo: remove it 264 csrio.fpu.dirty_fs := ctrlBlock.io.robio.csr.dirty_fs 265 csrio.vpu <> 0.U.asTypeOf(csrio.vpu) // Todo 266 267 val debugVconfig = dataPath.io.debugVconfig.asTypeOf(new VConfig) 268 val debugVtype = VType.toVtypeStruct(debugVconfig.vtype).asUInt 269 val debugVl = debugVconfig.vl 270 csrio.vpu.set_vxsat := ctrlBlock.io.robio.csr.vxsat 271 csrio.vpu.set_vstart.valid := ctrlBlock.io.robio.csr.vcsrFlag 272 csrio.vpu.set_vstart.bits := 0.U 273 csrio.vpu.set_vtype.valid := ctrlBlock.io.robio.csr.vcsrFlag 274 csrio.vpu.set_vtype.bits := ZeroExt(debugVtype, XLEN) 275 csrio.vpu.set_vl.valid := ctrlBlock.io.robio.csr.vcsrFlag 276 csrio.vpu.set_vl.bits := ZeroExt(debugVl, XLEN) 277 csrio.exception := ctrlBlock.io.robio.exception 278 csrio.memExceptionVAddr := io.mem.exceptionVAddr 279 csrio.externalInterrupt := io.fromTop.externalInterrupt 280 csrio.distributedUpdate(0) := io.mem.csrDistributedUpdate 281 csrio.distributedUpdate(1) := io.frontendCsrDistributedUpdate 282 csrio.perf <> io.perf 283 private val fenceio = intExuBlock.io.fenceio.get 284 fenceio.disableSfence := csrio.disableSfence 285 io.fenceio <> fenceio 286 287 vfExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 288 for (i <- 0 until vfExuBlock.io.in.size) { 289 for (j <- 0 until vfExuBlock.io.in(i).size) { 290 PipelineConnect(dataPath.io.toFpExu(i)(j), vfExuBlock.io.in(i)(j), vfExuBlock.io.in(i)(j).fire, 291 Mux(dataPath.io.toFpExu(i)(j).fire, 292 dataPath.io.toFpExu(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush), 293 vfExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush))) 294 } 295 } 296 vfExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 297 298 wbDataPath.io.flush := ctrlBlock.io.redirect 299 wbDataPath.io.fromTop.hartId := io.fromTop.hartId 300 wbDataPath.io.fromIntExu <> intExuBlock.io.out 301 wbDataPath.io.fromVfExu <> vfExuBlock.io.out 302 wbDataPath.io.fromMemExu.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 303 sink.valid := source.valid 304 source.ready := sink.ready 305 sink.bits.data := source.bits.data 306 sink.bits.pdest := source.bits.uop.pdest 307 sink.bits.robIdx := source.bits.uop.robIdx 308 sink.bits.intWen.foreach(_ := source.bits.uop.rfWen) 309 sink.bits.fpWen.foreach(_ := source.bits.uop.fpWen) 310 sink.bits.vecWen.foreach(_ := source.bits.uop.vecWen) 311 sink.bits.exceptionVec.foreach(_ := source.bits.uop.exceptionVec) 312 sink.bits.flushPipe.foreach(_ := source.bits.uop.flushPipe) 313 sink.bits.replay.foreach(_ := source.bits.uop.replayInst) 314 sink.bits.debug := source.bits.debug 315 sink.bits.debugInfo := 0.U.asTypeOf(sink.bits.debugInfo) 316 sink.bits.lqIdx.foreach(_ := source.bits.uop.lqIdx) 317 sink.bits.sqIdx.foreach(_ := source.bits.uop.sqIdx) 318 sink.bits.ftqIdx.foreach(_ := source.bits.uop.ftqPtr) 319 sink.bits.ftqOffset.foreach(_ := source.bits.uop.ftqOffset) 320 } 321 322 // to mem 323 io.mem.redirect := ctrlBlock.io.redirect 324 io.mem.issueUops.zip(dataPath.io.toMemExu.flatten).foreach { case (sink, source) => 325 sink.valid := source.valid 326 source.ready := sink.ready 327 sink.bits.iqIdx := source.bits.iqIdx 328 sink.bits.isFirstIssue := source.bits.isFirstIssue 329 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 330 sink.bits.src := 0.U.asTypeOf(sink.bits.src) 331 sink.bits.src.zip(source.bits.src).foreach { case (l, r) => l := r} 332 sink.bits.uop.fuType := source.bits.fuType 333 sink.bits.uop.fuOpType := source.bits.fuOpType 334 sink.bits.uop.imm := source.bits.imm 335 sink.bits.uop.robIdx := source.bits.robIdx 336 sink.bits.uop.pdest := source.bits.pdest 337 sink.bits.uop.rfWen := source.bits.rfWen.getOrElse(false.B) 338 sink.bits.uop.fpWen := source.bits.fpWen.getOrElse(false.B) 339 sink.bits.uop.vecWen := source.bits.vecWen.getOrElse(false.B) 340 sink.bits.uop.flushPipe := source.bits.flushPipe.getOrElse(false.B) 341 sink.bits.uop.pc := source.bits.pc.getOrElse(0.U) 342 sink.bits.uop.lqIdx := source.bits.lqIdx.getOrElse(0.U.asTypeOf(new LqPtr)) 343 sink.bits.uop.sqIdx := source.bits.sqIdx.getOrElse(0.U.asTypeOf(new SqPtr)) 344 sink.bits.uop.ftqPtr := source.bits.ftqIdx.getOrElse(0.U.asTypeOf(new FtqPtr)) 345 sink.bits.uop.ftqOffset := source.bits.ftqOffset.getOrElse(0.U) 346 } 347 io.mem.loadFastMatch := memScheduler.io.toMem.get.loadFastMatch.map(_.fastMatch) 348 io.mem.loadFastImm := memScheduler.io.toMem.get.loadFastMatch.map(_.fastImm) 349 io.mem.tlbCsr := csrio.tlb 350 io.mem.csrCtrl := csrio.customCtrl 351 io.mem.sfence := fenceio.sfence 352 io.mem.isStoreException := CommitType.lsInstIsStore(ctrlBlock.io.robio.exception.bits.commitType) 353 require(io.mem.loadPcRead.size == params.LduCnt) 354 io.mem.loadPcRead.zipWithIndex.foreach { case (loadPcRead, i) => 355 loadPcRead.data := ctrlBlock.io.memLdPcRead(i).data 356 ctrlBlock.io.memLdPcRead(i).ptr := loadPcRead.ptr 357 ctrlBlock.io.memLdPcRead(i).offset := loadPcRead.offset 358 } 359 // mem io 360 io.mem.lsqEnqIO <> memScheduler.io.memIO.get.lsqEnqIO 361 io.mem.robLsqIO <> ctrlBlock.io.robio.lsq 362 io.mem.toSbuffer <> fenceio.sbuffer 363 364 io.frontendSfence := fenceio.sfence 365 io.frontendTlbCsr := csrio.tlb 366 io.frontendCsrCtrl := csrio.customCtrl 367 368 io.tlb <> csrio.tlb 369 370 io.csrCustomCtrl := csrio.customCtrl 371 372 dontTouch(memScheduler.io) 373 dontTouch(io.mem) 374 dontTouch(dataPath.io.toMemExu) 375 dontTouch(wbDataPath.io.fromMemExu) 376} 377 378class BackendMemIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 379 // params alias 380 private val LoadQueueSize = VirtualLoadQueueSize 381 // In/Out // Todo: split it into one-direction bundle 382 val lsqEnqIO = Flipped(new LsqEnqIO) 383 val robLsqIO = new RobLsqIO 384 val toSbuffer = new FenceToSbuffer 385 val ldaIqFeedback = Vec(params.LduCnt, Flipped(new MemRSFeedbackIO)) 386 val staIqFeedback = Vec(params.StaCnt, Flipped(new MemRSFeedbackIO)) 387 val loadPcRead = Vec(params.LduCnt, Flipped(new FtqRead(UInt(VAddrBits.W)))) 388 389 // Input 390 val writeBack = MixedVec(Seq.fill(params.LduCnt + params.StaCnt * 2)(Flipped(DecoupledIO(new MemExuOutput()))) ++ Seq.fill(params.VlduCnt)(Flipped(DecoupledIO(new MemExuOutput(true))))) 391 392 val s3_delayed_load_error = Input(Vec(LoadPipelineWidth, Bool())) 393 val stIn = Input(Vec(params.StaCnt, ValidIO(new DynInst()))) 394 val memoryViolation = Flipped(ValidIO(new Redirect)) 395 val exceptionVAddr = Input(UInt(VAddrBits.W)) 396 val sqDeq = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) 397 val lqDeq = Input(UInt(log2Up(CommitWidth + 1).W)) 398 399 val lqCancelCnt = Input(UInt(log2Up(VirtualLoadQueueSize + 1).W)) 400 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 401 402 val otherFastWakeup = Flipped(Vec(params.LduCnt + 2 * params.StaCnt, ValidIO(new DynInst))) 403 val stIssuePtr = Input(new SqPtr()) 404 405 val csrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 406 407 // Output 408 val redirect = ValidIO(new Redirect) // rob flush MemBlock 409 val issueUops = MixedVec(Seq.fill(params.LduCnt + params.StaCnt * 2)(DecoupledIO(new MemExuInput())) ++ Seq.fill(params.VlduCnt)(DecoupledIO(new MemExuInput(true)))) 410 val loadFastMatch = Vec(params.LduCnt, Output(UInt(params.LduCnt.W))) 411 val loadFastImm = Vec(params.LduCnt, Output(UInt(12.W))) // Imm_I 412 413 val tlbCsr = Output(new TlbCsrBundle) 414 val csrCtrl = Output(new CustomCSRCtrlIO) 415 val sfence = Output(new SfenceBundle) 416 val isStoreException = Output(Bool()) 417} 418 419class BackendIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 420 val fromTop = new Bundle { 421 val hartId = Input(UInt(8.W)) 422 val externalInterrupt = new ExternalInterruptIO 423 } 424 425 val toTop = new Bundle { 426 val cpuHalted = Output(Bool()) 427 } 428 429 val fenceio = new FenceIO 430 // Todo: merge these bundles into BackendFrontendIO 431 val frontend = Flipped(new FrontendToCtrlIO) 432 val frontendSfence = Output(new SfenceBundle) 433 val frontendCsrCtrl = Output(new CustomCSRCtrlIO) 434 val frontendTlbCsr = Output(new TlbCsrBundle) 435 // distributed csr write 436 val frontendCsrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 437 438 val mem = new BackendMemIO 439 440 val perf = Input(new PerfCounterIO) 441 442 val tlb = Output(new TlbCsrBundle) 443 444 val csrCustomCtrl = Output(new CustomCSRCtrlIO) 445} 446