1package xiangshan.backend 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import utility.ZeroExt 8import xiangshan._ 9import xiangshan.backend.Bundles.{DynInst, IssueQueueIQWakeUpBundle, MemExuInput, MemExuOutput} 10import xiangshan.backend.ctrlblock.{DebugLSIO, LsTopdownInfo} 11import xiangshan.backend.datapath.DataConfig.{IntData, VecData} 12import xiangshan.backend.datapath.RdConfig.{IntRD, VfRD} 13import xiangshan.backend.datapath.WbConfig._ 14import xiangshan.backend.datapath._ 15import xiangshan.backend.exu.ExuBlock 16import xiangshan.backend.fu.vector.Bundles.{VConfig, VType} 17import xiangshan.backend.fu.{FenceIO, FenceToSbuffer, FuConfig, PerfCounterIO} 18import xiangshan.backend.issue.{CancelNetwork, Scheduler} 19import xiangshan.backend.rob.RobLsqIO 20import xiangshan.frontend.{FtqPtr, FtqRead} 21import xiangshan.mem.{LqPtr, LsqEnqIO, SqPtr} 22 23class Backend(val params: BackendParams)(implicit p: Parameters) extends LazyModule 24 with HasXSParameter { 25 26 /* Only update the idx in mem-scheduler here 27 * Idx in other schedulers can be updated the same way if needed 28 * 29 * Also note that we filter out the 'stData issue-queues' when counting 30 */ 31 for ((ibp, idx) <- params.memSchdParams.get.issueBlockParams.filter(iq => iq.StdCnt == 0).zipWithIndex) { 32 ibp.updateIdx(idx) 33 } 34 35 println(params.iqWakeUpParams) 36 37 for ((schdCfg, i) <- params.allSchdParams.zipWithIndex) { 38 schdCfg.bindBackendParam(params) 39 } 40 41 for ((iqCfg, i) <- params.allIssueParams.zipWithIndex) { 42 iqCfg.bindBackendParam(params) 43 } 44 45 for ((exuCfg, i) <- params.allExuParams.zipWithIndex) { 46 exuCfg.updateIQWakeUpConfigs(params.iqWakeUpParams) 47 exuCfg.updateExuIdx(i) 48 exuCfg.bindBackendParam(params) 49 } 50 51 println("[Backend] ExuConfigs:") 52 for (exuCfg <- params.allExuParams) { 53 val fuConfigs = exuCfg.fuConfigs 54 val wbPortConfigs = exuCfg.wbPortConfigs 55 val immType = exuCfg.immType 56 57 println("[Backend] " + 58 s"${exuCfg.name}: " + 59 s"${fuConfigs.map(_.name).mkString("fu(s): {", ",", "}")}, " + 60 s"${wbPortConfigs.mkString("wb: {", ",", "}")}, " + 61 s"${immType.map(SelImm.mkString(_)).mkString("imm: {", ",", "}")}, " + 62 s"latMax(${exuCfg.latencyValMax}), ${exuCfg.fuLatancySet.mkString("lat: {", ",", "}")}, " 63 ) 64 require( 65 wbPortConfigs.collectFirst { case x: IntWB => x }.nonEmpty == 66 fuConfigs.map(_.writeIntRf).reduce(_ || _), 67 "int wb port has no priority" 68 ) 69 require( 70 wbPortConfigs.collectFirst { case x: VfWB => x }.nonEmpty == 71 fuConfigs.map(x => x.writeFpRf || x.writeVecRf).reduce(_ || _), 72 "vec wb port has no priority" 73 ) 74 } 75 76 println(s"[Backend] all fu configs") 77 for (cfg <- FuConfig.allConfigs) { 78 println(s"[Backend] $cfg") 79 } 80 81 println(s"[Backend] Int RdConfigs: ExuName(Priority)") 82 for ((port, seq) <- params.getRdPortParams(IntData())) { 83 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 84 } 85 86 println(s"[Backend] Int WbConfigs: ExuName(Priority)") 87 for ((port, seq) <- params.getWbPortParams(IntData())) { 88 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 89 } 90 91 println(s"[Backend] Vf RdConfigs: ExuName(Priority)") 92 for ((port, seq) <- params.getRdPortParams(VecData())) { 93 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 94 } 95 96 println(s"[Backend] Vf WbConfigs: ExuName(Priority)") 97 for ((port, seq) <- params.getWbPortParams(VecData())) { 98 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 99 } 100 101 val ctrlBlock = LazyModule(new CtrlBlock(params)) 102 val intScheduler = params.intSchdParams.map(x => LazyModule(new Scheduler(x))) 103 val vfScheduler = params.vfSchdParams.map(x => LazyModule(new Scheduler(x))) 104 val memScheduler = params.memSchdParams.map(x => LazyModule(new Scheduler(x))) 105 val cancelNetwork = LazyModule(new CancelNetwork(params)) 106 val dataPath = LazyModule(new DataPath(params)) 107 val intExuBlock = params.intSchdParams.map(x => LazyModule(new ExuBlock(x))) 108 val vfExuBlock = params.vfSchdParams.map(x => LazyModule(new ExuBlock(x))) 109 val wbFuBusyTable = LazyModule(new WbFuBusyTable(params)) 110 111 lazy val module = new BackendImp(this) 112} 113 114class BackendImp(override val wrapper: Backend)(implicit p: Parameters) extends LazyModuleImp(wrapper) 115 with HasXSParameter { 116 implicit private val params = wrapper.params 117 118 val io = IO(new BackendIO()(p, wrapper.params)) 119 120 private val ctrlBlock = wrapper.ctrlBlock.module 121 private val intScheduler = wrapper.intScheduler.get.module 122 private val vfScheduler = wrapper.vfScheduler.get.module 123 private val memScheduler = wrapper.memScheduler.get.module 124 private val cancelNetwork = wrapper.cancelNetwork.module 125 private val dataPath = wrapper.dataPath.module 126 private val intExuBlock = wrapper.intExuBlock.get.module 127 private val vfExuBlock = wrapper.vfExuBlock.get.module 128 private val bypassNetwork = Module(new BypassNetwork) 129 private val wbDataPath = Module(new WbDataPath(params)) 130 private val wbFuBusyTable = wrapper.wbFuBusyTable.module 131 132 private val iqWakeUpMappedBundle: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = ( 133 intScheduler.io.toSchedulers.wakeupVec ++ 134 vfScheduler.io.toSchedulers.wakeupVec ++ 135 memScheduler.io.toSchedulers.wakeupVec 136 ).map(x => (x.bits.exuIdx, x)).toMap 137 138 println(s"[Backend] iq wake up keys: ${iqWakeUpMappedBundle.keys}") 139 140 wbFuBusyTable.io.in.intSchdBusyTable := intScheduler.io.wbFuBusyTable 141 wbFuBusyTable.io.in.vfSchdBusyTable := vfScheduler.io.wbFuBusyTable 142 wbFuBusyTable.io.in.memSchdBusyTable := memScheduler.io.wbFuBusyTable 143 intScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.intRespRead 144 vfScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.vfRespRead 145 memScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.memRespRead 146 dataPath.io.wbConfictRead := wbFuBusyTable.io.out.wbConflictRead 147 148 wbDataPath.io.fromIntExu.flatten.filter(x => x.bits.params.writeIntRf) 149 150 private val vconfig = dataPath.io.vconfigReadPort.data 151 private val og1CancelVec: Vec[Bool] = dataPath.io.og1CancelVec 152 private val og0CancelVecFromDataPath: Vec[Bool] = dataPath.io.og0CancelVec 153 private val og0CancelVecFromCancelNet: Vec[Bool] = cancelNetwork.io.out.og0CancelVec 154 private val og0CancelVec: Vec[Bool] = VecInit(og0CancelVecFromDataPath.zip(og0CancelVecFromCancelNet).map(x => x._1 | x._2)) 155 156 ctrlBlock.io.fromTop.hartId := io.fromTop.hartId 157 ctrlBlock.io.frontend <> io.frontend 158 ctrlBlock.io.fromWB.wbData <> wbDataPath.io.toCtrlBlock.writeback 159 ctrlBlock.io.fromMem.stIn <> io.mem.stIn 160 ctrlBlock.io.fromMem.violation <> io.mem.memoryViolation 161 ctrlBlock.io.lqCanAccept := io.mem.lqCanAccept 162 ctrlBlock.io.sqCanAccept := io.mem.sqCanAccept 163 ctrlBlock.io.csrCtrl <> intExuBlock.io.csrio.get.customCtrl 164 ctrlBlock.io.robio.csr.intrBitSet := intExuBlock.io.csrio.get.interrupt 165 ctrlBlock.io.robio.csr.trapTarget := intExuBlock.io.csrio.get.trapTarget 166 ctrlBlock.io.robio.csr.isXRet := intExuBlock.io.csrio.get.isXRet 167 ctrlBlock.io.robio.csr.wfiEvent := intExuBlock.io.csrio.get.wfi_event 168 ctrlBlock.io.robio.lsq <> io.mem.robLsqIO 169 ctrlBlock.io.robio.lsTopdownInfo <> io.mem.lsTopdownInfo 170 ctrlBlock.io.robio.debug_ls <> io.mem.debugLS 171 ctrlBlock.io.fromDataPath.vtype := vconfig(7, 0).asTypeOf(new VType) 172 173 intScheduler.io.fromTop.hartId := io.fromTop.hartId 174 intScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 175 intScheduler.io.fromCtrlBlock.pcVec := ctrlBlock.io.toIssueBlock.pcVec 176 intScheduler.io.fromCtrlBlock.targetVec := ctrlBlock.io.toIssueBlock.targetVec 177 intScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 178 intScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.intUops 179 intScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 180 intScheduler.io.vfWriteBack := 0.U.asTypeOf(intScheduler.io.vfWriteBack) 181 intScheduler.io.fromDataPath.resp := dataPath.io.toIntIQ 182 intScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 183 intScheduler.io.fromDataPath.og0Cancel := og0CancelVec 184 intScheduler.io.fromDataPath.og1Cancel := og1CancelVec 185 186 memScheduler.io.fromTop.hartId := io.fromTop.hartId 187 memScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 188 memScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 189 memScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.memUops 190 memScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 191 memScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 192 memScheduler.io.fromMem.get.scommit := io.mem.sqDeq 193 memScheduler.io.fromMem.get.lcommit := io.mem.lqDeq 194 memScheduler.io.fromMem.get.sqCancelCnt := io.mem.sqCancelCnt 195 memScheduler.io.fromMem.get.lqCancelCnt := io.mem.lqCancelCnt 196 memScheduler.io.fromMem.get.stIssuePtr := io.mem.stIssuePtr 197 memScheduler.io.fromMem.get.memWaitUpdateReq.staIssue.zip(io.mem.stIn).foreach { case (sink, source) => 198 sink.valid := source.valid 199 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 200 sink.bits.uop.robIdx := source.bits.robIdx 201 } 202 memScheduler.io.fromDataPath.resp := dataPath.io.toMemIQ 203 memScheduler.io.fromMem.get.ldaFeedback := io.mem.ldaIqFeedback 204 memScheduler.io.fromMem.get.staFeedback := io.mem.staIqFeedback 205 memScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 206 memScheduler.io.fromDataPath.og0Cancel := og0CancelVec 207 memScheduler.io.fromDataPath.og1Cancel := og1CancelVec 208 209 vfScheduler.io.fromTop.hartId := io.fromTop.hartId 210 vfScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 211 vfScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 212 vfScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.vfUops 213 vfScheduler.io.intWriteBack := 0.U.asTypeOf(vfScheduler.io.intWriteBack) 214 vfScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 215 vfScheduler.io.fromDataPath.resp := dataPath.io.toVfIQ 216 vfScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 217 vfScheduler.io.fromDataPath.og0Cancel := og0CancelVec 218 vfScheduler.io.fromDataPath.og1Cancel := og1CancelVec 219 220 cancelNetwork.io.in.int <> intScheduler.io.toDataPath 221 cancelNetwork.io.in.vf <> vfScheduler.io.toDataPath 222 cancelNetwork.io.in.mem <> memScheduler.io.toDataPath 223 cancelNetwork.io.in.og0CancelVec := og0CancelVecFromDataPath 224 cancelNetwork.io.in.og1CancelVec := og1CancelVec 225 intScheduler.io.fromCancelNetwork <> cancelNetwork.io.out.int 226 vfScheduler.io.fromCancelNetwork <> cancelNetwork.io.out.vf 227 memScheduler.io.fromCancelNetwork <> cancelNetwork.io.out.mem 228 229 dataPath.io.flush := ctrlBlock.io.toDataPath.flush 230 dataPath.io.vconfigReadPort.addr := ctrlBlock.io.toDataPath.vtypeAddr 231 232 dataPath.io.fromIntIQ <> intScheduler.io.toDataPathAfterDelay 233 dataPath.io.fromVfIQ <> vfScheduler.io.toDataPathAfterDelay 234 dataPath.io.fromMemIQ <> memScheduler.io.toDataPathAfterDelay 235 236 println(s"[Backend] wbDataPath.io.toIntPreg: ${wbDataPath.io.toIntPreg.size}, dataPath.io.fromIntWb: ${dataPath.io.fromIntWb.size}") 237 println(s"[Backend] wbDataPath.io.toVfPreg: ${wbDataPath.io.toVfPreg.size}, dataPath.io.fromFpWb: ${dataPath.io.fromVfWb.size}") 238 dataPath.io.fromIntWb := wbDataPath.io.toIntPreg 239 dataPath.io.fromVfWb := wbDataPath.io.toVfPreg 240 dataPath.io.debugIntRat := ctrlBlock.io.debug_int_rat 241 dataPath.io.debugFpRat := ctrlBlock.io.debug_fp_rat 242 dataPath.io.debugVecRat := ctrlBlock.io.debug_vec_rat 243 dataPath.io.debugVconfigRat := ctrlBlock.io.debug_vconfig_rat 244 245 bypassNetwork.io.fromDataPath.int <> dataPath.io.toIntExu 246 bypassNetwork.io.fromDataPath.vf <> dataPath.io.toFpExu 247 bypassNetwork.io.fromDataPath.mem <> dataPath.io.toMemExu 248 bypassNetwork.io.fromExus.connectExuOutput(_.int)(intExuBlock.io.out) 249 bypassNetwork.io.fromExus.connectExuOutput(_.vf)(vfExuBlock.io.out) 250 bypassNetwork.io.fromExus.mem.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 251 sink.valid := source.valid 252 sink.bits.pdest := source.bits.uop.pdest 253 sink.bits.data := source.bits.data 254 } 255 256 intExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 257 for (i <- 0 until intExuBlock.io.in.length) { 258 for (j <- 0 until intExuBlock.io.in(i).length) { 259 NewPipelineConnect( 260 bypassNetwork.io.toExus.int(i)(j), intExuBlock.io.in(i)(j), intExuBlock.io.in(i)(j).fire, 261 Mux( 262 bypassNetwork.io.toExus.int(i)(j).fire, 263 bypassNetwork.io.toExus.int(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush), 264 intExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 265 ) 266 ) 267 } 268 } 269 270 private val csrio = intExuBlock.io.csrio.get 271 csrio.hartId := io.fromTop.hartId 272 csrio.perf.retiredInstr <> ctrlBlock.io.robio.csr.perfinfo.retiredInstr 273 csrio.perf.ctrlInfo <> ctrlBlock.io.perfInfo.ctrlInfo 274 csrio.perf.perfEventsCtrl <> ctrlBlock.getPerf 275 csrio.fpu.fflags := ctrlBlock.io.robio.csr.fflags 276 csrio.fpu.isIllegal := false.B // Todo: remove it 277 csrio.fpu.dirty_fs := ctrlBlock.io.robio.csr.dirty_fs 278 csrio.vpu <> 0.U.asTypeOf(csrio.vpu) // Todo 279 280 val debugVconfig = dataPath.io.debugVconfig.asTypeOf(new VConfig) 281 val debugVtype = VType.toVtypeStruct(debugVconfig.vtype).asUInt 282 val debugVl = debugVconfig.vl 283 csrio.vpu.set_vxsat := ctrlBlock.io.robio.csr.vxsat 284 csrio.vpu.set_vstart.valid := ctrlBlock.io.robio.csr.vcsrFlag 285 csrio.vpu.set_vstart.bits := 0.U 286 csrio.vpu.set_vtype.valid := ctrlBlock.io.robio.csr.vcsrFlag 287 csrio.vpu.set_vtype.bits := ZeroExt(debugVtype, XLEN) 288 csrio.vpu.set_vl.valid := ctrlBlock.io.robio.csr.vcsrFlag 289 csrio.vpu.set_vl.bits := ZeroExt(debugVl, XLEN) 290 csrio.exception := ctrlBlock.io.robio.exception 291 csrio.memExceptionVAddr := io.mem.exceptionVAddr 292 csrio.externalInterrupt := io.fromTop.externalInterrupt 293 csrio.distributedUpdate(0) := io.mem.csrDistributedUpdate 294 csrio.distributedUpdate(1) := io.frontendCsrDistributedUpdate 295 csrio.perf <> io.perf 296 private val fenceio = intExuBlock.io.fenceio.get 297 fenceio.disableSfence := csrio.disableSfence 298 io.fenceio <> fenceio 299 300 vfExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 301 for (i <- 0 until vfExuBlock.io.in.size) { 302 for (j <- 0 until vfExuBlock.io.in(i).size) { 303 NewPipelineConnect( 304 bypassNetwork.io.toExus.vf(i)(j), vfExuBlock.io.in(i)(j), vfExuBlock.io.in(i)(j).fire, 305 Mux( 306 bypassNetwork.io.toExus.vf(i)(j).fire, 307 bypassNetwork.io.toExus.vf(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush), 308 vfExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 309 ) 310 ) 311 312 vfExuBlock.io.in(i)(j).bits.vpu.foreach(_.vstart := csrio.vpu.vstart) 313 } 314 } 315 vfExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 316 317 wbDataPath.io.flush := ctrlBlock.io.redirect 318 wbDataPath.io.fromTop.hartId := io.fromTop.hartId 319 wbDataPath.io.fromIntExu <> intExuBlock.io.out 320 wbDataPath.io.fromVfExu <> vfExuBlock.io.out 321 wbDataPath.io.fromMemExu.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 322 sink.valid := source.valid 323 source.ready := sink.ready 324 sink.bits.data := source.bits.data 325 sink.bits.pdest := source.bits.uop.pdest 326 sink.bits.robIdx := source.bits.uop.robIdx 327 sink.bits.intWen.foreach(_ := source.bits.uop.rfWen) 328 sink.bits.fpWen.foreach(_ := source.bits.uop.fpWen) 329 sink.bits.vecWen.foreach(_ := source.bits.uop.vecWen) 330 sink.bits.exceptionVec.foreach(_ := source.bits.uop.exceptionVec) 331 sink.bits.flushPipe.foreach(_ := source.bits.uop.flushPipe) 332 sink.bits.replay.foreach(_ := source.bits.uop.replayInst) 333 sink.bits.debug := source.bits.debug 334 sink.bits.debugInfo := 0.U.asTypeOf(sink.bits.debugInfo) 335 sink.bits.lqIdx.foreach(_ := source.bits.uop.lqIdx) 336 sink.bits.sqIdx.foreach(_ := source.bits.uop.sqIdx) 337 sink.bits.ftqIdx.foreach(_ := source.bits.uop.ftqPtr) 338 sink.bits.ftqOffset.foreach(_ := source.bits.uop.ftqOffset) 339 } 340 341 // to mem 342 private val toMem = Wire(bypassNetwork.io.toExus.mem.cloneType) 343 for (i <- toMem.indices) { 344 for (j <- toMem(i).indices) { 345 NewPipelineConnect( 346 bypassNetwork.io.toExus.mem(i)(j), toMem(i)(j), toMem(i)(j).fire, 347 Mux( 348 bypassNetwork.io.toExus.mem(i)(j).fire, 349 bypassNetwork.io.toExus.mem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush), 350 toMem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 351 ) 352 ) 353 } 354 } 355 356 io.mem.redirect := ctrlBlock.io.redirect 357 io.mem.issueUops.zip(toMem.flatten).foreach { case (sink, source) => 358 sink.valid := source.valid 359 source.ready := sink.ready 360 sink.bits.iqIdx := source.bits.iqIdx 361 sink.bits.isFirstIssue := source.bits.isFirstIssue 362 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 363 sink.bits.src := 0.U.asTypeOf(sink.bits.src) 364 sink.bits.src.zip(source.bits.src).foreach { case (l, r) => l := r} 365 sink.bits.uop.fuType := source.bits.fuType 366 sink.bits.uop.fuOpType := source.bits.fuOpType 367 sink.bits.uop.imm := source.bits.imm 368 sink.bits.uop.robIdx := source.bits.robIdx 369 sink.bits.uop.pdest := source.bits.pdest 370 sink.bits.uop.rfWen := source.bits.rfWen.getOrElse(false.B) 371 sink.bits.uop.fpWen := source.bits.fpWen.getOrElse(false.B) 372 sink.bits.uop.vecWen := source.bits.vecWen.getOrElse(false.B) 373 sink.bits.uop.flushPipe := source.bits.flushPipe.getOrElse(false.B) 374 sink.bits.uop.pc := source.bits.pc.getOrElse(0.U) 375 sink.bits.uop.lqIdx := source.bits.lqIdx.getOrElse(0.U.asTypeOf(new LqPtr)) 376 sink.bits.uop.sqIdx := source.bits.sqIdx.getOrElse(0.U.asTypeOf(new SqPtr)) 377 sink.bits.uop.ftqPtr := source.bits.ftqIdx.getOrElse(0.U.asTypeOf(new FtqPtr)) 378 sink.bits.uop.ftqOffset := source.bits.ftqOffset.getOrElse(0.U) 379 } 380 io.mem.loadFastMatch := memScheduler.io.toMem.get.loadFastMatch.map(_.fastMatch) 381 io.mem.loadFastImm := memScheduler.io.toMem.get.loadFastMatch.map(_.fastImm) 382 io.mem.tlbCsr := csrio.tlb 383 io.mem.csrCtrl := csrio.customCtrl 384 io.mem.sfence := fenceio.sfence 385 io.mem.isStoreException := CommitType.lsInstIsStore(ctrlBlock.io.robio.exception.bits.commitType) 386 require(io.mem.loadPcRead.size == params.LduCnt) 387 io.mem.loadPcRead.zipWithIndex.foreach { case (loadPcRead, i) => 388 loadPcRead.data := ctrlBlock.io.memLdPcRead(i).data 389 ctrlBlock.io.memLdPcRead(i).ptr := loadPcRead.ptr 390 ctrlBlock.io.memLdPcRead(i).offset := loadPcRead.offset 391 } 392 393 ctrlBlock.io.robio.robHeadLsIssue := io.mem.issueUops.map(deq => deq.fire && deq.bits.uop.robIdx === ctrlBlock.io.robio.robDeqPtr).reduce(_ || _) 394 395 // mem io 396 io.mem.lsqEnqIO <> memScheduler.io.memIO.get.lsqEnqIO 397 io.mem.robLsqIO <> ctrlBlock.io.robio.lsq 398 io.mem.toSbuffer <> fenceio.sbuffer 399 400 io.frontendSfence := fenceio.sfence 401 io.frontendTlbCsr := csrio.tlb 402 io.frontendCsrCtrl := csrio.customCtrl 403 404 io.tlb <> csrio.tlb 405 406 io.csrCustomCtrl := csrio.customCtrl 407 408 dontTouch(memScheduler.io) 409 dontTouch(io.mem) 410 dontTouch(dataPath.io.toMemExu) 411 dontTouch(wbDataPath.io.fromMemExu) 412} 413 414class BackendMemIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 415 // params alias 416 private val LoadQueueSize = VirtualLoadQueueSize 417 // In/Out // Todo: split it into one-direction bundle 418 val lsqEnqIO = Flipped(new LsqEnqIO) 419 val robLsqIO = new RobLsqIO 420 val toSbuffer = new FenceToSbuffer 421 val ldaIqFeedback = Vec(params.LduCnt, Flipped(new MemRSFeedbackIO)) 422 val staIqFeedback = Vec(params.StaCnt, Flipped(new MemRSFeedbackIO)) 423 val loadPcRead = Vec(params.LduCnt, Flipped(new FtqRead(UInt(VAddrBits.W)))) 424 425 // Input 426 val writeBack = MixedVec(Seq.fill(params.LduCnt + params.StaCnt * 2)(Flipped(DecoupledIO(new MemExuOutput()))) ++ Seq.fill(params.VlduCnt)(Flipped(DecoupledIO(new MemExuOutput(true))))) 427 428 val s3_delayed_load_error = Input(Vec(LoadPipelineWidth, Bool())) 429 val stIn = Input(Vec(params.StaCnt, ValidIO(new DynInst()))) 430 val memoryViolation = Flipped(ValidIO(new Redirect)) 431 val exceptionVAddr = Input(UInt(VAddrBits.W)) 432 val sqDeq = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) 433 val lqDeq = Input(UInt(log2Up(CommitWidth + 1).W)) 434 435 val lqCancelCnt = Input(UInt(log2Up(VirtualLoadQueueSize + 1).W)) 436 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 437 438 val lqCanAccept = Input(Bool()) 439 val sqCanAccept = Input(Bool()) 440 441 val otherFastWakeup = Flipped(Vec(params.LduCnt + 2 * params.StaCnt, ValidIO(new DynInst))) 442 val stIssuePtr = Input(new SqPtr()) 443 444 val csrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 445 446 val debugLS = Flipped(Output(new DebugLSIO)) 447 448 val lsTopdownInfo = Vec(params.LduCnt, Flipped(Output(new LsTopdownInfo))) 449 // Output 450 val redirect = ValidIO(new Redirect) // rob flush MemBlock 451 val issueUops = MixedVec(Seq.fill(params.LduCnt + params.StaCnt + params.StdCnt)(DecoupledIO(new MemExuInput())) ++ Seq.fill(params.VlduCnt)(DecoupledIO(new MemExuInput(true)))) 452 val loadFastMatch = Vec(params.LduCnt, Output(UInt(params.LduCnt.W))) 453 val loadFastImm = Vec(params.LduCnt, Output(UInt(12.W))) // Imm_I 454 455 val tlbCsr = Output(new TlbCsrBundle) 456 val csrCtrl = Output(new CustomCSRCtrlIO) 457 val sfence = Output(new SfenceBundle) 458 val isStoreException = Output(Bool()) 459} 460 461class BackendIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 462 val fromTop = new Bundle { 463 val hartId = Input(UInt(8.W)) 464 val externalInterrupt = new ExternalInterruptIO 465 } 466 467 val toTop = new Bundle { 468 val cpuHalted = Output(Bool()) 469 } 470 471 val fenceio = new FenceIO 472 // Todo: merge these bundles into BackendFrontendIO 473 val frontend = Flipped(new FrontendToCtrlIO) 474 val frontendSfence = Output(new SfenceBundle) 475 val frontendCsrCtrl = Output(new CustomCSRCtrlIO) 476 val frontendTlbCsr = Output(new TlbCsrBundle) 477 // distributed csr write 478 val frontendCsrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 479 480 val mem = new BackendMemIO 481 482 val perf = Input(new PerfCounterIO) 483 484 val tlb = Output(new TlbCsrBundle) 485 486 val csrCustomCtrl = Output(new CustomCSRCtrlIO) 487} 488