1package xiangshan.backend 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import utility.ZeroExt 8import xiangshan._ 9import xiangshan.backend.Bundles.{DynInst, IssueQueueIQWakeUpBundle, LoadShouldCancel, MemExuInput, MemExuOutput} 10import xiangshan.backend.ctrlblock.{DebugLSIO, LsTopdownInfo} 11import xiangshan.backend.datapath.DataConfig.{IntData, VecData} 12import xiangshan.backend.datapath.RdConfig.{IntRD, VfRD} 13import xiangshan.backend.datapath.WbConfig._ 14import xiangshan.backend.datapath._ 15import xiangshan.backend.dispatch.CoreDispatchTopDownIO 16import xiangshan.backend.exu.ExuBlock 17import xiangshan.backend.fu.vector.Bundles.{VConfig, VType} 18import xiangshan.backend.fu.{FenceIO, FenceToSbuffer, FuConfig, PerfCounterIO} 19import xiangshan.backend.issue.{CancelNetwork, Scheduler, SchedulerImpBase} 20import xiangshan.backend.rob.{RobCoreTopDownIO, RobDebugRollingIO, RobLsqIO} 21import xiangshan.frontend.{FtqPtr, FtqRead} 22import xiangshan.mem.{LqPtr, LsqEnqIO, SqPtr} 23 24class Backend(val params: BackendParams)(implicit p: Parameters) extends LazyModule 25 with HasXSParameter { 26 27 /* Only update the idx in mem-scheduler here 28 * Idx in other schedulers can be updated the same way if needed 29 * 30 * Also note that we filter out the 'stData issue-queues' when counting 31 */ 32 for ((ibp, idx) <- params.memSchdParams.get.issueBlockParams.filter(iq => iq.StdCnt == 0).zipWithIndex) { 33 ibp.updateIdx(idx) 34 } 35 36 println(params.iqWakeUpParams) 37 38 for ((schdCfg, i) <- params.allSchdParams.zipWithIndex) { 39 schdCfg.bindBackendParam(params) 40 } 41 42 for ((iqCfg, i) <- params.allIssueParams.zipWithIndex) { 43 iqCfg.bindBackendParam(params) 44 } 45 46 for ((exuCfg, i) <- params.allExuParams.zipWithIndex) { 47 exuCfg.updateIQWakeUpConfigs(params.iqWakeUpParams) 48 exuCfg.updateExuIdx(i) 49 exuCfg.bindBackendParam(params) 50 } 51 52 println("[Backend] ExuConfigs:") 53 for (exuCfg <- params.allExuParams) { 54 val fuConfigs = exuCfg.fuConfigs 55 val wbPortConfigs = exuCfg.wbPortConfigs 56 val immType = exuCfg.immType 57 58 println("[Backend] " + 59 s"${exuCfg.name}: " + 60 s"${fuConfigs.map(_.name).mkString("fu(s): {", ",", "}")}, " + 61 s"${wbPortConfigs.mkString("wb: {", ",", "}")}, " + 62 s"${immType.map(SelImm.mkString(_)).mkString("imm: {", ",", "}")}, " + 63 s"latMax(${exuCfg.latencyValMax}), ${exuCfg.fuLatancySet.mkString("lat: {", ",", "}")}, " 64 ) 65 require( 66 wbPortConfigs.collectFirst { case x: IntWB => x }.nonEmpty == 67 fuConfigs.map(_.writeIntRf).reduce(_ || _), 68 "int wb port has no priority" 69 ) 70 require( 71 wbPortConfigs.collectFirst { case x: VfWB => x }.nonEmpty == 72 fuConfigs.map(x => x.writeFpRf || x.writeVecRf).reduce(_ || _), 73 "vec wb port has no priority" 74 ) 75 } 76 77 println(s"[Backend] all fu configs") 78 for (cfg <- FuConfig.allConfigs) { 79 println(s"[Backend] $cfg") 80 } 81 82 println(s"[Backend] Int RdConfigs: ExuName(Priority)") 83 for ((port, seq) <- params.getRdPortParams(IntData())) { 84 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 85 } 86 87 println(s"[Backend] Int WbConfigs: ExuName(Priority)") 88 for ((port, seq) <- params.getWbPortParams(IntData())) { 89 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 90 } 91 92 println(s"[Backend] Vf RdConfigs: ExuName(Priority)") 93 for ((port, seq) <- params.getRdPortParams(VecData())) { 94 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 95 } 96 97 println(s"[Backend] Vf WbConfigs: ExuName(Priority)") 98 for ((port, seq) <- params.getWbPortParams(VecData())) { 99 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 100 } 101 102 val ctrlBlock = LazyModule(new CtrlBlock(params)) 103 val pcTargetMem = LazyModule(new PcTargetMem(params)) 104 val intScheduler = params.intSchdParams.map(x => LazyModule(new Scheduler(x))) 105 val vfScheduler = params.vfSchdParams.map(x => LazyModule(new Scheduler(x))) 106 val memScheduler = params.memSchdParams.map(x => LazyModule(new Scheduler(x))) 107 val cancelNetwork = LazyModule(new CancelNetwork(params)) 108 val dataPath = LazyModule(new DataPath(params)) 109 val intExuBlock = params.intSchdParams.map(x => LazyModule(new ExuBlock(x))) 110 val vfExuBlock = params.vfSchdParams.map(x => LazyModule(new ExuBlock(x))) 111 val wbFuBusyTable = LazyModule(new WbFuBusyTable(params)) 112 113 lazy val module = new BackendImp(this) 114} 115 116class BackendImp(override val wrapper: Backend)(implicit p: Parameters) extends LazyModuleImp(wrapper) 117 with HasXSParameter { 118 implicit private val params = wrapper.params 119 120 val io = IO(new BackendIO()(p, wrapper.params)) 121 122 private val ctrlBlock = wrapper.ctrlBlock.module 123 private val pcTargetMem = wrapper.pcTargetMem.module 124 private val intScheduler: SchedulerImpBase = wrapper.intScheduler.get.module 125 private val vfScheduler = wrapper.vfScheduler.get.module 126 private val memScheduler = wrapper.memScheduler.get.module 127 private val cancelNetwork = wrapper.cancelNetwork.module 128 private val dataPath = wrapper.dataPath.module 129 private val intExuBlock = wrapper.intExuBlock.get.module 130 private val vfExuBlock = wrapper.vfExuBlock.get.module 131 private val bypassNetwork = Module(new BypassNetwork) 132 private val wbDataPath = Module(new WbDataPath(params)) 133 private val wbFuBusyTable = wrapper.wbFuBusyTable.module 134 135 private val iqWakeUpMappedBundle: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = ( 136 intScheduler.io.toSchedulers.wakeupVec ++ 137 vfScheduler.io.toSchedulers.wakeupVec ++ 138 memScheduler.io.toSchedulers.wakeupVec 139 ).map(x => (x.bits.exuIdx, x)).toMap 140 141 println(s"[Backend] iq wake up keys: ${iqWakeUpMappedBundle.keys}") 142 143 wbFuBusyTable.io.in.intSchdBusyTable := intScheduler.io.wbFuBusyTable 144 wbFuBusyTable.io.in.vfSchdBusyTable := vfScheduler.io.wbFuBusyTable 145 wbFuBusyTable.io.in.memSchdBusyTable := memScheduler.io.wbFuBusyTable 146 intScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.intRespRead 147 vfScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.vfRespRead 148 memScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.memRespRead 149 dataPath.io.wbConfictRead := wbFuBusyTable.io.out.wbConflictRead 150 151 wbDataPath.io.fromIntExu.flatten.filter(x => x.bits.params.writeIntRf) 152 153 private val vconfig = dataPath.io.vconfigReadPort.data 154 private val og1CancelVec: Vec[Bool] = dataPath.io.og1CancelVec 155 private val og0CancelVecFromDataPath: Vec[Bool] = dataPath.io.og0CancelVec 156 private val og0CancelVecFromCancelNet: Vec[Bool] = cancelNetwork.io.out.og0CancelVec 157 private val og0CancelVecFromFinalIssue: Vec[Bool] = Wire(chiselTypeOf(dataPath.io.og0CancelVec)) 158 private val og0CancelVec: Seq[Bool] = og0CancelVecFromDataPath.zip(og0CancelVecFromCancelNet).zip(og0CancelVecFromFinalIssue).map(x => x._1._1 | x._1._2 | x._2) 159 private val cancelToBusyTable = dataPath.io.cancelToBusyTable 160 161 ctrlBlock.io.fromTop.hartId := io.fromTop.hartId 162 ctrlBlock.io.frontend <> io.frontend 163 ctrlBlock.io.fromWB.wbData <> wbDataPath.io.toCtrlBlock.writeback 164 ctrlBlock.io.fromMem.stIn <> io.mem.stIn 165 ctrlBlock.io.fromMem.violation <> io.mem.memoryViolation 166 ctrlBlock.io.lqCanAccept := io.mem.lqCanAccept 167 ctrlBlock.io.sqCanAccept := io.mem.sqCanAccept 168 ctrlBlock.io.csrCtrl <> intExuBlock.io.csrio.get.customCtrl 169 ctrlBlock.io.robio.csr.intrBitSet := intExuBlock.io.csrio.get.interrupt 170 ctrlBlock.io.robio.csr.trapTarget := intExuBlock.io.csrio.get.trapTarget 171 ctrlBlock.io.robio.csr.isXRet := intExuBlock.io.csrio.get.isXRet 172 ctrlBlock.io.robio.csr.wfiEvent := intExuBlock.io.csrio.get.wfi_event 173 ctrlBlock.io.robio.lsq <> io.mem.robLsqIO 174 ctrlBlock.io.robio.lsTopdownInfo <> io.mem.lsTopdownInfo 175 ctrlBlock.io.robio.debug_ls <> io.mem.debugLS 176 ctrlBlock.io.fromDataPath.vtype := vconfig(7, 0).asTypeOf(new VType) 177 ctrlBlock.perfinfo := DontCare // TODO: Implement backend hpm 178 179 intScheduler.io.fromTop.hartId := io.fromTop.hartId 180 intScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 181 intScheduler.io.fromCtrlBlock.pcVec := ctrlBlock.io.toIssueBlock.pcVec 182 intScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 183 intScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.intUops 184 intScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 185 intScheduler.io.vfWriteBack := 0.U.asTypeOf(intScheduler.io.vfWriteBack) 186 intScheduler.io.fromDataPath.resp := dataPath.io.toIntIQ 187 intScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 188 intScheduler.io.fromDataPath.og0Cancel := og0CancelVec 189 intScheduler.io.fromDataPath.og1Cancel := og1CancelVec 190 intScheduler.io.ldCancel := io.mem.ldCancel 191 intScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 192 193 memScheduler.io.fromTop.hartId := io.fromTop.hartId 194 memScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 195 memScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 196 memScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.memUops 197 memScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 198 memScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 199 memScheduler.io.fromMem.get.scommit := io.mem.sqDeq 200 memScheduler.io.fromMem.get.lcommit := io.mem.lqDeq 201 memScheduler.io.fromMem.get.sqCancelCnt := io.mem.sqCancelCnt 202 memScheduler.io.fromMem.get.lqCancelCnt := io.mem.lqCancelCnt 203 memScheduler.io.fromMem.get.stIssuePtr := io.mem.stIssuePtr 204 memScheduler.io.fromMem.get.memWaitUpdateReq.robIdx.zip(io.mem.stIn).foreach { case (sink, source) => 205 sink.valid := source.valid 206 sink.bits := source.bits.robIdx 207 } 208 memScheduler.io.fromMem.get.memWaitUpdateReq.sqIdx := DontCare // TODO 209 memScheduler.io.fromDataPath.resp := dataPath.io.toMemIQ 210 memScheduler.io.fromMem.get.ldaFeedback := io.mem.ldaIqFeedback 211 memScheduler.io.fromMem.get.staFeedback := io.mem.staIqFeedback 212 memScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 213 memScheduler.io.fromDataPath.og0Cancel := og0CancelVec 214 memScheduler.io.fromDataPath.og1Cancel := og1CancelVec 215 memScheduler.io.ldCancel := io.mem.ldCancel 216 memScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 217 218 vfScheduler.io.fromTop.hartId := io.fromTop.hartId 219 vfScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 220 vfScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 221 vfScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.vfUops 222 vfScheduler.io.intWriteBack := 0.U.asTypeOf(vfScheduler.io.intWriteBack) 223 vfScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 224 vfScheduler.io.fromDataPath.resp := dataPath.io.toVfIQ 225 vfScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 226 vfScheduler.io.fromDataPath.og0Cancel := og0CancelVec 227 vfScheduler.io.fromDataPath.og1Cancel := og1CancelVec 228 vfScheduler.io.ldCancel := io.mem.ldCancel 229 vfScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 230 231 cancelNetwork.io.in.int <> intScheduler.io.toDataPath 232 cancelNetwork.io.in.vf <> vfScheduler.io.toDataPath 233 cancelNetwork.io.in.mem <> memScheduler.io.toDataPath 234 cancelNetwork.io.in.og0CancelVec := og0CancelVecFromDataPath.zip(og0CancelVecFromFinalIssue).map(x => x._1 || x._2) 235 cancelNetwork.io.in.og1CancelVec := og1CancelVec 236 intScheduler.io.fromCancelNetwork <> cancelNetwork.io.out.int 237 vfScheduler.io.fromCancelNetwork <> cancelNetwork.io.out.vf 238 memScheduler.io.fromCancelNetwork <> cancelNetwork.io.out.mem 239 240 dataPath.io.hartId := io.fromTop.hartId 241 dataPath.io.flush := ctrlBlock.io.toDataPath.flush 242 dataPath.io.vconfigReadPort.addr := ctrlBlock.io.toDataPath.vtypeAddr 243 244 dataPath.io.fromIntIQ <> intScheduler.io.toDataPathAfterDelay 245 dataPath.io.fromVfIQ <> vfScheduler.io.toDataPathAfterDelay 246 dataPath.io.fromMemIQ <> memScheduler.io.toDataPathAfterDelay 247 248 dataPath.io.ldCancel := io.mem.ldCancel 249 250 println(s"[Backend] wbDataPath.io.toIntPreg: ${wbDataPath.io.toIntPreg.size}, dataPath.io.fromIntWb: ${dataPath.io.fromIntWb.size}") 251 println(s"[Backend] wbDataPath.io.toVfPreg: ${wbDataPath.io.toVfPreg.size}, dataPath.io.fromFpWb: ${dataPath.io.fromVfWb.size}") 252 dataPath.io.fromIntWb := wbDataPath.io.toIntPreg 253 dataPath.io.fromVfWb := wbDataPath.io.toVfPreg 254 dataPath.io.debugIntRat .foreach(_ := ctrlBlock.io.debug_int_rat.get) 255 dataPath.io.debugFpRat .foreach(_ := ctrlBlock.io.debug_fp_rat.get) 256 dataPath.io.debugVecRat .foreach(_ := ctrlBlock.io.debug_vec_rat.get) 257 dataPath.io.debugVconfigRat.foreach(_ := ctrlBlock.io.debug_vconfig_rat.get) 258 259 bypassNetwork.io.fromDataPath.int <> dataPath.io.toIntExu 260 bypassNetwork.io.fromDataPath.vf <> dataPath.io.toFpExu 261 bypassNetwork.io.fromDataPath.mem <> dataPath.io.toMemExu 262 bypassNetwork.io.fromExus.connectExuOutput(_.int)(intExuBlock.io.out) 263 bypassNetwork.io.fromExus.connectExuOutput(_.vf)(vfExuBlock.io.out) 264 bypassNetwork.io.fromExus.mem.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 265 sink.valid := source.valid 266 sink.bits.pdest := source.bits.uop.pdest 267 sink.bits.data := source.bits.data 268 } 269 270 271 intExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 272 for (i <- 0 until intExuBlock.io.in.length) { 273 for (j <- 0 until intExuBlock.io.in(i).length) { 274 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.int(i)(j).bits.loadDependency, io.mem.ldCancel) 275 NewPipelineConnect( 276 bypassNetwork.io.toExus.int(i)(j), intExuBlock.io.in(i)(j), intExuBlock.io.in(i)(j).fire, 277 Mux( 278 bypassNetwork.io.toExus.int(i)(j).fire, 279 bypassNetwork.io.toExus.int(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 280 intExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 281 ) 282 ) 283 } 284 } 285 286 pcTargetMem.io.fromFrontendFtq := io.frontend.fromFtq 287 pcTargetMem.io.fromDataPathFtq := bypassNetwork.io.toExus.int.flatten.filter(_.bits.params.hasPredecode).map(_.bits.ftqIdx.get).toSeq 288 intExuBlock.io.in.flatten.filter(_.bits.params.hasPredecode).map(_.bits.predictInfo.get.target).zipWithIndex.foreach { 289 case (sink, i) => 290 sink := pcTargetMem.io.toExus(i) 291 } 292 293 private val csrio = intExuBlock.io.csrio.get 294 csrio.hartId := io.fromTop.hartId 295 csrio.fpu.fflags := ctrlBlock.io.robio.csr.fflags 296 csrio.fpu.isIllegal := false.B // Todo: remove it 297 csrio.fpu.dirty_fs := ctrlBlock.io.robio.csr.dirty_fs 298 csrio.vpu <> 0.U.asTypeOf(csrio.vpu) // Todo 299 300 val debugVconfig = dataPath.io.debugVconfig.get.asTypeOf(new VConfig) 301 val debugVtype = VType.toVtypeStruct(debugVconfig.vtype).asUInt 302 val debugVl = debugVconfig.vl 303 csrio.vpu.set_vxsat := ctrlBlock.io.robio.csr.vxsat 304 csrio.vpu.set_vstart.valid := ctrlBlock.io.robio.csr.vcsrFlag 305 csrio.vpu.set_vstart.bits := 0.U 306 csrio.vpu.set_vtype.valid := ctrlBlock.io.robio.csr.vcsrFlag 307 //Todo here need change design 308 csrio.vpu.set_vtype.bits := ZeroExt(debugVtype, XLEN) 309 csrio.vpu.set_vl.valid := ctrlBlock.io.robio.csr.vcsrFlag 310 csrio.vpu.set_vl.bits := ZeroExt(debugVl, XLEN) 311 csrio.exception := ctrlBlock.io.robio.exception 312 csrio.memExceptionVAddr := io.mem.exceptionVAddr 313 csrio.externalInterrupt := io.fromTop.externalInterrupt 314 csrio.distributedUpdate(0) := io.mem.csrDistributedUpdate 315 csrio.distributedUpdate(1) := io.frontendCsrDistributedUpdate 316 csrio.perf <> io.perf 317 csrio.perf.retiredInstr <> ctrlBlock.io.robio.csr.perfinfo.retiredInstr 318 csrio.perf.ctrlInfo <> ctrlBlock.io.perfInfo.ctrlInfo 319 csrio.perf.perfEventsCtrl <> ctrlBlock.getPerf 320 private val fenceio = intExuBlock.io.fenceio.get 321 io.fenceio <> fenceio 322 fenceio.disableSfence := csrio.disableSfence 323 324 vfExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 325 for (i <- 0 until vfExuBlock.io.in.size) { 326 for (j <- 0 until vfExuBlock.io.in(i).size) { 327 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.vf(i)(j).bits.loadDependency, io.mem.ldCancel) 328 NewPipelineConnect( 329 bypassNetwork.io.toExus.vf(i)(j), vfExuBlock.io.in(i)(j), vfExuBlock.io.in(i)(j).fire, 330 Mux( 331 bypassNetwork.io.toExus.vf(i)(j).fire, 332 bypassNetwork.io.toExus.vf(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 333 vfExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 334 ) 335 ) 336 337 vfExuBlock.io.in(i)(j).bits.vpu.foreach(_.vstart := csrio.vpu.vstart) 338 } 339 } 340 341 intExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 342 vfExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 343 344 wbDataPath.io.flush := ctrlBlock.io.redirect 345 wbDataPath.io.fromTop.hartId := io.fromTop.hartId 346 wbDataPath.io.fromIntExu <> intExuBlock.io.out 347 wbDataPath.io.fromVfExu <> vfExuBlock.io.out 348 wbDataPath.io.fromMemExu.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 349 sink.valid := source.valid 350 source.ready := sink.ready 351 sink.bits.data := source.bits.data 352 sink.bits.pdest := source.bits.uop.pdest 353 sink.bits.robIdx := source.bits.uop.robIdx 354 sink.bits.intWen.foreach(_ := source.bits.uop.rfWen) 355 sink.bits.fpWen.foreach(_ := source.bits.uop.fpWen) 356 sink.bits.vecWen.foreach(_ := source.bits.uop.vecWen) 357 sink.bits.exceptionVec.foreach(_ := source.bits.uop.exceptionVec) 358 sink.bits.flushPipe.foreach(_ := source.bits.uop.flushPipe) 359 sink.bits.replay.foreach(_ := source.bits.uop.replayInst) 360 sink.bits.debug := source.bits.debug 361 sink.bits.debugInfo := source.bits.uop.debugInfo 362 sink.bits.lqIdx.foreach(_ := source.bits.uop.lqIdx) 363 sink.bits.sqIdx.foreach(_ := source.bits.uop.sqIdx) 364 } 365 366 // to mem 367 private val memIssueParams = params.memSchdParams.get.issueBlockParams 368 private val memExuBlocksHasLDU = memIssueParams.map(_.exuBlockParams.map(_.fuConfigs.contains(FuConfig.LduCfg))) 369 private val toMem = Wire(bypassNetwork.io.toExus.mem.cloneType) 370 for (i <- toMem.indices) { 371 for (j <- toMem(i).indices) { 372 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.mem(i)(j).bits.loadDependency, io.mem.ldCancel) 373 val issueTimeout = 374 if (memExuBlocksHasLDU(i)(j)) 375 Counter(0 until 16, toMem(i)(j).valid && !toMem(i)(j).fire, bypassNetwork.io.toExus.mem(i)(j).fire)._2 376 else 377 false.B 378 379 if (memScheduler.io.loadFinalIssueResp(i).nonEmpty) { 380 memScheduler.io.loadFinalIssueResp(i)(j).valid := issueTimeout 381 memScheduler.io.loadFinalIssueResp(i)(j).bits.dataInvalidSqIdx := DontCare 382 memScheduler.io.loadFinalIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType 383 memScheduler.io.loadFinalIssueResp(i)(j).bits.respType := RSFeedbackType.fuBusy 384 memScheduler.io.loadFinalIssueResp(i)(j).bits.rfWen := toMem(i)(j).bits.rfWen.getOrElse(false.B) 385 memScheduler.io.loadFinalIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx 386 } 387 388 NewPipelineConnect( 389 bypassNetwork.io.toExus.mem(i)(j), toMem(i)(j), toMem(i)(j).fire, 390 Mux( 391 bypassNetwork.io.toExus.mem(i)(j).fire, 392 bypassNetwork.io.toExus.mem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 393 toMem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || issueTimeout 394 ) 395 ) 396 } 397 } 398 399 io.mem.redirect := ctrlBlock.io.redirect 400 io.mem.issueUops.zip(toMem.flatten).foreach { case (sink, source) => 401 sink.valid := source.valid 402 source.ready := sink.ready 403 sink.bits.iqIdx := source.bits.iqIdx 404 sink.bits.isFirstIssue := source.bits.isFirstIssue 405 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 406 sink.bits.src := 0.U.asTypeOf(sink.bits.src) 407 sink.bits.src.zip(source.bits.src).foreach { case (l, r) => l := r} 408 sink.bits.deqPortIdx := source.bits.deqPortIdx.getOrElse(0.U) 409 sink.bits.uop.fuType := source.bits.fuType 410 sink.bits.uop.fuOpType := source.bits.fuOpType 411 sink.bits.uop.imm := source.bits.imm 412 sink.bits.uop.robIdx := source.bits.robIdx 413 sink.bits.uop.pdest := source.bits.pdest 414 sink.bits.uop.rfWen := source.bits.rfWen.getOrElse(false.B) 415 sink.bits.uop.fpWen := source.bits.fpWen.getOrElse(false.B) 416 sink.bits.uop.vecWen := source.bits.vecWen.getOrElse(false.B) 417 sink.bits.uop.flushPipe := source.bits.flushPipe.getOrElse(false.B) 418 sink.bits.uop.pc := source.bits.pc.getOrElse(0.U) 419 sink.bits.uop.lqIdx := source.bits.lqIdx.getOrElse(0.U.asTypeOf(new LqPtr)) 420 sink.bits.uop.sqIdx := source.bits.sqIdx.getOrElse(0.U.asTypeOf(new SqPtr)) 421 sink.bits.uop.ftqPtr := source.bits.ftqIdx.getOrElse(0.U.asTypeOf(new FtqPtr)) 422 sink.bits.uop.ftqOffset := source.bits.ftqOffset.getOrElse(0.U) 423 sink.bits.uop.debugInfo := source.bits.perfDebugInfo 424 } 425 io.mem.loadFastMatch := memScheduler.io.toMem.get.loadFastMatch.map(_.fastMatch) 426 io.mem.loadFastImm := memScheduler.io.toMem.get.loadFastMatch.map(_.fastImm) 427 io.mem.tlbCsr := csrio.tlb 428 io.mem.csrCtrl := csrio.customCtrl 429 io.mem.sfence := fenceio.sfence 430 io.mem.isStoreException := CommitType.lsInstIsStore(ctrlBlock.io.robio.exception.bits.commitType) 431 require(io.mem.loadPcRead.size == params.LduCnt) 432 io.mem.loadPcRead.zipWithIndex.foreach { case (loadPcRead, i) => 433 loadPcRead := ctrlBlock.io.memLdPcRead(i).data 434 ctrlBlock.io.memLdPcRead(i).ptr := io.mem.issueUops(i).bits.uop.ftqPtr 435 ctrlBlock.io.memLdPcRead(i).offset := io.mem.issueUops(i).bits.uop.ftqOffset 436 require(toMem.head(i).bits.ftqIdx.isDefined && toMem.head(i).bits.ftqOffset.isDefined) 437 } 438 439 ctrlBlock.io.robio.robHeadLsIssue := io.mem.issueUops.map(deq => deq.fire && deq.bits.uop.robIdx === ctrlBlock.io.robio.robDeqPtr).reduce(_ || _) 440 441 // mem io 442 io.mem.lsqEnqIO <> memScheduler.io.memIO.get.lsqEnqIO 443 io.mem.robLsqIO <> ctrlBlock.io.robio.lsq 444 445 private val intFinalIssueBlock = intExuBlock.io.in.flatten.map(_ => false.B) 446 private val vfFinalIssueBlock = vfExuBlock.io.in.flatten.map(_ => false.B) 447 private val memFinalIssueBlock = io.mem.issueUops zip memExuBlocksHasLDU.flatten map { 448 case (out, isLdu) => 449 if (isLdu) RegNext(out.valid && !out.ready, false.B) 450 else false.B 451 } 452 og0CancelVecFromFinalIssue := (intFinalIssueBlock ++ vfFinalIssueBlock ++ memFinalIssueBlock).toSeq 453 454 IndexedSeq 455 io.frontendSfence := fenceio.sfence 456 io.frontendTlbCsr := csrio.tlb 457 io.frontendCsrCtrl := csrio.customCtrl 458 459 io.tlb <> csrio.tlb 460 461 io.csrCustomCtrl := csrio.customCtrl 462 463 io.toTop.cpuHalted := false.B // TODO: implement cpu halt 464 465 dontTouch(memScheduler.io) 466 dontTouch(io.mem) 467 dontTouch(dataPath.io.toMemExu) 468 dontTouch(wbDataPath.io.fromMemExu) 469} 470 471class BackendMemIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 472 // params alias 473 private val LoadQueueSize = VirtualLoadQueueSize 474 // In/Out // Todo: split it into one-direction bundle 475 val lsqEnqIO = Flipped(new LsqEnqIO) 476 val robLsqIO = new RobLsqIO 477 val ldaIqFeedback = Vec(params.LduCnt, Flipped(new MemRSFeedbackIO)) 478 val staIqFeedback = Vec(params.StaCnt, Flipped(new MemRSFeedbackIO)) 479 val ldCancel = Vec(params.LduCnt, Flipped(new LoadCancelIO)) 480 val loadPcRead = Vec(params.LduCnt, Output(UInt(VAddrBits.W))) 481 482 // Input 483 val writeBack = MixedVec(Seq.fill(params.LduCnt + params.StaCnt * 2)(Flipped(DecoupledIO(new MemExuOutput()))) ++ Seq.fill(params.VlduCnt)(Flipped(DecoupledIO(new MemExuOutput(true))))) 484 485 val s3_delayed_load_error = Input(Vec(LoadPipelineWidth, Bool())) 486 val stIn = Input(Vec(params.StaCnt, ValidIO(new DynInst()))) 487 val memoryViolation = Flipped(ValidIO(new Redirect)) 488 val exceptionVAddr = Input(UInt(VAddrBits.W)) 489 val sqDeq = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) 490 val lqDeq = Input(UInt(log2Up(CommitWidth + 1).W)) 491 492 val lqCancelCnt = Input(UInt(log2Up(VirtualLoadQueueSize + 1).W)) 493 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 494 495 val lqCanAccept = Input(Bool()) 496 val sqCanAccept = Input(Bool()) 497 498 val otherFastWakeup = Flipped(Vec(params.LduCnt + 2 * params.StaCnt, ValidIO(new DynInst))) 499 val stIssuePtr = Input(new SqPtr()) 500 501 val csrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 502 503 val debugLS = Flipped(Output(new DebugLSIO)) 504 505 val lsTopdownInfo = Vec(params.LduCnt, Flipped(Output(new LsTopdownInfo))) 506 // Output 507 val redirect = ValidIO(new Redirect) // rob flush MemBlock 508 val issueUops = MixedVec(Seq.fill(params.LduCnt + params.StaCnt + params.StdCnt)(DecoupledIO(new MemExuInput())) ++ Seq.fill(params.VlduCnt)(DecoupledIO(new MemExuInput(true)))) 509 val loadFastMatch = Vec(params.LduCnt, Output(UInt(params.LduCnt.W))) 510 val loadFastImm = Vec(params.LduCnt, Output(UInt(12.W))) // Imm_I 511 512 val tlbCsr = Output(new TlbCsrBundle) 513 val csrCtrl = Output(new CustomCSRCtrlIO) 514 val sfence = Output(new SfenceBundle) 515 val isStoreException = Output(Bool()) 516} 517 518class BackendIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 519 val fromTop = new Bundle { 520 val hartId = Input(UInt(8.W)) 521 val externalInterrupt = new ExternalInterruptIO 522 } 523 524 val toTop = new Bundle { 525 val cpuHalted = Output(Bool()) 526 } 527 528 val fenceio = new FenceIO 529 // Todo: merge these bundles into BackendFrontendIO 530 val frontend = Flipped(new FrontendToCtrlIO) 531 val frontendSfence = Output(new SfenceBundle) 532 val frontendCsrCtrl = Output(new CustomCSRCtrlIO) 533 val frontendTlbCsr = Output(new TlbCsrBundle) 534 // distributed csr write 535 val frontendCsrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 536 537 val mem = new BackendMemIO 538 539 val perf = Input(new PerfCounterIO) 540 541 val tlb = Output(new TlbCsrBundle) 542 543 val csrCustomCtrl = Output(new CustomCSRCtrlIO) 544 545 val debugTopDown = new Bundle { 546 val fromRob = new RobCoreTopDownIO 547 val fromCore = new CoreDispatchTopDownIO 548 } 549 val debugRolling = new RobDebugRollingIO 550} 551