1package xiangshan.backend 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utils.OptionWrapper 7import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 8import utility.{PipelineConnect, ZeroExt} 9import xiangshan._ 10import xiangshan.backend.Bundles.{DynInst, MemExuInput, MemExuOutput} 11import xiangshan.backend.ctrlblock.CtrlBlock 12import xiangshan.backend.datapath.WbConfig._ 13import xiangshan.backend.datapath.{DataPath, NewPipelineConnect, WbDataPath, WbFuBusyTable} 14import xiangshan.backend.exu.ExuBlock 15import xiangshan.backend.fu.vector.Bundles.{VConfig, VType} 16import xiangshan.backend.fu.{FenceIO, FenceToSbuffer, FuConfig, PerfCounterIO} 17import xiangshan.backend.issue.{Scheduler, IntScheduler, MemScheduler, VfScheduler} 18import xiangshan.backend.rob.RobLsqIO 19import xiangshan.frontend.{FtqPtr, FtqRead} 20import xiangshan.mem.{LqPtr, LsqEnqIO, SqPtr} 21 22class Backend(val params: BackendParams)(implicit p: Parameters) extends LazyModule 23 with HasXSParameter { 24 25 println("[Backend] ExuConfigs:") 26 for (exuCfg <- params.allExuParams) { 27 val fuConfigs = exuCfg.fuConfigs 28 val wbPortConfigs = exuCfg.wbPortConfigs 29 val immType = exuCfg.immType 30 31 println("[Backend] " + 32 s"${exuCfg.name}: " + 33 s"${ fuConfigs.map(_.name).mkString("fu(s): {", ",", "}") }, " + 34 s"${ wbPortConfigs.mkString("wb: {", ",", "}") }, " + 35 s"${ immType.map(SelImm.mkString(_)).mkString("imm: {", "," , "}") }, " + 36 s"latMax(${exuCfg.latencyValMax}), ${exuCfg.fuLatancySet.mkString("lat: {",",","}")}, ") 37 require(wbPortConfigs.collectFirst { case x: IntWB => x }.nonEmpty == 38 fuConfigs.map(_.writeIntRf).reduce(_ || _), 39 "int wb port has no priority" ) 40 require(wbPortConfigs.collectFirst { case x: VfWB => x }.nonEmpty == 41 fuConfigs.map(x => x.writeFpRf || x.writeVecRf).reduce(_ || _), 42 "vec wb port has no priority" ) 43 } 44 45 for (cfg <- FuConfig.allConfigs) { 46 println(s"[Backend] $cfg") 47 } 48 49 val ctrlBlock = LazyModule(new CtrlBlock(params)) 50 val intScheduler = params.intSchdParams.map(x => LazyModule(new Scheduler(x))) 51 val vfScheduler = params.vfSchdParams.map(x => LazyModule(new Scheduler(x))) 52 val memScheduler = params.memSchdParams.map(x => LazyModule(new Scheduler(x))) 53 val dataPath = LazyModule(new DataPath(params)) 54 val intExuBlock = params.intSchdParams.map(x => LazyModule(new ExuBlock(x))) 55 val vfExuBlock = params.vfSchdParams.map(x => LazyModule(new ExuBlock(x))) 56 val wbFuBusyTable = LazyModule(new WbFuBusyTable(params)) 57 58 lazy val module = new BackendImp(this) 59} 60 61class BackendImp(override val wrapper: Backend)(implicit p: Parameters) extends LazyModuleImp(wrapper) 62 with HasXSParameter{ 63 implicit private val params = wrapper.params 64 val io = IO(new BackendIO()(p, wrapper.params)) 65 66 private val ctrlBlock = wrapper.ctrlBlock.module 67 private val intScheduler = wrapper.intScheduler.get.module 68 private val vfScheduler = wrapper.vfScheduler.get.module 69 private val memScheduler = wrapper.memScheduler.get.module 70 private val dataPath = wrapper.dataPath.module 71 private val intExuBlock = wrapper.intExuBlock.get.module 72 private val vfExuBlock = wrapper.vfExuBlock.get.module 73 private val wbDataPath = Module(new WbDataPath(params)) 74 private val wbFuBusyTable = wrapper.wbFuBusyTable.module 75 76 wbFuBusyTable.io.in.intSchdBusyTable := intScheduler.io.wbFuBusyTable 77 wbFuBusyTable.io.in.vfSchdBusyTable := vfScheduler.io.wbFuBusyTable 78 wbFuBusyTable.io.in.memSchdBusyTable := memScheduler.io.wbFuBusyTable 79 intScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.intRespRead 80 vfScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.vfRespRead 81 memScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.memRespRead 82 dataPath.io.wbConfictRead := wbFuBusyTable.io.out.wbConflictRead 83 84 wbDataPath.io.fromIntExu.flatten.filter(x => x.bits.params.writeIntRf) 85 86 private val vconfig = dataPath.io.vconfigReadPort.data 87 88 ctrlBlock.io.fromTop.hartId := io.fromTop.hartId 89 ctrlBlock.io.frontend <> io.frontend 90 ctrlBlock.io.fromWB.wbData <> wbDataPath.io.toCtrlBlock.writeback 91 ctrlBlock.io.fromMem.stIn <> io.mem.stIn 92 ctrlBlock.io.fromMem.violation <> io.mem.memoryViolation 93 ctrlBlock.io.csrCtrl <> intExuBlock.io.csrio.get.customCtrl 94 ctrlBlock.io.robio.csr.intrBitSet := intExuBlock.io.csrio.get.interrupt 95 ctrlBlock.io.robio.csr.trapTarget := intExuBlock.io.csrio.get.trapTarget 96 ctrlBlock.io.robio.csr.isXRet := intExuBlock.io.csrio.get.isXRet 97 ctrlBlock.io.robio.csr.wfiEvent := intExuBlock.io.csrio.get.wfi_event 98 ctrlBlock.io.robio.lsq <> io.mem.robLsqIO 99 ctrlBlock.io.fromDataPath.vtype := vconfig(7, 0).asTypeOf(new VType) 100 101 intScheduler.io.fromTop.hartId := io.fromTop.hartId 102 intScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 103 intScheduler.io.fromCtrlBlock.pcVec := ctrlBlock.io.toIssueBlock.pcVec 104 intScheduler.io.fromCtrlBlock.targetVec := ctrlBlock.io.toIssueBlock.targetVec 105 intScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 106 intScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.intUops 107 intScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 108 intScheduler.io.vfWriteBack := 0.U.asTypeOf(intScheduler.io.vfWriteBack) 109 intScheduler.io.fromDataPath := dataPath.io.toIntIQ 110 111 memScheduler.io.fromTop.hartId := io.fromTop.hartId 112 memScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 113 memScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 114 memScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.memUops 115 memScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 116 memScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 117 memScheduler.io.fromMem.get.scommit := io.mem.sqDeq 118 memScheduler.io.fromMem.get.lcommit := io.mem.lqDeq 119 memScheduler.io.fromMem.get.sqCancelCnt := io.mem.sqCancelCnt 120 memScheduler.io.fromMem.get.lqCancelCnt := io.mem.lqCancelCnt 121 memScheduler.io.fromMem.get.stIssuePtr := io.mem.stIssuePtr 122 memScheduler.io.fromMem.get.memWaitUpdateReq.staIssue.zip(io.mem.stIn).foreach { case (sink, source) => 123 sink.valid := source.valid 124 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 125 sink.bits.uop.robIdx := source.bits.robIdx 126 } 127 memScheduler.io.fromDataPath := dataPath.io.toMemIQ 128 memScheduler.io.fromMem.get.ldaFeedback := io.mem.ldaIqFeedback 129 memScheduler.io.fromMem.get.staFeedback := io.mem.staIqFeedback 130 131 vfScheduler.io.fromTop.hartId := io.fromTop.hartId 132 vfScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 133 vfScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 134 vfScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.vfUops 135 vfScheduler.io.intWriteBack := 0.U.asTypeOf(vfScheduler.io.intWriteBack) 136 vfScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 137 vfScheduler.io.fromDataPath := dataPath.io.toVfIQ 138 139 dataPath.io.flush := ctrlBlock.io.toDataPath.flush 140 dataPath.io.vconfigReadPort.addr := ctrlBlock.io.toDataPath.vtypeAddr 141 142 for (i <- 0 until dataPath.io.fromIntIQ.length) { 143 for (j <- 0 until dataPath.io.fromIntIQ(i).length) { 144 NewPipelineConnect(intScheduler.io.toDataPath(i)(j), dataPath.io.fromIntIQ(i)(j), dataPath.io.fromIntIQ(i)(j).valid, 145 intScheduler.io.toDataPath(i)(j).bits.common.robIdx.needFlush(ctrlBlock.io.toDataPath.flush), Option("intScheduler2DataPathPipe")) 146 } 147 } 148 149 for (i <- 0 until dataPath.io.fromVfIQ.length) { 150 for (j <- 0 until dataPath.io.fromVfIQ(i).length) { 151 NewPipelineConnect(vfScheduler.io.toDataPath(i)(j), dataPath.io.fromVfIQ(i)(j), dataPath.io.fromVfIQ(i)(j).valid, 152 vfScheduler.io.toDataPath(i)(j).bits.common.robIdx.needFlush(ctrlBlock.io.toDataPath.flush), Option("vfScheduler2DataPathPipe")) 153 } 154 } 155 156 for (i <- 0 until dataPath.io.fromMemIQ.length) { 157 for (j <- 0 until dataPath.io.fromMemIQ(i).length) { 158 NewPipelineConnect(memScheduler.io.toDataPath(i)(j), dataPath.io.fromMemIQ(i)(j), dataPath.io.fromMemIQ(i)(j).valid, 159 memScheduler.io.toDataPath(i)(j).bits.common.robIdx.needFlush(ctrlBlock.io.toDataPath.flush), Option("memScheduler2DataPathPipe")) 160 } 161 } 162 163 println(s"[Backend] wbDataPath.io.toIntPreg: ${wbDataPath.io.toIntPreg.size}, dataPath.io.fromIntWb: ${dataPath.io.fromIntWb.size}") 164 println(s"[Backend] wbDataPath.io.toVfPreg: ${wbDataPath.io.toVfPreg.size}, dataPath.io.fromFpWb: ${dataPath.io.fromVfWb.size}") 165 dataPath.io.fromIntWb := wbDataPath.io.toIntPreg 166 dataPath.io.fromVfWb := wbDataPath.io.toVfPreg 167 dataPath.io.debugIntRat := ctrlBlock.io.debug_int_rat 168 dataPath.io.debugFpRat := ctrlBlock.io.debug_fp_rat 169 dataPath.io.debugVecRat := ctrlBlock.io.debug_vec_rat 170 dataPath.io.debugVconfigRat := ctrlBlock.io.debug_vconfig_rat 171 172 intExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 173 for (i <- 0 until intExuBlock.io.in.length) { 174 for (j <- 0 until intExuBlock.io.in(i).length) { 175 NewPipelineConnect(dataPath.io.toIntExu(i)(j), intExuBlock.io.in(i)(j), intExuBlock.io.in(i)(j).fire, 176 Mux(dataPath.io.toIntExu(i)(j).fire, 177 dataPath.io.toIntExu(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush), 178 intExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush))) 179 } 180 } 181 182 private val csrio = intExuBlock.io.csrio.get 183 csrio.hartId := io.fromTop.hartId 184 csrio.perf.retiredInstr <> ctrlBlock.io.robio.csr.perfinfo.retiredInstr 185 csrio.perf.ctrlInfo <> ctrlBlock.io.perfInfo.ctrlInfo 186 csrio.perf.perfEventsCtrl <> ctrlBlock.getPerf 187 csrio.fpu.fflags := ctrlBlock.io.robio.csr.fflags 188 csrio.fpu.isIllegal := false.B // Todo: remove it 189 csrio.fpu.dirty_fs := ctrlBlock.io.robio.csr.dirty_fs 190 csrio.vpu <> 0.U.asTypeOf(csrio.vpu) // Todo 191 192 val debugVconfig = dataPath.io.debugVconfig.asTypeOf(new VConfig) 193 val debugVtype = VType.toVtypeStruct(debugVconfig.vtype).asUInt 194 val debugVl = debugVconfig.vl 195 csrio.vpu.set_vxsat := ctrlBlock.io.robio.csr.vxsat 196 csrio.vpu.set_vstart.valid := ctrlBlock.io.robio.csr.vcsrFlag 197 csrio.vpu.set_vstart.bits := 0.U 198 csrio.vpu.set_vtype.valid := ctrlBlock.io.robio.csr.vcsrFlag 199 csrio.vpu.set_vtype.bits := ZeroExt(debugVtype, XLEN) 200 csrio.vpu.set_vl.valid := ctrlBlock.io.robio.csr.vcsrFlag 201 csrio.vpu.set_vl.bits := ZeroExt(debugVl, XLEN) 202 csrio.exception := ctrlBlock.io.robio.exception 203 csrio.memExceptionVAddr := io.mem.exceptionVAddr 204 csrio.externalInterrupt := io.fromTop.externalInterrupt 205 csrio.distributedUpdate(0) := io.mem.csrDistributedUpdate 206 csrio.distributedUpdate(1) := io.frontendCsrDistributedUpdate 207 csrio.perf <> io.perf 208 private val fenceio = intExuBlock.io.fenceio.get 209 fenceio.disableSfence := csrio.disableSfence 210 io.fenceio <> fenceio 211 212 vfExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 213 for (i <- 0 until vfExuBlock.io.in.size) { 214 for (j <- 0 until vfExuBlock.io.in(i).size) { 215 NewPipelineConnect(dataPath.io.toFpExu(i)(j), vfExuBlock.io.in(i)(j), vfExuBlock.io.in(i)(j).fire, 216 Mux(dataPath.io.toFpExu(i)(j).fire, 217 dataPath.io.toFpExu(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush), 218 vfExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush))) 219 } 220 } 221 vfExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 222 223 wbDataPath.io.flush := ctrlBlock.io.redirect 224 wbDataPath.io.fromTop.hartId := io.fromTop.hartId 225 wbDataPath.io.fromIntExu <> intExuBlock.io.out 226 wbDataPath.io.fromVfExu <> vfExuBlock.io.out 227 wbDataPath.io.fromMemExu.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 228 sink.valid := source.valid 229 source.ready := sink.ready 230 sink.bits.data := source.bits.data 231 sink.bits.pdest := source.bits.uop.pdest 232 sink.bits.robIdx := source.bits.uop.robIdx 233 sink.bits.intWen.foreach(_ := source.bits.uop.rfWen) 234 sink.bits.fpWen.foreach(_ := source.bits.uop.fpWen) 235 sink.bits.vecWen.foreach(_ := source.bits.uop.vecWen) 236 sink.bits.exceptionVec.foreach(_ := source.bits.uop.exceptionVec) 237 sink.bits.flushPipe.foreach(_ := source.bits.uop.flushPipe) 238 sink.bits.replay.foreach(_ := source.bits.uop.replayInst) 239 sink.bits.debug := source.bits.debug 240 sink.bits.debugInfo := 0.U.asTypeOf(sink.bits.debugInfo) 241 sink.bits.lqIdx.foreach(_ := source.bits.uop.lqIdx) 242 sink.bits.sqIdx.foreach(_ := source.bits.uop.sqIdx) 243 sink.bits.ftqIdx.foreach(_ := source.bits.uop.ftqPtr) 244 sink.bits.ftqOffset.foreach(_ := source.bits.uop.ftqOffset) 245 } 246 247 // to mem 248 io.mem.redirect := ctrlBlock.io.redirect 249 io.mem.issueUops.zip(dataPath.io.toMemExu.flatten).foreach { case (sink, source) => 250 sink.valid := source.valid 251 source.ready := sink.ready 252 sink.bits.iqIdx := source.bits.iqIdx 253 sink.bits.isFirstIssue := source.bits.isFirstIssue 254 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 255 sink.bits.src := 0.U.asTypeOf(sink.bits.src) 256 sink.bits.src.zip(source.bits.src).foreach { case (l, r) => l := r} 257 sink.bits.uop.fuType := source.bits.fuType 258 sink.bits.uop.fuOpType := source.bits.fuOpType 259 sink.bits.uop.imm := source.bits.imm 260 sink.bits.uop.robIdx := source.bits.robIdx 261 sink.bits.uop.pdest := source.bits.pdest 262 sink.bits.uop.rfWen := source.bits.rfWen.getOrElse(false.B) 263 sink.bits.uop.fpWen := source.bits.fpWen.getOrElse(false.B) 264 sink.bits.uop.vecWen := source.bits.vecWen.getOrElse(false.B) 265 sink.bits.uop.flushPipe := source.bits.flushPipe.getOrElse(false.B) 266 sink.bits.uop.pc := source.bits.pc.getOrElse(0.U) 267 sink.bits.uop.lqIdx := source.bits.lqIdx.getOrElse(0.U.asTypeOf(new LqPtr)) 268 sink.bits.uop.sqIdx := source.bits.sqIdx.getOrElse(0.U.asTypeOf(new SqPtr)) 269 sink.bits.uop.ftqPtr := source.bits.ftqIdx.getOrElse(0.U.asTypeOf(new FtqPtr)) 270 sink.bits.uop.ftqOffset := source.bits.ftqOffset.getOrElse(0.U) 271 } 272 io.mem.loadFastMatch := memScheduler.io.toMem.get.loadFastMatch.map(_.fastMatch) 273 io.mem.loadFastImm := memScheduler.io.toMem.get.loadFastMatch.map(_.fastImm) 274 io.mem.tlbCsr := csrio.tlb 275 io.mem.csrCtrl := csrio.customCtrl 276 io.mem.sfence := fenceio.sfence 277 io.mem.isStoreException := CommitType.lsInstIsStore(ctrlBlock.io.robio.exception.bits.commitType) 278 require(io.mem.loadPcRead.size == params.LduCnt) 279 io.mem.loadPcRead.zipWithIndex.foreach { case (loadPcRead, i) => 280 loadPcRead.data := ctrlBlock.io.memLdPcRead(i).data 281 ctrlBlock.io.memLdPcRead(i).ptr := loadPcRead.ptr 282 ctrlBlock.io.memLdPcRead(i).offset := loadPcRead.offset 283 } 284 // mem io 285 io.mem.lsqEnqIO <> memScheduler.io.memIO.get.lsqEnqIO 286 io.mem.robLsqIO <> ctrlBlock.io.robio.lsq 287 io.mem.toSbuffer <> fenceio.sbuffer 288 289 io.frontendSfence := fenceio.sfence 290 io.frontendTlbCsr := csrio.tlb 291 io.frontendCsrCtrl := csrio.customCtrl 292 293 io.tlb <> csrio.tlb 294 295 io.csrCustomCtrl := csrio.customCtrl 296 297 dontTouch(memScheduler.io) 298 dontTouch(io.mem) 299 dontTouch(dataPath.io.toMemExu) 300 dontTouch(wbDataPath.io.fromMemExu) 301} 302 303class BackendMemIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 304 // params alias 305 private val LoadQueueSize = VirtualLoadQueueSize 306 // In/Out // Todo: split it into one-direction bundle 307 val lsqEnqIO = Flipped(new LsqEnqIO) 308 val robLsqIO = new RobLsqIO 309 val toSbuffer = new FenceToSbuffer 310 val ldaIqFeedback = Vec(params.LduCnt, Flipped(new MemRSFeedbackIO)) 311 val staIqFeedback = Vec(params.StaCnt, Flipped(new MemRSFeedbackIO)) 312 val loadPcRead = Vec(params.LduCnt, Flipped(new FtqRead(UInt(VAddrBits.W)))) 313 314 // Input 315 val writeBack = MixedVec(Seq.fill(params.LduCnt + params.StaCnt * 2)(Flipped(DecoupledIO(new MemExuOutput()))) ++ Seq.fill(params.VlduCnt)(Flipped(DecoupledIO(new MemExuOutput(true))))) 316 317 val s3_delayed_load_error = Input(Vec(LoadPipelineWidth, Bool())) 318 val stIn = Input(Vec(params.StaCnt, ValidIO(new DynInst()))) 319 val memoryViolation = Flipped(ValidIO(new Redirect)) 320 val exceptionVAddr = Input(UInt(VAddrBits.W)) 321 val sqDeq = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) 322 val lqDeq = Input(UInt(log2Up(CommitWidth + 1).W)) 323 324 val lqCancelCnt = Input(UInt(log2Up(VirtualLoadQueueSize + 1).W)) 325 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 326 327 val otherFastWakeup = Flipped(Vec(params.LduCnt + 2 * params.StaCnt, ValidIO(new DynInst))) 328 val stIssuePtr = Input(new SqPtr()) 329 330 val csrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 331 332 // Output 333 val redirect = ValidIO(new Redirect) // rob flush MemBlock 334 val issueUops = MixedVec(Seq.fill(params.LduCnt + params.StaCnt * 2)(DecoupledIO(new MemExuInput())) ++ Seq.fill(params.VlduCnt)(DecoupledIO(new MemExuInput(true)))) 335 val loadFastMatch = Vec(params.LduCnt, Output(UInt(params.LduCnt.W))) 336 val loadFastImm = Vec(params.LduCnt, Output(UInt(12.W))) // Imm_I 337 338 val tlbCsr = Output(new TlbCsrBundle) 339 val csrCtrl = Output(new CustomCSRCtrlIO) 340 val sfence = Output(new SfenceBundle) 341 val isStoreException = Output(Bool()) 342} 343 344class BackendIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 345 val fromTop = new Bundle { 346 val hartId = Input(UInt(8.W)) 347 val externalInterrupt = new ExternalInterruptIO 348 } 349 350 val toTop = new Bundle { 351 val cpuHalted = Output(Bool()) 352 } 353 354 val fenceio = new FenceIO 355 // Todo: merge these bundles into BackendFrontendIO 356 val frontend = Flipped(new FrontendToCtrlIO) 357 val frontendSfence = Output(new SfenceBundle) 358 val frontendCsrCtrl = Output(new CustomCSRCtrlIO) 359 val frontendTlbCsr = Output(new TlbCsrBundle) 360 // distributed csr write 361 val frontendCsrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 362 363 val mem = new BackendMemIO 364 365 val perf = Input(new PerfCounterIO) 366 367 val tlb = Output(new TlbCsrBundle) 368 369 val csrCustomCtrl = Output(new CustomCSRCtrlIO) 370} 371