1package xiangshan.backend 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import utility.{PipelineConnect, ZeroExt} 8import xiangshan._ 9import xiangshan.backend.Bundles.{DynInst, MemExuInput, MemExuOutput, FuBusyTableWriteBundle} 10import xiangshan.backend.ctrlblock.CtrlBlock 11import xiangshan.backend.datapath.WbConfig._ 12import xiangshan.backend.datapath.{DataPath, NewPipelineConnect, WbDataPath} 13import xiangshan.backend.exu.ExuBlock 14import xiangshan.backend.fu.vector.Bundles.{VConfig, VType} 15import xiangshan.backend.fu.{FenceIO, FenceToSbuffer, PerfCounterIO, FuConfig} 16import xiangshan.backend.issue.{Scheduler, IntScheduler, MemScheduler, VfScheduler} 17import xiangshan.backend.rob.RobLsqIO 18import xiangshan.frontend.{FtqPtr, FtqRead} 19import xiangshan.mem.{LqPtr, LsqEnqIO, SqPtr} 20 21class Backend(val params: BackendParams)(implicit p: Parameters) extends LazyModule 22 with HasXSParameter { 23 24 for (exuCfg <- params.allExuParams) { 25 val fuConfigs = exuCfg.fuConfigs 26 val wbPortConfigs = exuCfg.wbPortConfigs 27 val immType = exuCfg.immType 28 println(s"exu: ${fuConfigs.map(_.name)}, wb: ${wbPortConfigs}, imm: ${immType}") 29 require(wbPortConfigs.collectFirst { case x: IntWB => x }.nonEmpty == 30 fuConfigs.map(_.writeIntRf).reduce(_ || _), 31 "int wb port has no priority" ) 32 require(wbPortConfigs.collectFirst { case x: VfWB => x }.nonEmpty == 33 fuConfigs.map(x => x.writeFpRf || x.writeVecRf).reduce(_ || _), 34 "vec wb port has no priority" ) 35 } 36 37 println(s"Function Unit: Alu(${params.AluCnt}), Brh(${params.BrhCnt}), Jmp(${params.JmpCnt}), " + 38 s"Ldu(${params.LduCnt}), Sta(${params.StaCnt}), Std(${params.StdCnt})") 39 40 for (cfg <- FuConfig.allConfigs) { 41 println(s"[Backend] $cfg") 42 } 43 44 val ctrlBlock = LazyModule(new CtrlBlock(params)) 45 val intScheduler = params.intSchdParams.map(x => LazyModule(new Scheduler(x))) 46 val vfScheduler = params.vfSchdParams.map(x => LazyModule(new Scheduler(x))) 47 val memScheduler = params.memSchdParams.map(x => LazyModule(new Scheduler(x))) 48 val dataPath = LazyModule(new DataPath(params)) 49 val intExuBlock = params.intSchdParams.map(x => LazyModule(new ExuBlock(x))) 50 val vfExuBlock = params.vfSchdParams.map(x => LazyModule(new ExuBlock(x))) 51 52 lazy val module = new BackendImp(this) 53} 54 55class BackendImp(override val wrapper: Backend)(implicit p: Parameters) extends LazyModuleImp(wrapper) 56 with HasXSParameter{ 57 implicit private val params = wrapper.params 58 val io = IO(new BackendIO()(p, wrapper.params)) 59 60 private val ctrlBlock = wrapper.ctrlBlock.module 61 private val intScheduler = wrapper.intScheduler.get.module 62 private val vfScheduler = wrapper.vfScheduler.get.module 63 private val memScheduler = wrapper.memScheduler.get.module 64 private val dataPath = wrapper.dataPath.module 65 private val intExuBlock = wrapper.intExuBlock.get.module 66 private val vfExuBlock = wrapper.vfExuBlock.get.module 67 private val wbDataPath = Module(new WbDataPath(params)) 68 69 private val (intRespWrite, vfRespWrite, memRespWrite) = (intScheduler.io.wbFuBusyTable.fuBusyTableWrite, 70 vfScheduler.io.wbFuBusyTable.fuBusyTableWrite, 71 memScheduler.io.wbFuBusyTable.fuBusyTableWrite) 72 private val (intRespRead, vfRespRead, memRespRead) = (intScheduler.io.wbFuBusyTable.fuBusyTableRead, 73 vfScheduler.io.wbFuBusyTable.fuBusyTableRead, 74 memScheduler.io.wbFuBusyTable.fuBusyTableRead) 75 private val allRespWrite = (intRespWrite ++ vfRespWrite ++ memRespWrite).flatten 76 private val allRespRead = (intRespRead ++ vfRespRead ++ memRespRead).flatten 77 wbDataPath.io.fromIntExu.flatten.filter(x => x.bits.params.writeIntRf) 78 private val allExuParams = params.allExuParams 79 private val respWriteWithParams = allRespWrite.zip(allExuParams) 80 println(s"[respWriteWithParams] is ${respWriteWithParams}") 81 respWriteWithParams.foreach{ case(l,r) => 82 println(s"FuBusyTableWriteBundle is ${l}, ExeUnitParams is ${r}") 83 } 84// require(false) 85 86 private val intWBFuGroup = params.getIntWBExeGroup.map{case(groupId, exeUnit) => (groupId, exeUnit.flatMap(_.fuConfigs))} 87 private val intLatencyCertains = intWBFuGroup.map{case (k,v) => (k, v.map(_.latency.latencyVal.nonEmpty).reduce(_ && _))} 88 private val intWBFuLatencyMap = intLatencyCertains.map{case (k, latencyCertain) => 89 if (latencyCertain) Some(intWBFuGroup(k).map(y => (y.fuType, y.latency.latencyVal.get))) 90 else None 91 }.toSeq 92 private val intWBFuLatencyValMax = intWBFuLatencyMap.map(latencyMap=> latencyMap.map(x => x.map(_._2).max)) 93 94 private val vfWBFuGroup = params.getVfWBExeGroup.map{case(groupId, exeUnit) => (groupId, exeUnit.flatMap(_.fuConfigs))} 95 private val vfLatencyCertains = vfWBFuGroup.map{case (k,v) => (k, v.map(_.latency.latencyVal.nonEmpty).reduce(_ && _))} 96 val vfWBFuLatencyMap = vfLatencyCertains.map { case (k, latencyCertain) => 97 if (latencyCertain) Some(vfWBFuGroup(k).map(y => (y.fuType, y.latency.latencyVal.get))) 98 else None 99 }.toSeq 100 private val vfWBFuLatencyValMax = vfWBFuLatencyMap.map(latencyMap => latencyMap.map(x => x.map(_._2).max)) 101 102 private val intWBFuBusyTable = intWBFuLatencyValMax.map { case y => if (y.getOrElse(0)>0) Some(Reg(UInt(y.getOrElse(1).W))) else None } 103 println(s"[intWBFuBusyTable] is ${intWBFuBusyTable.map(x => x) }") 104 private val vfWBFuBusyTable = vfWBFuLatencyValMax.map { case y => if (y.getOrElse(0)>0) Some(Reg(UInt(y.getOrElse(1).W))) else None } 105 106 intWBFuBusyTable.map(x => x.map(dontTouch(_))) 107 dontTouch(intScheduler.io.wbFuBusyTable) 108 dontTouch(vfScheduler.io.wbFuBusyTable) 109 dontTouch(memScheduler.io.wbFuBusyTable) 110 111 // intWBFuBusyTable write 112 for (i <- 0 until intWBFuGroup.size) { 113 if (intWBFuBusyTable(i).nonEmpty){ 114 val deqIsLatencyNumMask = respWriteWithParams.zipWithIndex.map{ case((r, p), idx) => 115 val resps = p.schdType match { 116 case IntScheduler() => Seq(r.deqResp, r.og0Resp, r.og1Resp) 117 case MemScheduler() => Seq(r.deqResp, r.og1Resp) 118 case VfScheduler() => Seq(r.deqResp, r.og1Resp) 119 case _ => null 120 } 121 val matchI = (p.wbPortConfigs.collectFirst{ case x: IntWB => x }.getOrElse(-1)) == i 122 if(matchI){ 123 Mux(resps(0).valid && resps(0).bits.respType === RSFeedbackType.issueSuccess, 124 Cat((0 until intWBFuLatencyValMax(i).getOrElse(0)).map { case num => 125 val latencyNumFuType = p.fuConfigs.filter(_.latency.latencyVal.getOrElse(-1) == num+1).map(_.fuType) 126 val isLatencyNum = Cat(latencyNumFuType.map(futype => resps(0).bits.fuType === futype.U)).asUInt().orR() // The latency of the deqResp inst is Num 127 isLatencyNum 128 }), 129 0.U) 130 } else 0.U 131 }.reduce(_|_) 132 val og0IsLatencyNumMask = WireInit(-1.S.asTypeOf(deqIsLatencyNumMask)) 133 og0IsLatencyNumMask := respWriteWithParams.zipWithIndex.map { case ((r, p), idx) => 134 val resps = p.schdType match { 135 case IntScheduler() => Seq(r.deqResp, r.og0Resp, r.og1Resp) 136 case MemScheduler() => Seq(r.deqResp, r.og1Resp) 137 case VfScheduler() => Seq(r.deqResp, r.og1Resp) 138 case _ => null 139 } 140 val matchI = (p.wbPortConfigs.collectFirst { case x: IntWB => x }.getOrElse(-1)) == i 141 if (matchI) { 142 Mux(resps(1).valid && resps(1).bits.respType === RSFeedbackType.issueSuccess, 143 ~(Cat(Cat((0 until intWBFuLatencyValMax(i).getOrElse(0)).map { case num => 144 val latencyNumFuType = p.fuConfigs.filter(_.latency.latencyVal.getOrElse(-1) == num + 1).map(_.fuType) 145 val isLatencyNum = Cat(latencyNumFuType.map(futype => resps(1).bits.fuType === futype.U)).asUInt().orR() // The latency of the deqResp inst is Num 146 isLatencyNum 147 }), 0.U(1.W))), 148 -1.S.asTypeOf(deqIsLatencyNumMask)).asTypeOf(deqIsLatencyNumMask) 149 } else -1.S.asTypeOf(deqIsLatencyNumMask) 150 }.reduce(_&_) 151 val og1IsLatencyNumMask = WireInit(-1.S.asTypeOf(deqIsLatencyNumMask)) 152 og1IsLatencyNumMask := respWriteWithParams.zipWithIndex.map { case ((r, p), idx) => 153 val resps = p.schdType match { 154 case IntScheduler() => Seq(r.deqResp, r.og0Resp, r.og1Resp) 155 case MemScheduler() => Seq(r.deqResp, r.og1Resp) 156 case VfScheduler() => Seq(r.deqResp, r.og1Resp) 157 case _ => null 158 } 159 val matchI = (p.wbPortConfigs.collectFirst { case x: IntWB => x }.getOrElse(-1)) == i 160 if (matchI && resps.length==3) { 161 Mux(resps(2).valid && resps(2).bits.respType === RSFeedbackType.issueSuccess, 162 ~(Cat(Cat((0 until intWBFuLatencyValMax(i).getOrElse(0)).map { case num => 163 val latencyNumFuType = p.fuConfigs.filter(_.latency.latencyVal.getOrElse(-1) == num + 1).map(_.fuType) 164 val isLatencyNum = Cat(latencyNumFuType.map(futype => resps(2).bits.fuType === futype.U)).asUInt().orR() // The latency of the deqResp inst is Num 165 isLatencyNum 166 }), 0.U(1.W))), 167 -1.S.asTypeOf(deqIsLatencyNumMask)).asTypeOf(deqIsLatencyNumMask) 168 } else -1.S.asTypeOf(deqIsLatencyNumMask) 169 }.reduce(_ & _) 170 dontTouch(deqIsLatencyNumMask) 171 dontTouch(og0IsLatencyNumMask) 172 dontTouch(og1IsLatencyNumMask) 173 intWBFuBusyTable(i).get := ((intWBFuBusyTable(i).get << 1.U).asUInt() | deqIsLatencyNumMask) & og0IsLatencyNumMask.asUInt() & og1IsLatencyNumMask.asUInt() 174 } 175 } 176 // intWBFuBusyTable read 177 for(i <- 0 until allRespRead.size){ 178 allRespRead(i) := intWBFuBusyTable.zipWithIndex.map{ case (ele, idx) => 179 val matchI = (allExuParams(i).wbPortConfigs.collectFirst { case x: IntWB => x }.getOrElse(-1)) == idx 180 if(ele.nonEmpty && matchI){ 181 ele.get.asTypeOf(allRespRead(i)) 182 }else{ 183 0.U.asTypeOf(allRespRead(i)) 184 } 185 }.reduce(_|_) 186 } 187 188 ctrlBlock.io.fromTop.hartId := io.fromTop.hartId 189 ctrlBlock.io.frontend <> io.frontend 190 ctrlBlock.io.fromWB.wbData <> wbDataPath.io.toCtrlBlock.writeback 191 ctrlBlock.io.fromMem.stIn <> io.mem.stIn 192 ctrlBlock.io.fromMem.violation <> io.mem.memoryViolation 193 ctrlBlock.io.csrCtrl <> intExuBlock.io.csrio.get.customCtrl 194 ctrlBlock.io.robio.csr.intrBitSet := intExuBlock.io.csrio.get.interrupt 195 ctrlBlock.io.robio.csr.trapTarget := intExuBlock.io.csrio.get.trapTarget 196 ctrlBlock.io.robio.csr.isXRet := intExuBlock.io.csrio.get.isXRet 197 ctrlBlock.io.robio.csr.wfiEvent := intExuBlock.io.csrio.get.wfi_event 198 ctrlBlock.io.robio.lsq <> io.mem.robLsqIO 199 200 intScheduler.io.fromTop.hartId := io.fromTop.hartId 201 intScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 202 intScheduler.io.fromCtrlBlock.pcVec := ctrlBlock.io.toIssueBlock.pcVec 203 intScheduler.io.fromCtrlBlock.targetVec := ctrlBlock.io.toIssueBlock.targetVec 204 intScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 205 intScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.intUops 206 intScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 207 intScheduler.io.vfWriteBack := 0.U.asTypeOf(intScheduler.io.vfWriteBack) 208 209 memScheduler.io.fromTop.hartId := io.fromTop.hartId 210 memScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 211 memScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 212 memScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.memUops 213 memScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 214 memScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 215 memScheduler.io.fromMem.get.scommit := io.mem.sqDeq 216 memScheduler.io.fromMem.get.lcommit := io.mem.lqDeq 217 memScheduler.io.fromMem.get.sqCancelCnt := io.mem.sqCancelCnt 218 memScheduler.io.fromMem.get.lqCancelCnt := io.mem.lqCancelCnt 219 memScheduler.io.fromMem.get.stIssuePtr := io.mem.stIssuePtr 220 memScheduler.io.fromMem.get.memWaitUpdateReq.staIssue.zip(io.mem.stIn).foreach { case (sink, source) => 221 sink.valid := source.valid 222 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 223 sink.bits.uop.robIdx := source.bits.robIdx 224 } 225 io.mem.ldaIqFeedback <> memScheduler.io.fromMem.get.ldaFeedback 226 io.mem.staIqFeedback <> memScheduler.io.fromMem.get.staFeedback 227 228 vfScheduler.io.fromTop.hartId := io.fromTop.hartId 229 vfScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 230 vfScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 231 vfScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.vfUops 232 vfScheduler.io.intWriteBack := 0.U.asTypeOf(vfScheduler.io.intWriteBack) 233 vfScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 234 235 dataPath.io.flush := ctrlBlock.io.toDataPath.flush 236 dataPath.io.vconfigReadPort.addr := ctrlBlock.io.toDataPath.vtypeAddr 237 val vconfig = dataPath.io.vconfigReadPort.data 238 ctrlBlock.io.fromDataPath.vtype := vconfig(7, 0).asTypeOf(new VType) 239 for (i <- 0 until dataPath.io.fromIntIQ.length) { 240 for (j <- 0 until dataPath.io.fromIntIQ(i).length) { 241 NewPipelineConnect(intScheduler.io.toDataPath(i)(j), dataPath.io.fromIntIQ(i)(j), dataPath.io.fromIntIQ(i)(j).valid, 242 intScheduler.io.toDataPath(i)(j).bits.common.robIdx.needFlush(ctrlBlock.io.toDataPath.flush), Option("intScheduler2DataPathPipe")) 243 intScheduler.io.fromDataPath(i)(j) := dataPath.io.toIntIQ(i)(j) 244 } 245 } 246 247 for (i <- 0 until dataPath.io.fromVfIQ.length) { 248 for (j <- 0 until dataPath.io.fromVfIQ(i).length) { 249 NewPipelineConnect(vfScheduler.io.toDataPath(i)(j), dataPath.io.fromVfIQ(i)(j), dataPath.io.fromVfIQ(i)(j).valid, 250 vfScheduler.io.toDataPath(i)(j).bits.common.robIdx.needFlush(ctrlBlock.io.toDataPath.flush), Option("vfScheduler2DataPathPipe")) 251 vfScheduler.io.fromDataPath(i)(j) := dataPath.io.toVfIQ(i)(j) 252 } 253 } 254 255 for (i <- 0 until dataPath.io.fromMemIQ.length) { 256 for (j <- 0 until dataPath.io.fromMemIQ(i).length) { 257 NewPipelineConnect(memScheduler.io.toDataPath(i)(j), dataPath.io.fromMemIQ(i)(j), dataPath.io.fromMemIQ(i)(j).valid, 258 memScheduler.io.toDataPath(i)(j).bits.common.robIdx.needFlush(ctrlBlock.io.toDataPath.flush), Option("memScheduler2DataPathPipe")) 259 memScheduler.io.fromDataPath(i)(j) := dataPath.io.toMemIQ(i)(j) 260 } 261 } 262 263 println(s"[Backend] wbDataPath.io.toIntPreg: ${wbDataPath.io.toIntPreg.size}, dataPath.io.fromIntWb: ${dataPath.io.fromIntWb.size}") 264 println(s"[Backend] wbDataPath.io.toVfPreg: ${wbDataPath.io.toVfPreg.size}, dataPath.io.fromFpWb: ${dataPath.io.fromVfWb.size}") 265 dataPath.io.fromIntWb := wbDataPath.io.toIntPreg 266 dataPath.io.fromVfWb := wbDataPath.io.toVfPreg 267 dataPath.io.debugIntRat := ctrlBlock.io.debug_int_rat 268 dataPath.io.debugFpRat := ctrlBlock.io.debug_fp_rat 269 dataPath.io.debugVecRat := ctrlBlock.io.debug_vec_rat 270 dataPath.io.debugVconfigRat := ctrlBlock.io.debug_vconfig_rat 271 272 intExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 273 for (i <- 0 until intExuBlock.io.in.length) { 274 for (j <- 0 until intExuBlock.io.in(i).length) { 275 NewPipelineConnect(dataPath.io.toIntExu(i)(j), intExuBlock.io.in(i)(j), intExuBlock.io.in(i)(j).fire, 276 Mux(dataPath.io.toIntExu(i)(j).fire, 277 dataPath.io.toIntExu(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush), 278 intExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush))) 279 } 280 } 281 282 private val csrio = intExuBlock.io.csrio.get 283 csrio.hartId := io.fromTop.hartId 284 csrio.perf.retiredInstr <> ctrlBlock.io.robio.csr.perfinfo.retiredInstr 285 csrio.perf.ctrlInfo <> ctrlBlock.io.perfInfo.ctrlInfo 286 csrio.perf.perfEventsCtrl <> ctrlBlock.getPerf 287 csrio.fpu.fflags := ctrlBlock.io.robio.csr.fflags 288 csrio.fpu.isIllegal := false.B // Todo: remove it 289 csrio.fpu.dirty_fs := ctrlBlock.io.robio.csr.dirty_fs 290 csrio.vpu <> 0.U.asTypeOf(csrio.vpu) // Todo 291 292 val debugVconfig = dataPath.io.debugVconfig.asTypeOf(new VConfig) 293 val debugVtype = VType.toVtypeStruct(debugVconfig.vtype).asUInt 294 val debugVl = debugVconfig.vl 295 csrio.vpu.set_vxsat := ctrlBlock.io.robio.csr.vxsat 296 csrio.vpu.set_vstart.valid := ctrlBlock.io.robio.csr.vcsrFlag 297 csrio.vpu.set_vstart.bits := 0.U 298 csrio.vpu.set_vtype.valid := ctrlBlock.io.robio.csr.vcsrFlag 299 csrio.vpu.set_vtype.bits := ZeroExt(debugVtype, XLEN) 300 csrio.vpu.set_vl.valid := ctrlBlock.io.robio.csr.vcsrFlag 301 csrio.vpu.set_vl.bits := ZeroExt(debugVl, XLEN) 302 csrio.exception := ctrlBlock.io.robio.exception 303 csrio.memExceptionVAddr := io.mem.exceptionVAddr 304 csrio.externalInterrupt := io.fromTop.externalInterrupt 305 csrio.distributedUpdate(0) := io.mem.csrDistributedUpdate 306 csrio.distributedUpdate(1) := io.frontendCsrDistributedUpdate 307 csrio.perf <> io.perf 308 private val fenceio = intExuBlock.io.fenceio.get 309 fenceio.disableSfence := csrio.disableSfence 310 io.fenceio <> fenceio 311 312 vfExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 313 for (i <- 0 until vfExuBlock.io.in.size) { 314 for (j <- 0 until vfExuBlock.io.in(i).size) { 315 NewPipelineConnect(dataPath.io.toFpExu(i)(j), vfExuBlock.io.in(i)(j), vfExuBlock.io.in(i)(j).fire, 316 Mux(dataPath.io.toFpExu(i)(j).fire, 317 dataPath.io.toFpExu(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush), 318 vfExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush))) 319 } 320 } 321 vfExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 322 323 wbDataPath.io.flush := ctrlBlock.io.redirect 324 wbDataPath.io.fromTop.hartId := io.fromTop.hartId 325 wbDataPath.io.fromIntExu <> intExuBlock.io.out 326 wbDataPath.io.fromVfExu <> vfExuBlock.io.out 327 wbDataPath.io.fromMemExu.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 328 sink.valid := source.valid 329 source.ready := sink.ready 330 sink.bits.data := source.bits.data 331 sink.bits.pdest := source.bits.uop.pdest 332 sink.bits.robIdx := source.bits.uop.robIdx 333 sink.bits.intWen.foreach(_ := source.bits.uop.rfWen) 334 sink.bits.fpWen.foreach(_ := source.bits.uop.fpWen) 335 sink.bits.vecWen.foreach(_ := source.bits.uop.vecWen) 336 sink.bits.exceptionVec.foreach(_ := source.bits.uop.exceptionVec) 337 sink.bits.flushPipe.foreach(_ := source.bits.uop.flushPipe) 338 sink.bits.replay.foreach(_ := source.bits.uop.replayInst) 339 sink.bits.debug := source.bits.debug 340 sink.bits.debugInfo := 0.U.asTypeOf(sink.bits.debugInfo) 341 sink.bits.lqIdx.foreach(_ := source.bits.uop.lqIdx) 342 sink.bits.sqIdx.foreach(_ := source.bits.uop.sqIdx) 343 sink.bits.ftqIdx.foreach(_ := source.bits.uop.ftqPtr) 344 sink.bits.ftqOffset.foreach(_ := source.bits.uop.ftqOffset) 345 } 346 347 // to mem 348 io.mem.redirect := ctrlBlock.io.redirect 349 io.mem.issueUops.zip(dataPath.io.toMemExu.flatten).foreach { case (sink, source) => 350 sink.valid := source.valid 351 source.ready := sink.ready 352 sink.bits.iqIdx := source.bits.iqIdx 353 sink.bits.isFirstIssue := source.bits.isFirstIssue 354 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 355 sink.bits.src := 0.U.asTypeOf(sink.bits.src) 356 sink.bits.src.zip(source.bits.src).foreach { case (l, r) => l := r} 357 sink.bits.uop.fuType := source.bits.fuType 358 sink.bits.uop.fuOpType := source.bits.fuOpType 359 sink.bits.uop.imm := source.bits.imm 360 sink.bits.uop.robIdx := source.bits.robIdx 361 sink.bits.uop.pdest := source.bits.pdest 362 sink.bits.uop.rfWen := source.bits.rfWen.getOrElse(false.B) 363 sink.bits.uop.fpWen := source.bits.fpWen.getOrElse(false.B) 364 sink.bits.uop.vecWen := source.bits.vecWen.getOrElse(false.B) 365 sink.bits.uop.flushPipe := source.bits.flushPipe.getOrElse(false.B) 366 sink.bits.uop.pc := source.bits.pc.getOrElse(0.U) 367 sink.bits.uop.lqIdx := source.bits.lqIdx.getOrElse(0.U.asTypeOf(new LqPtr)) 368 sink.bits.uop.sqIdx := source.bits.sqIdx.getOrElse(0.U.asTypeOf(new SqPtr)) 369 sink.bits.uop.ftqPtr := source.bits.ftqIdx.getOrElse(0.U.asTypeOf(new FtqPtr)) 370 sink.bits.uop.ftqOffset := source.bits.ftqOffset.getOrElse(0.U) 371 } 372 io.mem.loadFastMatch := memScheduler.io.toMem.get.loadFastMatch.map(_.fastMatch) 373 io.mem.loadFastImm := memScheduler.io.toMem.get.loadFastMatch.map(_.fastImm) 374 io.mem.tlbCsr := csrio.tlb 375 io.mem.csrCtrl := csrio.customCtrl 376 io.mem.sfence := fenceio.sfence 377 io.mem.isStoreException := CommitType.lsInstIsStore(ctrlBlock.io.robio.exception.bits.commitType) 378 require(io.mem.loadPcRead.size == params.LduCnt) 379 io.mem.loadPcRead.zipWithIndex.foreach { case (loadPcRead, i) => 380 loadPcRead.data := ctrlBlock.io.memLdPcRead(i).data 381 ctrlBlock.io.memLdPcRead(i).ptr := loadPcRead.ptr 382 ctrlBlock.io.memLdPcRead(i).offset := loadPcRead.offset 383 } 384 // mem io 385 io.mem.lsqEnqIO <> memScheduler.io.memIO.get.lsqEnqIO 386 io.mem.robLsqIO <> ctrlBlock.io.robio.lsq 387 io.mem.toSbuffer <> fenceio.sbuffer 388 389 io.frontendSfence := fenceio.sfence 390 io.frontendTlbCsr := csrio.tlb 391 io.frontendCsrCtrl := csrio.customCtrl 392 393 io.tlb <> csrio.tlb 394 395 io.csrCustomCtrl := csrio.customCtrl 396 397 dontTouch(memScheduler.io) 398 dontTouch(io.mem) 399 dontTouch(dataPath.io.toMemExu) 400 dontTouch(wbDataPath.io.fromMemExu) 401} 402 403class BackendMemIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 404 // params alias 405 private val LoadQueueSize = VirtualLoadQueueSize 406 // In/Out // Todo: split it into one-direction bundle 407 val lsqEnqIO = Flipped(new LsqEnqIO) 408 val robLsqIO = new RobLsqIO 409 val toSbuffer = new FenceToSbuffer 410 val ldaIqFeedback = Vec(params.LduCnt, Flipped(new MemRSFeedbackIO)) 411 val staIqFeedback = Vec(params.StaCnt, Flipped(new MemRSFeedbackIO)) 412 val loadPcRead = Vec(params.LduCnt, Flipped(new FtqRead(UInt(VAddrBits.W)))) 413 414 // Input 415 val writeBack = MixedVec(Seq.fill(params.LduCnt + params.StaCnt * 2)(Flipped(DecoupledIO(new MemExuOutput()))) ++ Seq.fill(params.VlduCnt)(Flipped(DecoupledIO(new MemExuOutput(true))))) 416 417 val s3_delayed_load_error = Input(Vec(LoadPipelineWidth, Bool())) 418 val stIn = Input(Vec(params.StaCnt, ValidIO(new DynInst()))) 419 val memoryViolation = Flipped(ValidIO(new Redirect)) 420 val exceptionVAddr = Input(UInt(VAddrBits.W)) 421 val sqDeq = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) 422 val lqDeq = Input(UInt(log2Up(CommitWidth + 1).W)) 423 424 val lqCancelCnt = Input(UInt(log2Up(VirtualLoadQueueSize + 1).W)) 425 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 426 427 val otherFastWakeup = Flipped(Vec(params.LduCnt + 2 * params.StaCnt, ValidIO(new DynInst))) 428 val stIssuePtr = Input(new SqPtr()) 429 430 val csrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 431 432 // Output 433 val redirect = ValidIO(new Redirect) // rob flush MemBlock 434 val issueUops = MixedVec(Seq.fill(params.LduCnt + params.StaCnt * 2)(DecoupledIO(new MemExuInput())) ++ Seq.fill(params.VlduCnt)(DecoupledIO(new MemExuInput(true)))) 435 val loadFastMatch = Vec(params.LduCnt, Output(UInt(params.LduCnt.W))) 436 val loadFastImm = Vec(params.LduCnt, Output(UInt(12.W))) // Imm_I 437 438 val tlbCsr = Output(new TlbCsrBundle) 439 val csrCtrl = Output(new CustomCSRCtrlIO) 440 val sfence = Output(new SfenceBundle) 441 val isStoreException = Output(Bool()) 442} 443 444class BackendIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 445 val fromTop = new Bundle { 446 val hartId = Input(UInt(8.W)) 447 val externalInterrupt = new ExternalInterruptIO 448 } 449 450 val toTop = new Bundle { 451 val cpuHalted = Output(Bool()) 452 } 453 454 val fenceio = new FenceIO 455 // Todo: merge these bundles into BackendFrontendIO 456 val frontend = Flipped(new FrontendToCtrlIO) 457 val frontendSfence = Output(new SfenceBundle) 458 val frontendCsrCtrl = Output(new CustomCSRCtrlIO) 459 val frontendTlbCsr = Output(new TlbCsrBundle) 460 // distributed csr write 461 val frontendCsrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 462 463 val mem = new BackendMemIO 464 465 val perf = Input(new PerfCounterIO) 466 467 val tlb = Output(new TlbCsrBundle) 468 469 val csrCustomCtrl = Output(new CustomCSRCtrlIO) 470} 471