1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15* 16* 17* Acknowledgement 18* 19* This implementation is inspired by several key papers: 20* [1] Robert. M. Tomasulo. "[An efficient algorithm for exploiting multiple arithmetic units.] 21* (https://doi.org/10.1147/rd.111.0025)" IBM Journal of Research and Development (IBMJ) 11.1: 25-33. 1967. 22***************************************************************************************/ 23 24package xiangshan.backend 25 26import org.chipsalliance.cde.config.Parameters 27import chisel3._ 28import chisel3.util._ 29import device.MsiInfoBundle 30import difftest._ 31import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 32import system.HasSoCParameter 33import utility._ 34import xiangshan._ 35import xiangshan.backend.Bundles.{DynInst, IssueQueueIQWakeUpBundle, LoadShouldCancel, MemExuInput, MemExuOutput, VPUCtrlSignals} 36import xiangshan.backend.ctrlblock.{DebugLSIO, LsTopdownInfo} 37import xiangshan.backend.datapath.DataConfig.{IntData, VecData, FpData} 38import xiangshan.backend.datapath.RdConfig.{IntRD, VfRD} 39import xiangshan.backend.datapath.WbConfig._ 40import xiangshan.backend.datapath.DataConfig._ 41import xiangshan.backend.datapath._ 42import xiangshan.backend.dispatch.CoreDispatchTopDownIO 43import xiangshan.backend.exu.ExuBlock 44import xiangshan.backend.fu.vector.Bundles.{VConfig, VType} 45import xiangshan.backend.fu.{FenceIO, FenceToSbuffer, FuConfig, FuType, PFEvent, PerfCounterIO} 46import xiangshan.backend.issue.EntryBundles._ 47import xiangshan.backend.issue.{CancelNetwork, Scheduler, SchedulerArithImp, SchedulerImpBase, SchedulerMemImp} 48import xiangshan.backend.rob.{RobCoreTopDownIO, RobDebugRollingIO, RobLsqIO, RobPtr} 49import xiangshan.frontend.{FtqPtr, FtqRead, PreDecodeInfo} 50import xiangshan.mem.{LqPtr, LsqEnqIO, SqPtr} 51 52import scala.collection.mutable 53 54class Backend(val params: BackendParams)(implicit p: Parameters) extends LazyModule 55 with HasXSParameter { 56 override def shouldBeInlined: Boolean = false 57 val inner = LazyModule(new BackendInlined(params)) 58 lazy val module = new BackendImp(this) 59} 60 61class BackendImp(wrapper: Backend)(implicit p: Parameters) extends LazyModuleImp(wrapper) { 62 val io = IO(new BackendIO()(p, wrapper.params)) 63 io <> wrapper.inner.module.io 64 if (p(DebugOptionsKey).ResetGen) { 65 ResetGen(ResetGenNode(Seq(ModuleNode(wrapper.inner.module))), reset, sim = false) 66 } 67} 68 69class BackendInlined(val params: BackendParams)(implicit p: Parameters) extends LazyModule 70 with HasXSParameter { 71 72 override def shouldBeInlined: Boolean = true 73 74 // check read & write port config 75 params.configChecks 76 77 /* Only update the idx in mem-scheduler here 78 * Idx in other schedulers can be updated the same way if needed 79 * 80 * Also note that we filter out the 'stData issue-queues' when counting 81 */ 82 for ((ibp, idx) <- params.memSchdParams.get.issueBlockParams.filter(iq => iq.StdCnt == 0).zipWithIndex) { 83 ibp.updateIdx(idx) 84 } 85 86 println(params.iqWakeUpParams) 87 88 for ((schdCfg, i) <- params.allSchdParams.zipWithIndex) { 89 schdCfg.bindBackendParam(params) 90 } 91 92 for ((iqCfg, i) <- params.allIssueParams.zipWithIndex) { 93 iqCfg.bindBackendParam(params) 94 } 95 96 for ((exuCfg, i) <- params.allExuParams.zipWithIndex) { 97 exuCfg.bindBackendParam(params) 98 exuCfg.updateIQWakeUpConfigs(params.iqWakeUpParams) 99 exuCfg.updateExuIdx(i) 100 } 101 102 println("[Backend] ExuConfigs:") 103 for (exuCfg <- params.allExuParams) { 104 val fuConfigs = exuCfg.fuConfigs 105 val wbPortConfigs = exuCfg.wbPortConfigs 106 val immType = exuCfg.immType 107 108 println("[Backend] " + 109 s"${exuCfg.name}: " + 110 (if (exuCfg.fakeUnit) "fake, " else "") + 111 (if (exuCfg.hasLoadFu || exuCfg.hasHyldaFu) s"LdExuIdx(${backendParams.getLdExuIdx(exuCfg)})" else "") + 112 s"${fuConfigs.map(_.name).mkString("fu(s): {", ",", "}")}, " + 113 s"${wbPortConfigs.mkString("wb: {", ",", "}")}, " + 114 s"${immType.map(SelImm.mkString(_)).mkString("imm: {", ",", "}")}, " + 115 s"latMax(${exuCfg.latencyValMax}), ${exuCfg.fuLatancySet.mkString("lat: {", ",", "}")}, " + 116 s"srcReg(${exuCfg.numRegSrc})" 117 ) 118 require( 119 wbPortConfigs.collectFirst { case x: IntWB => x }.nonEmpty == 120 fuConfigs.map(_.writeIntRf).reduce(_ || _), 121 s"${exuCfg.name} int wb port has no priority" 122 ) 123 require( 124 wbPortConfigs.collectFirst { case x: FpWB => x }.nonEmpty == 125 fuConfigs.map(x => x.writeFpRf).reduce(_ || _), 126 s"${exuCfg.name} fp wb port has no priority" 127 ) 128 require( 129 wbPortConfigs.collectFirst { case x: VfWB => x }.nonEmpty == 130 fuConfigs.map(x => x.writeVecRf).reduce(_ || _), 131 s"${exuCfg.name} vec wb port has no priority" 132 ) 133 } 134 135 println(s"[Backend] all fu configs") 136 for (cfg <- FuConfig.allConfigs) { 137 println(s"[Backend] $cfg") 138 } 139 140 println(s"[Backend] Int RdConfigs: ExuName(Priority)") 141 for ((port, seq) <- params.getRdPortParams(IntData())) { 142 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 143 } 144 145 println(s"[Backend] Int WbConfigs: ExuName(Priority)") 146 for ((port, seq) <- params.getWbPortParams(IntData())) { 147 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 148 } 149 150 println(s"[Backend] Fp RdConfigs: ExuName(Priority)") 151 for ((port, seq) <- params.getRdPortParams(FpData())) { 152 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 153 } 154 155 println(s"[Backend] Fp WbConfigs: ExuName(Priority)") 156 for ((port, seq) <- params.getWbPortParams(FpData())) { 157 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 158 } 159 160 println(s"[Backend] Vf RdConfigs: ExuName(Priority)") 161 for ((port, seq) <- params.getRdPortParams(VecData())) { 162 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 163 } 164 165 println(s"[Backend] Vf WbConfigs: ExuName(Priority)") 166 for ((port, seq) <- params.getWbPortParams(VecData())) { 167 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 168 } 169 170 println(s"[Backend] Dispatch Configs:") 171 println(s"[Backend] Load IQ enq width(${params.numLoadDp}), Store IQ enq width(${params.numStoreDp})") 172 println(s"[Backend] Load DP width(${LSQLdEnqWidth}), Store DP width(${LSQStEnqWidth})") 173 174 params.updateCopyPdestInfo 175 println(s"[Backend] copyPdestInfo ${params.copyPdestInfo}") 176 params.allExuParams.map(_.copyNum) 177 val ctrlBlock = LazyModule(new CtrlBlock(params)) 178 val pcTargetMem = LazyModule(new PcTargetMem(params)) 179 val intScheduler = params.intSchdParams.map(x => LazyModule(new Scheduler(x))) 180 val fpScheduler = params.fpSchdParams.map(x => LazyModule(new Scheduler(x))) 181 val vfScheduler = params.vfSchdParams.map(x => LazyModule(new Scheduler(x))) 182 val memScheduler = params.memSchdParams.map(x => LazyModule(new Scheduler(x))) 183 val dataPath = LazyModule(new DataPath(params)) 184 val intExuBlock = params.intSchdParams.map(x => LazyModule(new ExuBlock(x))) 185 val fpExuBlock = params.fpSchdParams.map(x => LazyModule(new ExuBlock(x))) 186 val vfExuBlock = params.vfSchdParams.map(x => LazyModule(new ExuBlock(x))) 187 val wbFuBusyTable = LazyModule(new WbFuBusyTable(params)) 188 189 lazy val module = new BackendInlinedImp(this) 190} 191 192class BackendInlinedImp(override val wrapper: BackendInlined)(implicit p: Parameters) extends LazyModuleImp(wrapper) 193 with HasXSParameter 194 with HasPerfEvents 195 with HasCriticalErrors { 196 implicit private val params: BackendParams = wrapper.params 197 198 val io = IO(new BackendIO()(p, wrapper.params)) 199 200 private val ctrlBlock = wrapper.ctrlBlock.module 201 private val pcTargetMem = wrapper.pcTargetMem.module 202 private val intScheduler: SchedulerImpBase = wrapper.intScheduler.get.module 203 private val fpScheduler = wrapper.fpScheduler.get.module 204 private val vfScheduler = wrapper.vfScheduler.get.module 205 private val memScheduler = wrapper.memScheduler.get.module 206 private val dataPath = wrapper.dataPath.module 207 private val intExuBlock = wrapper.intExuBlock.get.module 208 private val fpExuBlock = wrapper.fpExuBlock.get.module 209 private val vfExuBlock = wrapper.vfExuBlock.get.module 210 private val og2ForVector = Module(new Og2ForVector(params)) 211 private val bypassNetwork = Module(new BypassNetwork) 212 private val wbDataPath = Module(new WbDataPath(params)) 213 private val wbFuBusyTable = wrapper.wbFuBusyTable.module 214 private val vecExcpMod = Module(new VecExcpDataMergeModule) 215 216 private val iqWakeUpMappedBundle: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = ( 217 intScheduler.io.toSchedulers.wakeupVec ++ 218 fpScheduler.io.toSchedulers.wakeupVec ++ 219 vfScheduler.io.toSchedulers.wakeupVec ++ 220 memScheduler.io.toSchedulers.wakeupVec 221 ).map(x => (x.bits.exuIdx, x)).toMap 222 223 println(s"[Backend] iq wake up keys: ${iqWakeUpMappedBundle.keys}") 224 225 wbFuBusyTable.io.in.intSchdBusyTable := intScheduler.io.wbFuBusyTable 226 wbFuBusyTable.io.in.fpSchdBusyTable := fpScheduler.io.wbFuBusyTable 227 wbFuBusyTable.io.in.vfSchdBusyTable := vfScheduler.io.wbFuBusyTable 228 wbFuBusyTable.io.in.memSchdBusyTable := memScheduler.io.wbFuBusyTable 229 intScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.intRespRead 230 fpScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.fpRespRead 231 vfScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.vfRespRead 232 memScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.memRespRead 233 dataPath.io.wbConfictRead := wbFuBusyTable.io.out.wbConflictRead 234 235 private val og1Cancel = dataPath.io.og1Cancel 236 private val og0Cancel = dataPath.io.og0Cancel 237 private val vlFromIntIsZero = intExuBlock.io.vlIsZero.get 238 private val vlFromIntIsVlmax = intExuBlock.io.vlIsVlmax.get 239 private val vlFromVfIsZero = vfExuBlock.io.vlIsZero.get 240 private val vlFromVfIsVlmax = vfExuBlock.io.vlIsVlmax.get 241 242 private val backendCriticalError = Wire(Bool()) 243 244 ctrlBlock.io.intIQValidNumVec := intScheduler.io.intIQValidNumVec 245 ctrlBlock.io.fpIQValidNumVec := fpScheduler.io.fpIQValidNumVec 246 ctrlBlock.io.fromTop.hartId := io.fromTop.hartId 247 ctrlBlock.io.frontend <> io.frontend 248 ctrlBlock.io.fromCSR.toDecode := intExuBlock.io.csrToDecode.get 249 ctrlBlock.io.fromWB.wbData <> wbDataPath.io.toCtrlBlock.writeback 250 ctrlBlock.io.fromMem.stIn <> io.mem.stIn 251 ctrlBlock.io.fromMem.violation <> io.mem.memoryViolation 252 ctrlBlock.io.lqCanAccept := io.mem.lqCanAccept 253 ctrlBlock.io.sqCanAccept := io.mem.sqCanAccept 254 ctrlBlock.io.csrCtrl <> intExuBlock.io.csrio.get.customCtrl 255 ctrlBlock.io.robio.csr.intrBitSet := intExuBlock.io.csrio.get.interrupt 256 ctrlBlock.io.robio.csr.trapTarget := intExuBlock.io.csrio.get.trapTarget 257 ctrlBlock.io.robio.csr.isXRet := intExuBlock.io.csrio.get.isXRet 258 ctrlBlock.io.robio.csr.wfiEvent := intExuBlock.io.csrio.get.wfi_event 259 ctrlBlock.io.robio.csr.criticalErrorState := intExuBlock.io.csrio.get.criticalErrorState 260 ctrlBlock.io.robio.lsq <> io.mem.robLsqIO 261 ctrlBlock.io.robio.lsTopdownInfo <> io.mem.lsTopdownInfo 262 ctrlBlock.io.robio.debug_ls <> io.mem.debugLS 263 ctrlBlock.io.debugEnqLsq.canAccept := io.mem.lsqEnqIO.canAccept 264 ctrlBlock.io.debugEnqLsq.resp := io.mem.lsqEnqIO.resp 265 ctrlBlock.io.debugEnqLsq.req := memScheduler.io.memIO.get.lsqEnqIO.req 266 ctrlBlock.io.debugEnqLsq.needAlloc := memScheduler.io.memIO.get.lsqEnqIO.needAlloc 267 ctrlBlock.io.debugEnqLsq.iqAccept := memScheduler.io.memIO.get.lsqEnqIO.iqAccept 268 ctrlBlock.io.fromVecExcpMod.busy := vecExcpMod.o.status.busy 269 270 intScheduler.io.fromTop.hartId := io.fromTop.hartId 271 intScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 272 intScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 273 intScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.intUops 274 intScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 275 intScheduler.io.fpWriteBack := 0.U.asTypeOf(intScheduler.io.fpWriteBack) 276 intScheduler.io.vfWriteBack := 0.U.asTypeOf(intScheduler.io.vfWriteBack) 277 intScheduler.io.v0WriteBack := 0.U.asTypeOf(intScheduler.io.v0WriteBack) 278 intScheduler.io.vlWriteBack := 0.U.asTypeOf(intScheduler.io.vlWriteBack) 279 intScheduler.io.fromDataPath.resp := dataPath.io.toIntIQ 280 intScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 281 intScheduler.io.fromDataPath.og0Cancel := og0Cancel 282 intScheduler.io.fromDataPath.og1Cancel := og1Cancel 283 intScheduler.io.ldCancel := io.mem.ldCancel 284 intScheduler.io.fromDataPath.replaceRCIdx.get := dataPath.io.toWakeupQueueRCIdx.take(params.getIntExuRCWriteSize) 285 intScheduler.io.vlWriteBackInfo.vlFromIntIsZero := false.B 286 intScheduler.io.vlWriteBackInfo.vlFromIntIsVlmax := false.B 287 intScheduler.io.vlWriteBackInfo.vlFromVfIsZero := false.B 288 intScheduler.io.vlWriteBackInfo.vlFromVfIsVlmax := false.B 289 290 fpScheduler.io.fromTop.hartId := io.fromTop.hartId 291 fpScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 292 fpScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 293 fpScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.fpUops 294 fpScheduler.io.intWriteBack := 0.U.asTypeOf(fpScheduler.io.intWriteBack) 295 fpScheduler.io.fpWriteBack := wbDataPath.io.toFpPreg 296 fpScheduler.io.vfWriteBack := 0.U.asTypeOf(fpScheduler.io.vfWriteBack) 297 fpScheduler.io.v0WriteBack := 0.U.asTypeOf(fpScheduler.io.v0WriteBack) 298 fpScheduler.io.vlWriteBack := 0.U.asTypeOf(fpScheduler.io.vlWriteBack) 299 fpScheduler.io.fromDataPath.resp := dataPath.io.toFpIQ 300 fpScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 301 fpScheduler.io.fromDataPath.og0Cancel := og0Cancel 302 fpScheduler.io.fromDataPath.og1Cancel := og1Cancel 303 fpScheduler.io.ldCancel := io.mem.ldCancel 304 fpScheduler.io.vlWriteBackInfo.vlFromIntIsZero := false.B 305 fpScheduler.io.vlWriteBackInfo.vlFromIntIsVlmax := false.B 306 fpScheduler.io.vlWriteBackInfo.vlFromVfIsZero := false.B 307 fpScheduler.io.vlWriteBackInfo.vlFromVfIsVlmax := false.B 308 309 memScheduler.io.fromTop.hartId := io.fromTop.hartId 310 memScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 311 memScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 312 memScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.memUops 313 memScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 314 memScheduler.io.fpWriteBack := wbDataPath.io.toFpPreg 315 memScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 316 memScheduler.io.v0WriteBack := wbDataPath.io.toV0Preg 317 memScheduler.io.vlWriteBack := wbDataPath.io.toVlPreg 318 memScheduler.io.fromMem.get.scommit := io.mem.sqDeq 319 memScheduler.io.fromMem.get.lcommit := io.mem.lqDeq 320 memScheduler.io.fromMem.get.wakeup := io.mem.wakeup 321 memScheduler.io.fromMem.get.sqDeqPtr := io.mem.sqDeqPtr 322 memScheduler.io.fromMem.get.lqDeqPtr := io.mem.lqDeqPtr 323 memScheduler.io.fromMem.get.sqCancelCnt := io.mem.sqCancelCnt 324 memScheduler.io.fromMem.get.lqCancelCnt := io.mem.lqCancelCnt 325 memScheduler.io.fromMem.get.stIssuePtr := io.mem.stIssuePtr 326 require(memScheduler.io.fromMem.get.memWaitUpdateReq.robIdx.length == io.mem.stIn.length) 327 memScheduler.io.fromMem.get.memWaitUpdateReq.robIdx.zip(io.mem.stIn).foreach { case (sink, source) => 328 sink.valid := source.valid 329 sink.bits := source.bits.robIdx 330 } 331 memScheduler.io.fromMem.get.memWaitUpdateReq.sqIdx := DontCare // TODO 332 memScheduler.io.fromDataPath.resp := dataPath.io.toMemIQ 333 memScheduler.io.fromMem.get.ldaFeedback := io.mem.ldaIqFeedback 334 memScheduler.io.fromMem.get.staFeedback := io.mem.staIqFeedback 335 memScheduler.io.fromMem.get.hyuFeedback := io.mem.hyuIqFeedback 336 memScheduler.io.fromMem.get.vstuFeedback := io.mem.vstuIqFeedback 337 memScheduler.io.fromMem.get.vlduFeedback := io.mem.vlduIqFeedback 338 memScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 339 memScheduler.io.fromDataPath.og0Cancel := og0Cancel 340 memScheduler.io.fromDataPath.og1Cancel := og1Cancel 341 memScheduler.io.ldCancel := io.mem.ldCancel 342 memScheduler.io.fromDataPath.replaceRCIdx.get := dataPath.io.toWakeupQueueRCIdx.takeRight(params.getMemExuRCWriteSize) 343 memScheduler.io.vlWriteBackInfo.vlFromIntIsZero := vlFromIntIsZero 344 memScheduler.io.vlWriteBackInfo.vlFromIntIsVlmax := vlFromIntIsVlmax 345 memScheduler.io.vlWriteBackInfo.vlFromVfIsZero := vlFromVfIsZero 346 memScheduler.io.vlWriteBackInfo.vlFromVfIsVlmax := vlFromVfIsVlmax 347 memScheduler.io.fromOg2Resp.get := og2ForVector.io.toMemIQOg2Resp 348 349 vfScheduler.io.fromTop.hartId := io.fromTop.hartId 350 vfScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 351 vfScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 352 vfScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.vfUops 353 vfScheduler.io.intWriteBack := 0.U.asTypeOf(vfScheduler.io.intWriteBack) 354 vfScheduler.io.fpWriteBack := 0.U.asTypeOf(vfScheduler.io.fpWriteBack) 355 vfScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 356 vfScheduler.io.v0WriteBack := wbDataPath.io.toV0Preg 357 vfScheduler.io.vlWriteBack := wbDataPath.io.toVlPreg 358 vfScheduler.io.fromDataPath.resp := dataPath.io.toVfIQ 359 vfScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 360 vfScheduler.io.fromDataPath.og0Cancel := og0Cancel 361 vfScheduler.io.fromDataPath.og1Cancel := og1Cancel 362 vfScheduler.io.ldCancel := io.mem.ldCancel 363 vfScheduler.io.vlWriteBackInfo.vlFromIntIsZero := vlFromIntIsZero 364 vfScheduler.io.vlWriteBackInfo.vlFromIntIsVlmax := vlFromIntIsVlmax 365 vfScheduler.io.vlWriteBackInfo.vlFromVfIsZero := vlFromVfIsZero 366 vfScheduler.io.vlWriteBackInfo.vlFromVfIsVlmax := vlFromVfIsVlmax 367 vfScheduler.io.fromOg2Resp.get := og2ForVector.io.toVfIQOg2Resp 368 369 dataPath.io.hartId := io.fromTop.hartId 370 dataPath.io.flush := ctrlBlock.io.toDataPath.flush 371 372 dataPath.io.fromIntIQ <> intScheduler.io.toDataPathAfterDelay 373 dataPath.io.fromFpIQ <> fpScheduler.io.toDataPathAfterDelay 374 dataPath.io.fromVfIQ <> vfScheduler.io.toDataPathAfterDelay 375 dataPath.io.fromMemIQ <> memScheduler.io.toDataPathAfterDelay 376 377 dataPath.io.ldCancel := io.mem.ldCancel 378 379 println(s"[Backend] wbDataPath.io.toIntPreg: ${wbDataPath.io.toIntPreg.size}, dataPath.io.fromIntWb: ${dataPath.io.fromIntWb.size}") 380 println(s"[Backend] wbDataPath.io.toVfPreg: ${wbDataPath.io.toVfPreg.size}, dataPath.io.fromFpWb: ${dataPath.io.fromVfWb.size}") 381 dataPath.io.fromIntWb := wbDataPath.io.toIntPreg 382 dataPath.io.fromFpWb := wbDataPath.io.toFpPreg 383 dataPath.io.fromVfWb := wbDataPath.io.toVfPreg 384 dataPath.io.fromV0Wb := wbDataPath.io.toV0Preg 385 dataPath.io.fromVlWb := wbDataPath.io.toVlPreg 386 dataPath.io.diffIntRat.foreach(_ := ctrlBlock.io.diff_int_rat.get) 387 dataPath.io.diffFpRat .foreach(_ := ctrlBlock.io.diff_fp_rat.get) 388 dataPath.io.diffVecRat.foreach(_ := ctrlBlock.io.diff_vec_rat.get) 389 dataPath.io.diffV0Rat .foreach(_ := ctrlBlock.io.diff_v0_rat.get) 390 dataPath.io.diffVlRat .foreach(_ := ctrlBlock.io.diff_vl_rat.get) 391 dataPath.io.fromBypassNetwork := bypassNetwork.io.toDataPath 392 dataPath.io.fromVecExcpMod.r := vecExcpMod.o.toVPRF.r 393 dataPath.io.fromVecExcpMod.w := vecExcpMod.o.toVPRF.w 394 395 og2ForVector.io.flush := ctrlBlock.io.toDataPath.flush 396 og2ForVector.io.ldCancel := io.mem.ldCancel 397 og2ForVector.io.fromOg1VfArith <> dataPath.io.toVecExu 398 og2ForVector.io.fromOg1VecMem.zip(dataPath.io.toMemExu.zip(params.memSchdParams.get.issueBlockParams).filter(_._2.needOg2Resp).map(_._1)) 399 .foreach { 400 case (og1Mem, datapathMem) => og1Mem <> datapathMem 401 } 402 og2ForVector.io.fromOg1ImmInfo := dataPath.io.og1ImmInfo.zip(params.allExuParams).filter(_._2.needOg2).map(_._1) 403 404 println(s"[Backend] BypassNetwork OG1 Mem Size: ${bypassNetwork.io.fromDataPath.mem.zip(params.memSchdParams.get.issueBlockParams).filterNot(_._2.needOg2Resp).size}") 405 println(s"[Backend] BypassNetwork OG2 Mem Size: ${bypassNetwork.io.fromDataPath.mem.zip(params.memSchdParams.get.issueBlockParams).filter(_._2.needOg2Resp).size}") 406 println(s"[Backend] bypassNetwork.io.fromDataPath.mem: ${bypassNetwork.io.fromDataPath.mem.size}, dataPath.io.toMemExu: ${dataPath.io.toMemExu.size}") 407 bypassNetwork.io.fromDataPath.int <> dataPath.io.toIntExu 408 bypassNetwork.io.fromDataPath.fp <> dataPath.io.toFpExu 409 bypassNetwork.io.fromDataPath.vf <> og2ForVector.io.toVfArithExu 410 bypassNetwork.io.fromDataPath.mem.lazyZip(params.memSchdParams.get.issueBlockParams).lazyZip(dataPath.io.toMemExu).filterNot(_._2.needOg2Resp) 411 .map(x => (x._1, x._3)).foreach { 412 case (bypassMem, datapathMem) => bypassMem <> datapathMem 413 } 414 bypassNetwork.io.fromDataPath.mem.zip(params.memSchdParams.get.issueBlockParams).filter(_._2.needOg2Resp).map(_._1) 415 .zip(og2ForVector.io.toVecMemExu).foreach { 416 case (bypassMem, og2Mem) => bypassMem <> og2Mem 417 } 418 bypassNetwork.io.fromDataPath.immInfo := dataPath.io.og1ImmInfo 419 bypassNetwork.io.fromDataPath.immInfo.zip(params.allExuParams).filter(_._2.needOg2).map(_._1) 420 .zip(og2ForVector.io.toBypassNetworkImmInfo).foreach { 421 case (immInfo, og2ImmInfo) => immInfo := og2ImmInfo 422 } 423 bypassNetwork.io.fromDataPath.rcData := dataPath.io.toBypassNetworkRCData 424 bypassNetwork.io.fromExus.connectExuOutput(_.int)(intExuBlock.io.out) 425 bypassNetwork.io.fromExus.connectExuOutput(_.fp)(fpExuBlock.io.out) 426 bypassNetwork.io.fromExus.connectExuOutput(_.vf)(vfExuBlock.io.out) 427 428 require(bypassNetwork.io.fromExus.mem.flatten.size == io.mem.writeBack.size, 429 s"bypassNetwork.io.fromExus.mem.flatten.size(${bypassNetwork.io.fromExus.mem.flatten.size}: ${bypassNetwork.io.fromExus.mem.map(_.size)}, " + 430 s"io.mem.writeback(${io.mem.writeBack.size})" 431 ) 432 bypassNetwork.io.fromExus.mem.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 433 sink.valid := source.valid 434 sink.bits.intWen := source.bits.uop.rfWen && source.bits.isFromLoadUnit 435 sink.bits.pdest := source.bits.uop.pdest 436 sink.bits.data := source.bits.data 437 } 438 439 440 intExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 441 for (i <- 0 until intExuBlock.io.in.length) { 442 for (j <- 0 until intExuBlock.io.in(i).length) { 443 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.int(i)(j).bits.loadDependency, io.mem.ldCancel) 444 NewPipelineConnect( 445 bypassNetwork.io.toExus.int(i)(j), intExuBlock.io.in(i)(j), intExuBlock.io.in(i)(j).fire, 446 Mux( 447 bypassNetwork.io.toExus.int(i)(j).fire, 448 bypassNetwork.io.toExus.int(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 449 intExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 450 ), 451 Option("bypassNetwork2intExuBlock") 452 ) 453 } 454 } 455 456 pcTargetMem.io.fromFrontendFtq := io.frontend.fromFtq 457 pcTargetMem.io.toDataPath <> dataPath.io.fromPcTargetMem 458 459 private val csrin = intExuBlock.io.csrin.get 460 csrin.hartId := io.fromTop.hartId 461 csrin.msiInfo.valid := RegNext(io.fromTop.msiInfo.valid) 462 csrin.msiInfo.bits := RegEnable(io.fromTop.msiInfo.bits, io.fromTop.msiInfo.valid) 463 csrin.clintTime.valid := RegNext(io.fromTop.clintTime.valid) 464 csrin.clintTime.bits := RegEnable(io.fromTop.clintTime.bits, io.fromTop.clintTime.valid) 465 csrin.trapInstInfo := ctrlBlock.io.toCSR.trapInstInfo 466 csrin.fromVecExcpMod.busy := vecExcpMod.o.status.busy 467 csrin.criticalErrorState := backendCriticalError 468 469 private val csrio = intExuBlock.io.csrio.get 470 csrio.hartId := io.fromTop.hartId 471 csrio.fpu.fflags := ctrlBlock.io.robio.csr.fflags 472 csrio.fpu.isIllegal := false.B // Todo: remove it 473 csrio.fpu.dirty_fs := ctrlBlock.io.robio.csr.dirty_fs 474 csrio.vpu <> WireDefault(0.U.asTypeOf(csrio.vpu)) // Todo 475 476 val fromIntExuVsetVType = intExuBlock.io.vtype.getOrElse(0.U.asTypeOf((Valid(new VType)))) 477 val fromVfExuVsetVType = vfExuBlock.io.vtype.getOrElse(0.U.asTypeOf((Valid(new VType)))) 478 val fromVsetVType = Mux(fromIntExuVsetVType.valid, fromIntExuVsetVType.bits, fromVfExuVsetVType.bits) 479 val vsetvlVType = RegEnable(fromVsetVType, 0.U.asTypeOf(new VType), fromIntExuVsetVType.valid || fromVfExuVsetVType.valid) 480 ctrlBlock.io.toDecode.vsetvlVType := vsetvlVType 481 482 val commitVType = ctrlBlock.io.robio.commitVType.vtype 483 val hasVsetvl = ctrlBlock.io.robio.commitVType.hasVsetvl 484 val vtype = VType.toVtypeStruct(Mux(hasVsetvl, vsetvlVType, commitVType.bits)).asUInt 485 486 // csr not store the value of vl, so when using difftest we assign the value of vl to debugVl 487 val debugVl_s0 = WireInit(UInt(VlData().dataWidth.W), 0.U) 488 val debugVl_s1 = WireInit(UInt(VlData().dataWidth.W), 0.U) 489 debugVl_s0 := dataPath.io.diffVl.getOrElse(0.U.asTypeOf(UInt(VlData().dataWidth.W))) 490 debugVl_s1 := RegNext(debugVl_s0) 491 csrio.vpu.set_vxsat := ctrlBlock.io.robio.csr.vxsat 492 csrio.vpu.set_vstart.valid := ctrlBlock.io.robio.csr.vstart.valid 493 csrio.vpu.set_vstart.bits := ctrlBlock.io.robio.csr.vstart.bits 494 ctrlBlock.io.toDecode.vstart := csrio.vpu.vstart 495 //Todo here need change design 496 csrio.vpu.set_vtype.valid := commitVType.valid 497 csrio.vpu.set_vtype.bits := ZeroExt(vtype, XLEN) 498 csrio.vpu.vl := ZeroExt(debugVl_s1, XLEN) 499 csrio.vpu.dirty_vs := ctrlBlock.io.robio.csr.dirty_vs 500 csrio.exception := ctrlBlock.io.robio.exception 501 csrio.robDeqPtr := ctrlBlock.io.robio.robDeqPtr 502 csrio.memExceptionVAddr := io.mem.exceptionAddr.vaddr 503 csrio.memExceptionGPAddr := io.mem.exceptionAddr.gpaddr 504 csrio.memExceptionIsForVSnonLeafPTE := io.mem.exceptionAddr.isForVSnonLeafPTE 505 csrio.externalInterrupt := RegNext(io.fromTop.externalInterrupt) 506 csrio.perf <> io.perf 507 csrio.perf.retiredInstr <> ctrlBlock.io.robio.csr.perfinfo.retiredInstr 508 csrio.perf.ctrlInfo <> ctrlBlock.io.perfInfo.ctrlInfo 509 private val fenceio = intExuBlock.io.fenceio.get 510 io.fenceio <> fenceio 511 512 // to fpExuBlock 513 fpExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 514 for (i <- 0 until fpExuBlock.io.in.length) { 515 for (j <- 0 until fpExuBlock.io.in(i).length) { 516 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.fp(i)(j).bits.loadDependency, io.mem.ldCancel) 517 NewPipelineConnect( 518 bypassNetwork.io.toExus.fp(i)(j), fpExuBlock.io.in(i)(j), fpExuBlock.io.in(i)(j).fire, 519 Mux( 520 bypassNetwork.io.toExus.fp(i)(j).fire, 521 bypassNetwork.io.toExus.fp(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 522 fpExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 523 ), 524 Option("bypassNetwork2fpExuBlock") 525 ) 526 } 527 } 528 529 vfExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 530 for (i <- 0 until vfExuBlock.io.in.size) { 531 for (j <- 0 until vfExuBlock.io.in(i).size) { 532 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.vf(i)(j).bits.loadDependency, io.mem.ldCancel) 533 NewPipelineConnect( 534 bypassNetwork.io.toExus.vf(i)(j), vfExuBlock.io.in(i)(j), vfExuBlock.io.in(i)(j).fire, 535 Mux( 536 bypassNetwork.io.toExus.vf(i)(j).fire, 537 bypassNetwork.io.toExus.vf(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 538 vfExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 539 ), 540 Option("bypassNetwork2vfExuBlock") 541 ) 542 543 } 544 } 545 546 intExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 547 fpExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 548 fpExuBlock.io.vxrm.foreach(_ := csrio.vpu.vxrm) 549 vfExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 550 vfExuBlock.io.vxrm.foreach(_ := csrio.vpu.vxrm) 551 552 wbDataPath.io.flush := ctrlBlock.io.redirect 553 wbDataPath.io.fromTop.hartId := io.fromTop.hartId 554 wbDataPath.io.fromIntExu <> intExuBlock.io.out 555 wbDataPath.io.fromFpExu <> fpExuBlock.io.out 556 wbDataPath.io.fromVfExu <> vfExuBlock.io.out 557 wbDataPath.io.fromMemExu.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 558 sink.valid := source.valid 559 source.ready := sink.ready 560 sink.bits.data := VecInit(Seq.fill(sink.bits.params.wbPathNum)(source.bits.data)) 561 sink.bits.pdest := source.bits.uop.pdest 562 sink.bits.robIdx := source.bits.uop.robIdx 563 sink.bits.intWen.foreach(_ := source.bits.uop.rfWen) 564 sink.bits.fpWen.foreach(_ := source.bits.uop.fpWen) 565 sink.bits.vecWen.foreach(_ := source.bits.uop.vecWen) 566 sink.bits.v0Wen.foreach(_ := source.bits.uop.v0Wen) 567 sink.bits.vlWen.foreach(_ := source.bits.uop.vlWen) 568 sink.bits.exceptionVec.foreach(_ := source.bits.uop.exceptionVec) 569 sink.bits.flushPipe.foreach(_ := source.bits.uop.flushPipe) 570 sink.bits.replay.foreach(_ := source.bits.uop.replayInst) 571 sink.bits.debug := source.bits.debug 572 sink.bits.debugInfo := source.bits.uop.debugInfo 573 sink.bits.lqIdx.foreach(_ := source.bits.uop.lqIdx) 574 sink.bits.sqIdx.foreach(_ := source.bits.uop.sqIdx) 575 sink.bits.predecodeInfo.foreach(_ := source.bits.uop.preDecodeInfo) 576 sink.bits.vls.foreach(x => { 577 x.vdIdx := source.bits.vdIdx.get 578 x.vdIdxInField := source.bits.vdIdxInField.get 579 x.vpu := source.bits.uop.vpu 580 x.oldVdPsrc := source.bits.uop.psrc(2) 581 x.isIndexed := VlduType.isIndexed(source.bits.uop.fuOpType) 582 x.isMasked := VlduType.isMasked(source.bits.uop.fuOpType) 583 x.isStrided := VlduType.isStrided(source.bits.uop.fuOpType) 584 x.isWhole := VlduType.isWhole(source.bits.uop.fuOpType) 585 x.isVecLoad := VlduType.isVecLd(source.bits.uop.fuOpType) 586 x.isVlm := VlduType.isMasked(source.bits.uop.fuOpType) && VlduType.isVecLd(source.bits.uop.fuOpType) 587 }) 588 sink.bits.trigger.foreach(_ := source.bits.uop.trigger) 589 } 590 wbDataPath.io.fromCSR.vstart := csrio.vpu.vstart 591 592 vecExcpMod.i.fromExceptionGen := ctrlBlock.io.toVecExcpMod.excpInfo 593 vecExcpMod.i.fromRab.logicPhyRegMap := ctrlBlock.io.toVecExcpMod.logicPhyRegMap 594 vecExcpMod.i.fromRat := ctrlBlock.io.toVecExcpMod.ratOldPest 595 vecExcpMod.i.fromVprf := dataPath.io.toVecExcpMod 596 597 // to mem 598 private val memIssueParams = params.memSchdParams.get.issueBlockParams 599 private val memExuBlocksHasLDU = memIssueParams.map(_.exuBlockParams.map(x => x.hasLoadFu || x.hasHyldaFu)) 600 private val memExuBlocksHasVecLoad = memIssueParams.map(_.exuBlockParams.map(x => x.hasVLoadFu)) 601 println(s"[Backend] memExuBlocksHasLDU: $memExuBlocksHasLDU") 602 println(s"[Backend] memExuBlocksHasVecLoad: $memExuBlocksHasVecLoad") 603 604 private val toMem = Wire(bypassNetwork.io.toExus.mem.cloneType) 605 for (i <- toMem.indices) { 606 for (j <- toMem(i).indices) { 607 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.mem(i)(j).bits.loadDependency, io.mem.ldCancel) 608 val needIssueTimeout = memExuBlocksHasLDU(i)(j) || memExuBlocksHasVecLoad(i)(j) 609 val issueTimeout = 610 if (needIssueTimeout) 611 Counter(0 until 16, toMem(i)(j).valid && !toMem(i)(j).fire, bypassNetwork.io.toExus.mem(i)(j).fire)._2 612 else 613 false.B 614 615 if (memScheduler.io.loadFinalIssueResp(i).nonEmpty && memExuBlocksHasLDU(i)(j)) { 616 memScheduler.io.loadFinalIssueResp(i)(j).valid := issueTimeout 617 memScheduler.io.loadFinalIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType 618 memScheduler.io.loadFinalIssueResp(i)(j).bits.resp := RespType.block 619 memScheduler.io.loadFinalIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx 620 memScheduler.io.loadFinalIssueResp(i)(j).bits.uopIdx.foreach(_ := toMem(i)(j).bits.vpu.get.vuopIdx) 621 memScheduler.io.loadFinalIssueResp(i)(j).bits.sqIdx.foreach(_ := toMem(i)(j).bits.sqIdx.get) 622 memScheduler.io.loadFinalIssueResp(i)(j).bits.lqIdx.foreach(_ := toMem(i)(j).bits.lqIdx.get) 623 } 624 625 if (memScheduler.io.vecLoadFinalIssueResp(i).nonEmpty && memExuBlocksHasVecLoad(i)(j)) { 626 memScheduler.io.vecLoadFinalIssueResp(i)(j).valid := issueTimeout 627 memScheduler.io.vecLoadFinalIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType 628 memScheduler.io.vecLoadFinalIssueResp(i)(j).bits.resp := RespType.block 629 memScheduler.io.vecLoadFinalIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx 630 memScheduler.io.vecLoadFinalIssueResp(i)(j).bits.uopIdx.foreach(_ := toMem(i)(j).bits.vpu.get.vuopIdx) 631 memScheduler.io.vecLoadFinalIssueResp(i)(j).bits.sqIdx.foreach(_ := toMem(i)(j).bits.sqIdx.get) 632 memScheduler.io.vecLoadFinalIssueResp(i)(j).bits.lqIdx.foreach(_ := toMem(i)(j).bits.lqIdx.get) 633 } 634 635 NewPipelineConnect( 636 bypassNetwork.io.toExus.mem(i)(j), toMem(i)(j), toMem(i)(j).fire, 637 Mux( 638 bypassNetwork.io.toExus.mem(i)(j).fire, 639 bypassNetwork.io.toExus.mem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 640 toMem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || issueTimeout 641 ), 642 Option("bypassNetwork2toMemExus") 643 ) 644 645 if (memScheduler.io.memAddrIssueResp(i).nonEmpty && memExuBlocksHasLDU(i)(j)) { 646 memScheduler.io.memAddrIssueResp(i)(j).valid := toMem(i)(j).fire && FuType.isLoad(toMem(i)(j).bits.fuType) 647 memScheduler.io.memAddrIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType 648 memScheduler.io.memAddrIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx 649 memScheduler.io.memAddrIssueResp(i)(j).bits.sqIdx.foreach(_ := toMem(i)(j).bits.sqIdx.get) 650 memScheduler.io.memAddrIssueResp(i)(j).bits.lqIdx.foreach(_ := toMem(i)(j).bits.lqIdx.get) 651 memScheduler.io.memAddrIssueResp(i)(j).bits.resp := RespType.success // for load inst, firing at toMem means issuing successfully 652 } 653 654 if (memScheduler.io.vecLoadIssueResp(i).nonEmpty && memExuBlocksHasVecLoad(i)(j)) { 655 memScheduler.io.vecLoadIssueResp(i)(j) match { 656 case resp => 657 resp.valid := toMem(i)(j).fire && VlduType.isVecLd(toMem(i)(j).bits.fuOpType) 658 resp.bits.fuType := toMem(i)(j).bits.fuType 659 resp.bits.robIdx := toMem(i)(j).bits.robIdx 660 resp.bits.uopIdx.get := toMem(i)(j).bits.vpu.get.vuopIdx 661 resp.bits.sqIdx.get := toMem(i)(j).bits.sqIdx.get 662 resp.bits.lqIdx.get := toMem(i)(j).bits.lqIdx.get 663 resp.bits.resp := RespType.success 664 } 665 if (backendParams.debugEn){ 666 dontTouch(memScheduler.io.vecLoadIssueResp(i)(j)) 667 } 668 } 669 } 670 } 671 672 io.mem.redirect := ctrlBlock.io.redirect 673 io.mem.issueUops.zip(toMem.flatten).foreach { case (sink, source) => 674 val enableMdp = Constantin.createRecord("EnableMdp", true) 675 sink.valid := source.valid 676 source.ready := sink.ready 677 sink.bits.iqIdx := source.bits.iqIdx 678 sink.bits.isFirstIssue := source.bits.isFirstIssue 679 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 680 sink.bits.src := 0.U.asTypeOf(sink.bits.src) 681 sink.bits.src.zip(source.bits.src).foreach { case (l, r) => l := r} 682 sink.bits.uop.fuType := source.bits.fuType 683 sink.bits.uop.fuOpType := source.bits.fuOpType 684 sink.bits.uop.imm := source.bits.imm 685 sink.bits.uop.robIdx := source.bits.robIdx 686 sink.bits.uop.pdest := source.bits.pdest 687 sink.bits.uop.rfWen := source.bits.rfWen.getOrElse(false.B) 688 sink.bits.uop.fpWen := source.bits.fpWen.getOrElse(false.B) 689 sink.bits.uop.vecWen := source.bits.vecWen.getOrElse(false.B) 690 sink.bits.uop.v0Wen := source.bits.v0Wen.getOrElse(false.B) 691 sink.bits.uop.vlWen := source.bits.vlWen.getOrElse(false.B) 692 sink.bits.uop.flushPipe := source.bits.flushPipe.getOrElse(false.B) 693 sink.bits.uop.pc := source.bits.pc.getOrElse(0.U) 694 sink.bits.uop.loadWaitBit := Mux(enableMdp, source.bits.loadWaitBit.getOrElse(false.B), false.B) 695 sink.bits.uop.waitForRobIdx := Mux(enableMdp, source.bits.waitForRobIdx.getOrElse(0.U.asTypeOf(new RobPtr)), 0.U.asTypeOf(new RobPtr)) 696 sink.bits.uop.storeSetHit := Mux(enableMdp, source.bits.storeSetHit.getOrElse(false.B), false.B) 697 sink.bits.uop.loadWaitStrict := Mux(enableMdp, source.bits.loadWaitStrict.getOrElse(false.B), false.B) 698 sink.bits.uop.ssid := Mux(enableMdp, source.bits.ssid.getOrElse(0.U(SSIDWidth.W)), 0.U(SSIDWidth.W)) 699 sink.bits.uop.lqIdx := source.bits.lqIdx.getOrElse(0.U.asTypeOf(new LqPtr)) 700 sink.bits.uop.sqIdx := source.bits.sqIdx.getOrElse(0.U.asTypeOf(new SqPtr)) 701 sink.bits.uop.ftqPtr := source.bits.ftqIdx.getOrElse(0.U.asTypeOf(new FtqPtr)) 702 sink.bits.uop.ftqOffset := source.bits.ftqOffset.getOrElse(0.U) 703 sink.bits.uop.debugInfo := source.bits.perfDebugInfo 704 sink.bits.uop.vpu := source.bits.vpu.getOrElse(0.U.asTypeOf(new VPUCtrlSignals)) 705 sink.bits.uop.preDecodeInfo := source.bits.preDecode.getOrElse(0.U.asTypeOf(new PreDecodeInfo)) 706 sink.bits.uop.numLsElem := source.bits.numLsElem.getOrElse(0.U) // Todo: remove this bundle, keep only the one below 707 sink.bits.flowNum.foreach(_ := source.bits.numLsElem.get) 708 } 709 io.mem.loadFastMatch := memScheduler.io.toMem.get.loadFastMatch.map(_.fastMatch) 710 io.mem.loadFastImm := memScheduler.io.toMem.get.loadFastMatch.map(_.fastImm) 711 io.mem.tlbCsr := csrio.tlb 712 io.mem.csrCtrl := csrio.customCtrl 713 io.mem.sfence := fenceio.sfence 714 io.mem.isStoreException := CommitType.lsInstIsStore(ctrlBlock.io.robio.exception.bits.commitType) 715 io.mem.isVlsException := ctrlBlock.io.robio.exception.bits.vls 716 require(io.mem.loadPcRead.size == params.LduCnt) 717 io.mem.loadPcRead.zipWithIndex.foreach { case (loadPcRead, i) => 718 loadPcRead := ctrlBlock.io.memLdPcRead(i).data 719 ctrlBlock.io.memLdPcRead(i).valid := io.mem.issueLda(i).valid 720 ctrlBlock.io.memLdPcRead(i).ptr := io.mem.issueLda(i).bits.uop.ftqPtr 721 ctrlBlock.io.memLdPcRead(i).offset := io.mem.issueLda(i).bits.uop.ftqOffset 722 } 723 724 io.mem.storePcRead.zipWithIndex.foreach { case (storePcRead, i) => 725 storePcRead := ctrlBlock.io.memStPcRead(i).data 726 ctrlBlock.io.memStPcRead(i).valid := io.mem.issueSta(i).valid 727 ctrlBlock.io.memStPcRead(i).ptr := io.mem.issueSta(i).bits.uop.ftqPtr 728 ctrlBlock.io.memStPcRead(i).offset := io.mem.issueSta(i).bits.uop.ftqOffset 729 } 730 731 io.mem.hyuPcRead.zipWithIndex.foreach( { case (hyuPcRead, i) => 732 hyuPcRead := ctrlBlock.io.memHyPcRead(i).data 733 ctrlBlock.io.memHyPcRead(i).valid := io.mem.issueHylda(i).valid 734 ctrlBlock.io.memHyPcRead(i).ptr := io.mem.issueHylda(i).bits.uop.ftqPtr 735 ctrlBlock.io.memHyPcRead(i).offset := io.mem.issueHylda(i).bits.uop.ftqOffset 736 }) 737 738 ctrlBlock.io.robio.robHeadLsIssue := io.mem.issueUops.map(deq => deq.fire && deq.bits.uop.robIdx === ctrlBlock.io.robio.robDeqPtr).reduce(_ || _) 739 740 // mem io 741 io.mem.lsqEnqIO <> memScheduler.io.memIO.get.lsqEnqIO 742 io.mem.robLsqIO <> ctrlBlock.io.robio.lsq 743 io.mem.storeDebugInfo <> ctrlBlock.io.robio.storeDebugInfo 744 745 io.frontendSfence := fenceio.sfence 746 io.frontendTlbCsr := csrio.tlb 747 io.frontendCsrCtrl := csrio.customCtrl 748 749 io.tlb <> csrio.tlb 750 751 io.csrCustomCtrl := csrio.customCtrl 752 753 io.toTop.cpuHalted := ctrlBlock.io.toTop.cpuHalt 754 755 io.debugTopDown.fromRob := ctrlBlock.io.debugTopDown.fromRob 756 ctrlBlock.io.debugTopDown.fromCore := io.debugTopDown.fromCore 757 758 io.debugRolling := ctrlBlock.io.debugRolling 759 760 if(backendParams.debugEn) { 761 dontTouch(memScheduler.io) 762 dontTouch(dataPath.io.toMemExu) 763 dontTouch(wbDataPath.io.fromMemExu) 764 } 765 766 // reset tree 767 if (p(DebugOptionsKey).ResetGen) { 768 val rightResetTree = ResetGenNode(Seq( 769 ModuleNode(dataPath), 770 ModuleNode(intExuBlock), 771 ModuleNode(fpExuBlock), 772 ModuleNode(vfExuBlock), 773 ModuleNode(bypassNetwork), 774 ModuleNode(wbDataPath) 775 )) 776 val leftResetTree = ResetGenNode(Seq( 777 ModuleNode(pcTargetMem), 778 ModuleNode(intScheduler), 779 ModuleNode(fpScheduler), 780 ModuleNode(vfScheduler), 781 ModuleNode(memScheduler), 782 ModuleNode(og2ForVector), 783 ModuleNode(wbFuBusyTable), 784 ResetGenNode(Seq( 785 ModuleNode(ctrlBlock), 786 // ResetGenNode(Seq( 787 CellNode(io.frontendReset) 788 // )) 789 )) 790 )) 791 ResetGen(leftResetTree, reset, sim = false) 792 ResetGen(rightResetTree, reset, sim = false) 793 } else { 794 io.frontendReset := DontCare 795 } 796 797 // perf events 798 val pfevent = Module(new PFEvent) 799 pfevent.io.distribute_csr := RegNext(csrio.customCtrl.distribute_csr) 800 val csrevents = pfevent.io.hpmevent.slice(8,16) 801 802 val ctrlBlockPerf = ctrlBlock.getPerfEvents 803 val intSchedulerPerf = intScheduler.asInstanceOf[SchedulerArithImp].getPerfEvents 804 val fpSchedulerPerf = fpScheduler.asInstanceOf[SchedulerArithImp].getPerfEvents 805 val vecSchedulerPerf = vfScheduler.asInstanceOf[SchedulerArithImp].getPerfEvents 806 val memSchedulerPerf = memScheduler.asInstanceOf[SchedulerMemImp].getPerfEvents 807 808 val perfBackend = Seq() 809 // let index = 0 be no event 810 val allPerfEvents = Seq(("noEvent", 0.U)) ++ ctrlBlockPerf ++ intSchedulerPerf ++ fpSchedulerPerf ++ vecSchedulerPerf ++ memSchedulerPerf ++ perfBackend 811 812 813 if (printEventCoding) { 814 for (((name, inc), i) <- allPerfEvents.zipWithIndex) { 815 println("backend perfEvents Set", name, inc, i) 816 } 817 } 818 819 val allPerfInc = allPerfEvents.map(_._2.asTypeOf(new PerfEvent)) 820 val perfEvents = HPerfMonitor(csrevents, allPerfInc).getPerfEvents 821 csrio.perf.perfEventsBackend := VecInit(perfEvents.map(_._2.asTypeOf(new PerfEvent))) 822 823 val ctrlBlockError = ctrlBlock.getCriticalErrors 824 val intExuBlockError = intExuBlock.getCriticalErrors 825 val criticalErrors = ctrlBlockError ++ intExuBlockError 826 827 if (printCriticalError) { 828 for (((name, error), _) <- criticalErrors.zipWithIndex) { 829 XSError(error, s"critical error: $name \n") 830 } 831 } 832 833 // expand to collect frontend/memblock/L2 critical errors 834 backendCriticalError := criticalErrors.map(_._2).reduce(_ || _) 835 836 io.toTop.cpuCriticalError := csrio.criticalErrorState 837} 838 839class BackendMemIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 840 // Since fast load replay always use load unit 0, Backend flips two load port to avoid conflicts 841 val flippedLda = true 842 // params alias 843 private val LoadQueueSize = VirtualLoadQueueSize 844 // In/Out // Todo: split it into one-direction bundle 845 val lsqEnqIO = Flipped(new LsqEnqIO) 846 val robLsqIO = new RobLsqIO 847 val ldaIqFeedback = Vec(params.LduCnt, Flipped(new MemRSFeedbackIO)) 848 val staIqFeedback = Vec(params.StaCnt, Flipped(new MemRSFeedbackIO)) 849 val hyuIqFeedback = Vec(params.HyuCnt, Flipped(new MemRSFeedbackIO)) 850 val vstuIqFeedback = Flipped(Vec(params.VstuCnt, new MemRSFeedbackIO(isVector = true))) 851 val vlduIqFeedback = Flipped(Vec(params.VlduCnt, new MemRSFeedbackIO(isVector = true))) 852 val ldCancel = Vec(params.LdExuCnt, Input(new LoadCancelIO)) 853 val wakeup = Vec(params.LdExuCnt, Flipped(Valid(new DynInst))) 854 val loadPcRead = Vec(params.LduCnt, Output(UInt(VAddrBits.W))) 855 val storePcRead = Vec(params.StaCnt, Output(UInt(VAddrBits.W))) 856 val hyuPcRead = Vec(params.HyuCnt, Output(UInt(VAddrBits.W))) 857 // Input 858 val writebackLda = Vec(params.LduCnt, Flipped(DecoupledIO(new MemExuOutput))) 859 val writebackSta = Vec(params.StaCnt, Flipped(DecoupledIO(new MemExuOutput))) 860 val writebackStd = Vec(params.StdCnt, Flipped(DecoupledIO(new MemExuOutput))) 861 val writebackHyuLda = Vec(params.HyuCnt, Flipped(DecoupledIO(new MemExuOutput))) 862 val writebackHyuSta = Vec(params.HyuCnt, Flipped(DecoupledIO(new MemExuOutput))) 863 val writebackVldu = Vec(params.VlduCnt, Flipped(DecoupledIO(new MemExuOutput(true)))) 864 865 val s3_delayed_load_error = Input(Vec(LoadPipelineWidth, Bool())) 866 val stIn = Input(Vec(params.StaExuCnt, ValidIO(new DynInst()))) 867 val memoryViolation = Flipped(ValidIO(new Redirect)) 868 val exceptionAddr = Input(new Bundle { 869 val vaddr = UInt(XLEN.W) 870 val gpaddr = UInt(XLEN.W) 871 val isForVSnonLeafPTE = Bool() 872 }) 873 val sqDeq = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) 874 val lqDeq = Input(UInt(log2Up(CommitWidth + 1).W)) 875 val sqDeqPtr = Input(new SqPtr) 876 val lqDeqPtr = Input(new LqPtr) 877 878 val lqCancelCnt = Input(UInt(log2Up(VirtualLoadQueueSize + 1).W)) 879 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 880 881 val lqCanAccept = Input(Bool()) 882 val sqCanAccept = Input(Bool()) 883 884 val otherFastWakeup = Flipped(Vec(params.LduCnt + params.HyuCnt, ValidIO(new DynInst))) 885 val stIssuePtr = Input(new SqPtr()) 886 887 val debugLS = Flipped(Output(new DebugLSIO)) 888 889 val lsTopdownInfo = Vec(params.LduCnt + params.HyuCnt, Flipped(Output(new LsTopdownInfo))) 890 // Output 891 val redirect = ValidIO(new Redirect) // rob flush MemBlock 892 val issueLda = MixedVec(Seq.fill(params.LduCnt)(DecoupledIO(new MemExuInput()))) 893 val issueSta = MixedVec(Seq.fill(params.StaCnt)(DecoupledIO(new MemExuInput()))) 894 val issueStd = MixedVec(Seq.fill(params.StdCnt)(DecoupledIO(new MemExuInput()))) 895 val issueHylda = MixedVec(Seq.fill(params.HyuCnt)(DecoupledIO(new MemExuInput()))) 896 val issueHysta = MixedVec(Seq.fill(params.HyuCnt)(DecoupledIO(new MemExuInput()))) 897 val issueVldu = MixedVec(Seq.fill(params.VlduCnt)(DecoupledIO(new MemExuInput(true)))) 898 899 val loadFastMatch = Vec(params.LduCnt, Output(UInt(params.LduCnt.W))) 900 val loadFastImm = Vec(params.LduCnt, Output(UInt(12.W))) // Imm_I 901 902 val tlbCsr = Output(new TlbCsrBundle) 903 val csrCtrl = Output(new CustomCSRCtrlIO) 904 val sfence = Output(new SfenceBundle) 905 val isStoreException = Output(Bool()) 906 val isVlsException = Output(Bool()) 907 908 // ATTENTION: The issue ports' sequence order should be the same as IQs' deq config 909 private [backend] def issueUops: Seq[DecoupledIO[MemExuInput]] = { 910 issueSta ++ 911 issueHylda ++ issueHysta ++ 912 issueLda ++ 913 issueVldu ++ 914 issueStd 915 }.toSeq 916 917 // ATTENTION: The writeback ports' sequence order should be the same as IQs' deq config 918 private [backend] def writeBack: Seq[DecoupledIO[MemExuOutput]] = { 919 writebackSta ++ 920 writebackHyuLda ++ writebackHyuSta ++ 921 writebackLda ++ 922 writebackVldu ++ 923 writebackStd 924 } 925 926 // store event difftest information 927 val storeDebugInfo = Vec(EnsbufferWidth, new Bundle { 928 val robidx = Input(new RobPtr) 929 val pc = Output(UInt(VAddrBits.W)) 930 }) 931} 932 933class TopToBackendBundle(implicit p: Parameters) extends XSBundle { 934 val hartId = Output(UInt(hartIdLen.W)) 935 val externalInterrupt = Output(new ExternalInterruptIO) 936 val msiInfo = Output(ValidIO(new MsiInfoBundle)) 937 val clintTime = Output(ValidIO(UInt(64.W))) 938} 939 940class BackendToTopBundle extends Bundle { 941 val cpuHalted = Output(Bool()) 942 val cpuCriticalError = Output(Bool()) 943} 944 945class BackendIO(implicit p: Parameters, params: BackendParams) extends XSBundle with HasSoCParameter { 946 val fromTop = Flipped(new TopToBackendBundle) 947 948 val toTop = new BackendToTopBundle 949 950 val fenceio = new FenceIO 951 // Todo: merge these bundles into BackendFrontendIO 952 val frontend = Flipped(new FrontendToCtrlIO) 953 val frontendSfence = Output(new SfenceBundle) 954 val frontendCsrCtrl = Output(new CustomCSRCtrlIO) 955 val frontendTlbCsr = Output(new TlbCsrBundle) 956 val frontendReset = Output(Reset()) 957 958 val mem = new BackendMemIO 959 960 val perf = Input(new PerfCounterIO) 961 962 val tlb = Output(new TlbCsrBundle) 963 964 val csrCustomCtrl = Output(new CustomCSRCtrlIO) 965 966 val debugTopDown = new Bundle { 967 val fromRob = new RobCoreTopDownIO 968 val fromCore = new CoreDispatchTopDownIO 969 } 970 val debugRolling = new RobDebugRollingIO 971} 972