1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15* 16* 17* Acknowledgement 18* 19* This implementation is inspired by several key papers: 20* [1] Robert. M. Tomasulo. "[An efficient algorithm for exploiting multiple arithmetic units.] 21* (https://doi.org/10.1147/rd.111.0025)" IBM Journal of Research and Development (IBMJ) 11.1: 25-33. 1967. 22***************************************************************************************/ 23 24package xiangshan.backend 25 26import org.chipsalliance.cde.config.Parameters 27import chisel3._ 28import chisel3.util._ 29import device.MsiInfoBundle 30import difftest._ 31import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 32import system.HasSoCParameter 33import utility._ 34import xiangshan._ 35import xiangshan.backend.Bundles.{DynInst, IssueQueueIQWakeUpBundle, LoadShouldCancel, MemExuInput, MemExuOutput, VPUCtrlSignals} 36import xiangshan.backend.ctrlblock.{DebugLSIO, LsTopdownInfo} 37import xiangshan.backend.datapath.DataConfig.{IntData, VecData, FpData} 38import xiangshan.backend.datapath.RdConfig.{IntRD, VfRD} 39import xiangshan.backend.datapath.WbConfig._ 40import xiangshan.backend.datapath.DataConfig._ 41import xiangshan.backend.datapath._ 42import xiangshan.backend.dispatch.CoreDispatchTopDownIO 43import xiangshan.backend.exu.ExuBlock 44import xiangshan.backend.fu.vector.Bundles.{VConfig, VType} 45import xiangshan.backend.fu.{FenceIO, FenceToSbuffer, FuConfig, FuType, PFEvent, PerfCounterIO} 46import xiangshan.backend.issue.EntryBundles._ 47import xiangshan.backend.issue.{Scheduler, SchedulerArithImp, SchedulerImpBase, SchedulerMemImp} 48import xiangshan.backend.rob.{RobCoreTopDownIO, RobDebugRollingIO, RobLsqIO, RobPtr} 49import xiangshan.backend.trace.TraceCoreInterface 50import xiangshan.frontend.{FtqPtr, FtqRead, PreDecodeInfo} 51import xiangshan.mem.{LqPtr, LsqEnqIO, SqPtr} 52 53import scala.collection.mutable 54 55class Backend(val params: BackendParams)(implicit p: Parameters) extends LazyModule 56 with HasXSParameter { 57 override def shouldBeInlined: Boolean = false 58 val inner = LazyModule(new BackendInlined(params)) 59 lazy val module = new BackendImp(this) 60} 61 62class BackendImp(wrapper: Backend)(implicit p: Parameters) extends LazyModuleImp(wrapper) { 63 val io = IO(new BackendIO()(p, wrapper.params)) 64 io <> wrapper.inner.module.io 65 if (p(DebugOptionsKey).ResetGen) { 66 ResetGen(ResetGenNode(Seq(ModuleNode(wrapper.inner.module))), reset, sim = false) 67 } 68} 69 70class BackendInlined(val params: BackendParams)(implicit p: Parameters) extends LazyModule 71 with HasXSParameter { 72 73 override def shouldBeInlined: Boolean = true 74 75 // check read & write port config 76 params.configChecks 77 78 /* Only update the idx in mem-scheduler here 79 * Idx in other schedulers can be updated the same way if needed 80 * 81 * Also note that we filter out the 'stData issue-queues' when counting 82 */ 83 for ((ibp, idx) <- params.memSchdParams.get.issueBlockParams.filter(iq => iq.StdCnt == 0).zipWithIndex) { 84 ibp.updateIdx(idx) 85 } 86 87 println(params.iqWakeUpParams) 88 89 for ((schdCfg, i) <- params.allSchdParams.zipWithIndex) { 90 schdCfg.bindBackendParam(params) 91 } 92 93 for ((iqCfg, i) <- params.allIssueParams.zipWithIndex) { 94 iqCfg.bindBackendParam(params) 95 } 96 97 for ((exuCfg, i) <- params.allExuParams.zipWithIndex) { 98 exuCfg.bindBackendParam(params) 99 exuCfg.updateIQWakeUpConfigs(params.iqWakeUpParams) 100 exuCfg.updateExuIdx(i) 101 } 102 103 println("[Backend] ExuConfigs:") 104 for (exuCfg <- params.allExuParams) { 105 val fuConfigs = exuCfg.fuConfigs 106 val wbPortConfigs = exuCfg.wbPortConfigs 107 val immType = exuCfg.immType 108 109 println("[Backend] " + 110 s"${exuCfg.name}: " + 111 (if (exuCfg.fakeUnit) "fake, " else "") + 112 (if (exuCfg.hasLoadFu || exuCfg.hasHyldaFu) s"LdExuIdx(${backendParams.getLdExuIdx(exuCfg)})" else "") + 113 s"${fuConfigs.map(_.name).mkString("fu(s): {", ",", "}")}, " + 114 s"${wbPortConfigs.mkString("wb: {", ",", "}")}, " + 115 s"${immType.map(SelImm.mkString(_)).mkString("imm: {", ",", "}")}, " + 116 s"latMax(${exuCfg.latencyValMax}), ${exuCfg.fuLatancySet.mkString("lat: {", ",", "}")}, " + 117 s"srcReg(${exuCfg.numRegSrc})" 118 ) 119 require( 120 wbPortConfigs.collectFirst { case x: IntWB => x }.nonEmpty == 121 fuConfigs.map(_.writeIntRf).reduce(_ || _), 122 s"${exuCfg.name} int wb port has no priority" 123 ) 124 require( 125 wbPortConfigs.collectFirst { case x: FpWB => x }.nonEmpty == 126 fuConfigs.map(x => x.writeFpRf).reduce(_ || _), 127 s"${exuCfg.name} fp wb port has no priority" 128 ) 129 require( 130 wbPortConfigs.collectFirst { case x: VfWB => x }.nonEmpty == 131 fuConfigs.map(x => x.writeVecRf).reduce(_ || _), 132 s"${exuCfg.name} vec wb port has no priority" 133 ) 134 } 135 136 println(s"[Backend] all fu configs") 137 for (cfg <- FuConfig.allConfigs) { 138 println(s"[Backend] $cfg") 139 } 140 141 println(s"[Backend] Int RdConfigs: ExuName(Priority)") 142 for ((port, seq) <- params.getRdPortParams(IntData())) { 143 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 144 } 145 146 println(s"[Backend] Int WbConfigs: ExuName(Priority)") 147 for ((port, seq) <- params.getWbPortParams(IntData())) { 148 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 149 } 150 151 println(s"[Backend] Fp RdConfigs: ExuName(Priority)") 152 for ((port, seq) <- params.getRdPortParams(FpData())) { 153 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 154 } 155 156 println(s"[Backend] Fp WbConfigs: ExuName(Priority)") 157 for ((port, seq) <- params.getWbPortParams(FpData())) { 158 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 159 } 160 161 println(s"[Backend] Vf RdConfigs: ExuName(Priority)") 162 for ((port, seq) <- params.getRdPortParams(VecData())) { 163 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 164 } 165 166 println(s"[Backend] Vf WbConfigs: ExuName(Priority)") 167 for ((port, seq) <- params.getWbPortParams(VecData())) { 168 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 169 } 170 171 println(s"[Backend] Dispatch Configs:") 172 println(s"[Backend] Load IQ enq width(${params.numLoadDp}), Store IQ enq width(${params.numStoreDp})") 173 println(s"[Backend] Load DP width(${LSQLdEnqWidth}), Store DP width(${LSQStEnqWidth})") 174 175 params.updateCopyPdestInfo 176 println(s"[Backend] copyPdestInfo ${params.copyPdestInfo}") 177 params.allExuParams.map(_.copyNum) 178 val ctrlBlock = LazyModule(new CtrlBlock(params)) 179 val intScheduler = params.intSchdParams.map(x => LazyModule(new Scheduler(x))) 180 val fpScheduler = params.fpSchdParams.map(x => LazyModule(new Scheduler(x))) 181 val vfScheduler = params.vfSchdParams.map(x => LazyModule(new Scheduler(x))) 182 val memScheduler = params.memSchdParams.map(x => LazyModule(new Scheduler(x))) 183 val dataPath = LazyModule(new DataPath(params)) 184 val intExuBlock = params.intSchdParams.map(x => LazyModule(new ExuBlock(x))) 185 val fpExuBlock = params.fpSchdParams.map(x => LazyModule(new ExuBlock(x))) 186 val vfExuBlock = params.vfSchdParams.map(x => LazyModule(new ExuBlock(x))) 187 val wbFuBusyTable = LazyModule(new WbFuBusyTable(params)) 188 189 lazy val module = new BackendInlinedImp(this) 190} 191 192class BackendInlinedImp(override val wrapper: BackendInlined)(implicit p: Parameters) extends LazyModuleImp(wrapper) 193 with HasXSParameter 194 with HasPerfEvents 195 with HasCriticalErrors { 196 implicit private val params: BackendParams = wrapper.params 197 198 val io = IO(new BackendIO()(p, wrapper.params)) 199 200 private val ctrlBlock = wrapper.ctrlBlock.module 201 private val intScheduler: SchedulerImpBase = wrapper.intScheduler.get.module 202 private val fpScheduler = wrapper.fpScheduler.get.module 203 private val vfScheduler = wrapper.vfScheduler.get.module 204 private val memScheduler = wrapper.memScheduler.get.module 205 private val dataPath = wrapper.dataPath.module 206 private val intExuBlock = wrapper.intExuBlock.get.module 207 private val fpExuBlock = wrapper.fpExuBlock.get.module 208 private val vfExuBlock = wrapper.vfExuBlock.get.module 209 private val og2ForVector = Module(new Og2ForVector(params)) 210 private val bypassNetwork = Module(new BypassNetwork) 211 private val wbDataPath = Module(new WbDataPath(params)) 212 private val wbFuBusyTable = wrapper.wbFuBusyTable.module 213 private val vecExcpMod = Module(new VecExcpDataMergeModule) 214 215 private val iqWakeUpMappedBundle: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = ( 216 intScheduler.io.toSchedulers.wakeupVec ++ 217 fpScheduler.io.toSchedulers.wakeupVec ++ 218 vfScheduler.io.toSchedulers.wakeupVec ++ 219 memScheduler.io.toSchedulers.wakeupVec 220 ).map(x => (x.bits.exuIdx, x)).toMap 221 222 private val iqWakeUpMappedBundleDelayed: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = ( 223 intScheduler.io.toSchedulers.wakeupVec ++ 224 fpScheduler.io.toSchedulers.wakeupVec ++ 225 vfScheduler.io.toSchedulers.wakeupVec ++ 226 memScheduler.io.toSchedulers.wakeupVec 227 ).map{ case x => 228 val delayed = Wire(chiselTypeOf(x)) 229 // TODO: add clock gate use Wen, remove issuequeue wakeupToIQ logic Wen = Wen && valid 230 delayed := RegNext(x) 231 (x.bits.exuIdx, delayed) 232 }.toMap 233 234 println(s"[Backend] iq wake up keys: ${iqWakeUpMappedBundle.keys}") 235 236 wbFuBusyTable.io.in.intSchdBusyTable := intScheduler.io.wbFuBusyTable 237 wbFuBusyTable.io.in.fpSchdBusyTable := fpScheduler.io.wbFuBusyTable 238 wbFuBusyTable.io.in.vfSchdBusyTable := vfScheduler.io.wbFuBusyTable 239 wbFuBusyTable.io.in.memSchdBusyTable := memScheduler.io.wbFuBusyTable 240 intScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.intRespRead 241 fpScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.fpRespRead 242 vfScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.vfRespRead 243 memScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.memRespRead 244 dataPath.io.wbConfictRead := wbFuBusyTable.io.out.wbConflictRead 245 246 private val og1Cancel = dataPath.io.og1Cancel 247 private val og0Cancel = dataPath.io.og0Cancel 248 private val vlFromIntIsZero = intExuBlock.io.vlIsZero.get 249 private val vlFromIntIsVlmax = intExuBlock.io.vlIsVlmax.get 250 private val vlFromVfIsZero = vfExuBlock.io.vlIsZero.get 251 private val vlFromVfIsVlmax = vfExuBlock.io.vlIsVlmax.get 252 253 private val backendCriticalError = Wire(Bool()) 254 255 ctrlBlock.io.fromTop.hartId := io.fromTop.hartId 256 ctrlBlock.io.frontend <> io.frontend 257 ctrlBlock.io.fromCSR.toDecode := intExuBlock.io.csrToDecode.get 258 ctrlBlock.io.fromCSR.traceCSR := intExuBlock.io.csrio.get.traceCSR 259 ctrlBlock.io.fromCSR.instrAddrTransType := RegNext(intExuBlock.io.csrio.get.instrAddrTransType) 260 ctrlBlock.io.fromWB.wbData <> wbDataPath.io.toCtrlBlock.writeback 261 ctrlBlock.io.fromMem.stIn <> io.mem.stIn 262 ctrlBlock.io.fromMem.violation <> io.mem.memoryViolation 263 ctrlBlock.io.lqCanAccept := io.mem.lqCanAccept 264 ctrlBlock.io.sqCanAccept := io.mem.sqCanAccept 265 266 io.mem.lsqEnqIO <> ctrlBlock.io.toMem.lsqEnqIO 267 ctrlBlock.io.fromMemToDispatch.scommit := io.mem.sqDeq 268 ctrlBlock.io.fromMemToDispatch.lcommit := io.mem.lqDeq 269 ctrlBlock.io.fromMemToDispatch.sqDeqPtr := io.mem.sqDeqPtr 270 ctrlBlock.io.fromMemToDispatch.lqDeqPtr := io.mem.lqDeqPtr 271 ctrlBlock.io.fromMemToDispatch.sqCancelCnt := io.mem.sqCancelCnt 272 ctrlBlock.io.fromMemToDispatch.lqCancelCnt := io.mem.lqCancelCnt 273 ctrlBlock.io.toDispatch.wakeUpInt := intScheduler.io.toSchedulers.wakeupVec 274 ctrlBlock.io.toDispatch.wakeUpFp := fpScheduler.io.toSchedulers.wakeupVec 275 ctrlBlock.io.toDispatch.wakeUpVec := vfScheduler.io.toSchedulers.wakeupVec 276 ctrlBlock.io.toDispatch.wakeUpMem := memScheduler.io.toSchedulers.wakeupVec 277 ctrlBlock.io.toDispatch.IQValidNumVec := intScheduler.io.IQValidNumVec ++ fpScheduler.io.IQValidNumVec ++ vfScheduler.io.IQValidNumVec ++ memScheduler.io.IQValidNumVec 278 ctrlBlock.io.toDispatch.ldCancel := io.mem.ldCancel 279 ctrlBlock.io.toDispatch.og0Cancel := og0Cancel 280 ctrlBlock.io.toDispatch.wbPregsInt.zip(wbDataPath.io.toIntPreg).map(x => { 281 x._1.valid := x._2.wen && x._2.intWen 282 x._1.bits := x._2.addr 283 }) 284 ctrlBlock.io.toDispatch.wbPregsFp.zip(wbDataPath.io.toFpPreg).map(x => { 285 x._1.valid := x._2.wen && x._2.fpWen 286 x._1.bits := x._2.addr 287 }) 288 ctrlBlock.io.toDispatch.wbPregsVec.zip(wbDataPath.io.toVfPreg).map(x => { 289 x._1.valid := x._2.wen && x._2.vecWen 290 x._1.bits := x._2.addr 291 }) 292 ctrlBlock.io.toDispatch.wbPregsV0.zip(wbDataPath.io.toV0Preg).map(x => { 293 x._1.valid := x._2.wen && x._2.v0Wen 294 x._1.bits := x._2.addr 295 }) 296 ctrlBlock.io.toDispatch.wbPregsVl.zip(wbDataPath.io.toVlPreg).map(x => { 297 x._1.valid := x._2.wen && x._2.vlWen 298 x._1.bits := x._2.addr 299 }) 300 ctrlBlock.io.csrCtrl <> intExuBlock.io.csrio.get.customCtrl 301 ctrlBlock.io.robio.csr.intrBitSet := intExuBlock.io.csrio.get.interrupt 302 ctrlBlock.io.robio.csr.trapTarget := intExuBlock.io.csrio.get.trapTarget 303 ctrlBlock.io.robio.csr.isXRet := intExuBlock.io.csrio.get.isXRet 304 ctrlBlock.io.robio.csr.wfiEvent := intExuBlock.io.csrio.get.wfi_event 305 ctrlBlock.io.robio.csr.criticalErrorState := intExuBlock.io.csrio.get.criticalErrorState 306 ctrlBlock.io.robio.lsq <> io.mem.robLsqIO 307 ctrlBlock.io.robio.lsTopdownInfo <> io.mem.lsTopdownInfo 308 ctrlBlock.io.robio.debug_ls <> io.mem.debugLS 309 ctrlBlock.io.debugEnqLsq.canAccept := io.mem.lsqEnqIO.canAccept 310 ctrlBlock.io.debugEnqLsq.resp := io.mem.lsqEnqIO.resp 311 ctrlBlock.io.debugEnqLsq.req := ctrlBlock.io.toMem.lsqEnqIO.req 312 ctrlBlock.io.debugEnqLsq.needAlloc := ctrlBlock.io.toMem.lsqEnqIO.needAlloc 313 ctrlBlock.io.debugEnqLsq.iqAccept := ctrlBlock.io.toMem.lsqEnqIO.iqAccept 314 ctrlBlock.io.fromVecExcpMod.busy := vecExcpMod.o.status.busy 315 316 val intWriteBackDelayed = Wire(chiselTypeOf(wbDataPath.io.toIntPreg)) 317 intWriteBackDelayed.zip(wbDataPath.io.toIntPreg).map{ case (sink, source) => 318 sink := DontCare 319 sink.wen := RegNext(source.wen) 320 sink.intWen := RegNext(source.intWen) 321 sink.addr := RegEnable(source.addr, source.wen) 322 } 323 val fpWriteBackDelayed = Wire(chiselTypeOf(wbDataPath.io.toFpPreg)) 324 fpWriteBackDelayed.zip(wbDataPath.io.toFpPreg).map { case (sink, source) => 325 sink := DontCare 326 sink.wen := RegNext(source.wen) 327 sink.fpWen := RegNext(source.fpWen) 328 sink.addr := RegEnable(source.addr, source.wen) 329 } 330 val vfWriteBackDelayed = Wire(chiselTypeOf(wbDataPath.io.toVfPreg)) 331 vfWriteBackDelayed.zip(wbDataPath.io.toVfPreg).map { case (sink, source) => 332 sink := DontCare 333 sink.wen := RegNext(source.wen) 334 sink.vecWen := RegNext(source.vecWen) 335 sink.addr := RegEnable(source.addr, source.wen) 336 } 337 val v0WriteBackDelayed = Wire(chiselTypeOf(wbDataPath.io.toV0Preg)) 338 v0WriteBackDelayed.zip(wbDataPath.io.toV0Preg).map { case (sink, source) => 339 sink := DontCare 340 sink.wen := RegNext(source.wen) 341 sink.v0Wen := RegNext(source.v0Wen) 342 sink.addr := RegEnable(source.addr, source.wen) 343 } 344 val vlWriteBackDelayed = Wire(chiselTypeOf(wbDataPath.io.toVlPreg)) 345 vlWriteBackDelayed.zip(wbDataPath.io.toVlPreg).map { case (sink, source) => 346 sink := DontCare 347 sink.wen := RegNext(source.wen) 348 sink.vlWen := RegNext(source.vlWen) 349 sink.addr := RegEnable(source.addr, source.wen) 350 } 351 intScheduler.io.fromTop.hartId := io.fromTop.hartId 352 intScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 353 intScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.intUops 354 intScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 355 intScheduler.io.fpWriteBack := 0.U.asTypeOf(intScheduler.io.fpWriteBack) 356 intScheduler.io.vfWriteBack := 0.U.asTypeOf(intScheduler.io.vfWriteBack) 357 intScheduler.io.v0WriteBack := 0.U.asTypeOf(intScheduler.io.v0WriteBack) 358 intScheduler.io.vlWriteBack := 0.U.asTypeOf(intScheduler.io.vlWriteBack) 359 intScheduler.io.intWriteBackDelayed := intWriteBackDelayed 360 intScheduler.io.fpWriteBackDelayed := 0.U.asTypeOf(intScheduler.io.fpWriteBackDelayed) 361 intScheduler.io.vfWriteBackDelayed := 0.U.asTypeOf(intScheduler.io.vfWriteBackDelayed) 362 intScheduler.io.v0WriteBackDelayed := 0.U.asTypeOf(intScheduler.io.v0WriteBackDelayed) 363 intScheduler.io.vlWriteBackDelayed := 0.U.asTypeOf(intScheduler.io.vlWriteBackDelayed) 364 intScheduler.io.fromDataPath.resp := dataPath.io.toIntIQ 365 intScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 366 intScheduler.io.fromSchedulers.wakeupVecDelayed.foreach { wakeup => wakeup := iqWakeUpMappedBundleDelayed(wakeup.bits.exuIdx) } 367 intScheduler.io.fromDataPath.og0Cancel := og0Cancel 368 intScheduler.io.fromDataPath.og1Cancel := og1Cancel 369 intScheduler.io.ldCancel := io.mem.ldCancel 370 intScheduler.io.fromDataPath.replaceRCIdx.get := dataPath.io.toWakeupQueueRCIdx.take(params.getIntExuRCWriteSize) 371 intScheduler.io.vlWriteBackInfo.vlFromIntIsZero := false.B 372 intScheduler.io.vlWriteBackInfo.vlFromIntIsVlmax := false.B 373 intScheduler.io.vlWriteBackInfo.vlFromVfIsZero := false.B 374 intScheduler.io.vlWriteBackInfo.vlFromVfIsVlmax := false.B 375 376 fpScheduler.io.fromTop.hartId := io.fromTop.hartId 377 fpScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 378 fpScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.fpUops 379 fpScheduler.io.intWriteBack := 0.U.asTypeOf(fpScheduler.io.intWriteBack) 380 fpScheduler.io.fpWriteBack := wbDataPath.io.toFpPreg 381 fpScheduler.io.vfWriteBack := 0.U.asTypeOf(fpScheduler.io.vfWriteBack) 382 fpScheduler.io.v0WriteBack := 0.U.asTypeOf(fpScheduler.io.v0WriteBack) 383 fpScheduler.io.vlWriteBack := 0.U.asTypeOf(fpScheduler.io.vlWriteBack) 384 fpScheduler.io.intWriteBackDelayed := 0.U.asTypeOf(intWriteBackDelayed) 385 fpScheduler.io.fpWriteBackDelayed := fpWriteBackDelayed 386 fpScheduler.io.vfWriteBackDelayed := 0.U.asTypeOf(intScheduler.io.vfWriteBackDelayed) 387 fpScheduler.io.v0WriteBackDelayed := 0.U.asTypeOf(intScheduler.io.v0WriteBackDelayed) 388 fpScheduler.io.vlWriteBackDelayed := 0.U.asTypeOf(intScheduler.io.vlWriteBackDelayed) 389 fpScheduler.io.fromDataPath.resp := dataPath.io.toFpIQ 390 fpScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 391 fpScheduler.io.fromSchedulers.wakeupVecDelayed.foreach { wakeup => wakeup := iqWakeUpMappedBundleDelayed(wakeup.bits.exuIdx) } 392 fpScheduler.io.fromDataPath.og0Cancel := og0Cancel 393 fpScheduler.io.fromDataPath.og1Cancel := og1Cancel 394 fpScheduler.io.ldCancel := io.mem.ldCancel 395 fpScheduler.io.vlWriteBackInfo.vlFromIntIsZero := false.B 396 fpScheduler.io.vlWriteBackInfo.vlFromIntIsVlmax := false.B 397 fpScheduler.io.vlWriteBackInfo.vlFromVfIsZero := false.B 398 fpScheduler.io.vlWriteBackInfo.vlFromVfIsVlmax := false.B 399 400 memScheduler.io.fromTop.hartId := io.fromTop.hartId 401 memScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 402 memScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.memUops 403 memScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 404 memScheduler.io.fpWriteBack := wbDataPath.io.toFpPreg 405 memScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 406 memScheduler.io.v0WriteBack := wbDataPath.io.toV0Preg 407 memScheduler.io.vlWriteBack := wbDataPath.io.toVlPreg 408 memScheduler.io.intWriteBackDelayed := intWriteBackDelayed 409 memScheduler.io.fpWriteBackDelayed := fpWriteBackDelayed 410 memScheduler.io.vfWriteBackDelayed := vfWriteBackDelayed 411 memScheduler.io.v0WriteBackDelayed := v0WriteBackDelayed 412 memScheduler.io.vlWriteBackDelayed := vlWriteBackDelayed 413 memScheduler.io.fromMem.get.scommit := io.mem.sqDeq 414 memScheduler.io.fromMem.get.lcommit := io.mem.lqDeq 415 memScheduler.io.fromMem.get.wakeup := io.mem.wakeup 416 memScheduler.io.fromMem.get.sqDeqPtr := io.mem.sqDeqPtr 417 memScheduler.io.fromMem.get.lqDeqPtr := io.mem.lqDeqPtr 418 memScheduler.io.fromMem.get.sqCancelCnt := io.mem.sqCancelCnt 419 memScheduler.io.fromMem.get.lqCancelCnt := io.mem.lqCancelCnt 420 memScheduler.io.fromMem.get.stIssuePtr := io.mem.stIssuePtr 421 require(memScheduler.io.fromMem.get.memWaitUpdateReq.robIdx.length == io.mem.stIn.length) 422 memScheduler.io.fromMem.get.memWaitUpdateReq.robIdx.zip(io.mem.stIn).foreach { case (sink, source) => 423 sink.valid := source.valid 424 sink.bits := source.bits.robIdx 425 } 426 memScheduler.io.fromMem.get.memWaitUpdateReq.sqIdx := DontCare // TODO 427 memScheduler.io.fromDataPath.resp := dataPath.io.toMemIQ 428 memScheduler.io.fromMem.get.ldaFeedback := io.mem.ldaIqFeedback 429 memScheduler.io.fromMem.get.staFeedback := io.mem.staIqFeedback 430 memScheduler.io.fromMem.get.hyuFeedback := io.mem.hyuIqFeedback 431 memScheduler.io.fromMem.get.vstuFeedback := io.mem.vstuIqFeedback 432 memScheduler.io.fromMem.get.vlduFeedback := io.mem.vlduIqFeedback 433 memScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 434 memScheduler.io.fromSchedulers.wakeupVecDelayed.foreach { wakeup => wakeup := iqWakeUpMappedBundleDelayed(wakeup.bits.exuIdx) } 435 memScheduler.io.fromDataPath.og0Cancel := og0Cancel 436 memScheduler.io.fromDataPath.og1Cancel := og1Cancel 437 memScheduler.io.ldCancel := io.mem.ldCancel 438 memScheduler.io.fromDataPath.replaceRCIdx.get := dataPath.io.toWakeupQueueRCIdx.takeRight(params.getMemExuRCWriteSize) 439 memScheduler.io.vlWriteBackInfo.vlFromIntIsZero := vlFromIntIsZero 440 memScheduler.io.vlWriteBackInfo.vlFromIntIsVlmax := vlFromIntIsVlmax 441 memScheduler.io.vlWriteBackInfo.vlFromVfIsZero := vlFromVfIsZero 442 memScheduler.io.vlWriteBackInfo.vlFromVfIsVlmax := vlFromVfIsVlmax 443 memScheduler.io.fromOg2Resp.get := og2ForVector.io.toMemIQOg2Resp 444 445 vfScheduler.io.fromTop.hartId := io.fromTop.hartId 446 vfScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 447 vfScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.vfUops 448 vfScheduler.io.intWriteBack := 0.U.asTypeOf(vfScheduler.io.intWriteBack) 449 vfScheduler.io.fpWriteBack := 0.U.asTypeOf(vfScheduler.io.fpWriteBack) 450 vfScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 451 vfScheduler.io.v0WriteBack := wbDataPath.io.toV0Preg 452 vfScheduler.io.vlWriteBack := wbDataPath.io.toVlPreg 453 vfScheduler.io.intWriteBackDelayed := 0.U.asTypeOf(intWriteBackDelayed) 454 vfScheduler.io.fpWriteBackDelayed := 0.U.asTypeOf(fpWriteBackDelayed) 455 vfScheduler.io.vfWriteBackDelayed := vfWriteBackDelayed 456 vfScheduler.io.v0WriteBackDelayed := v0WriteBackDelayed 457 vfScheduler.io.vlWriteBackDelayed := vlWriteBackDelayed 458 vfScheduler.io.fromDataPath.resp := dataPath.io.toVfIQ 459 vfScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 460 vfScheduler.io.fromSchedulers.wakeupVecDelayed.foreach { wakeup => wakeup := iqWakeUpMappedBundleDelayed(wakeup.bits.exuIdx) } 461 vfScheduler.io.fromDataPath.og0Cancel := og0Cancel 462 vfScheduler.io.fromDataPath.og1Cancel := og1Cancel 463 vfScheduler.io.ldCancel := io.mem.ldCancel 464 vfScheduler.io.vlWriteBackInfo.vlFromIntIsZero := vlFromIntIsZero 465 vfScheduler.io.vlWriteBackInfo.vlFromIntIsVlmax := vlFromIntIsVlmax 466 vfScheduler.io.vlWriteBackInfo.vlFromVfIsZero := vlFromVfIsZero 467 vfScheduler.io.vlWriteBackInfo.vlFromVfIsVlmax := vlFromVfIsVlmax 468 vfScheduler.io.fromOg2Resp.get := og2ForVector.io.toVfIQOg2Resp 469 470 dataPath.io.hartId := io.fromTop.hartId 471 dataPath.io.flush := ctrlBlock.io.toDataPath.flush 472 473 dataPath.io.fromIntIQ <> intScheduler.io.toDataPathAfterDelay 474 dataPath.io.fromFpIQ <> fpScheduler.io.toDataPathAfterDelay 475 dataPath.io.fromVfIQ <> vfScheduler.io.toDataPathAfterDelay 476 dataPath.io.fromMemIQ <> memScheduler.io.toDataPathAfterDelay 477 478 dataPath.io.ldCancel := io.mem.ldCancel 479 480 println(s"[Backend] wbDataPath.io.toIntPreg: ${wbDataPath.io.toIntPreg.size}, dataPath.io.fromIntWb: ${dataPath.io.fromIntWb.size}") 481 println(s"[Backend] wbDataPath.io.toVfPreg: ${wbDataPath.io.toVfPreg.size}, dataPath.io.fromFpWb: ${dataPath.io.fromVfWb.size}") 482 dataPath.io.fromIntWb := wbDataPath.io.toIntPreg 483 dataPath.io.fromFpWb := wbDataPath.io.toFpPreg 484 dataPath.io.fromVfWb := wbDataPath.io.toVfPreg 485 dataPath.io.fromV0Wb := wbDataPath.io.toV0Preg 486 dataPath.io.fromVlWb := wbDataPath.io.toVlPreg 487 dataPath.io.diffIntRat.foreach(_ := ctrlBlock.io.diff_int_rat.get) 488 dataPath.io.diffFpRat .foreach(_ := ctrlBlock.io.diff_fp_rat.get) 489 dataPath.io.diffVecRat.foreach(_ := ctrlBlock.io.diff_vec_rat.get) 490 dataPath.io.diffV0Rat .foreach(_ := ctrlBlock.io.diff_v0_rat.get) 491 dataPath.io.diffVlRat .foreach(_ := ctrlBlock.io.diff_vl_rat.get) 492 dataPath.io.fromBypassNetwork := bypassNetwork.io.toDataPath 493 dataPath.io.fromVecExcpMod.r := vecExcpMod.o.toVPRF.r 494 dataPath.io.fromVecExcpMod.w := vecExcpMod.o.toVPRF.w 495 dataPath.io.topDownInfo.lqEmpty := DelayN(io.topDownInfo.lqEmpty, 2) 496 dataPath.io.topDownInfo.sqEmpty := DelayN(io.topDownInfo.sqEmpty, 2) 497 dataPath.io.topDownInfo.l1Miss := RegNext(io.topDownInfo.l1Miss) 498 dataPath.io.topDownInfo.l2TopMiss.l2Miss := io.topDownInfo.l2TopMiss.l2Miss 499 dataPath.io.topDownInfo.l2TopMiss.l3Miss := io.topDownInfo.l2TopMiss.l3Miss 500 501 og2ForVector.io.flush := ctrlBlock.io.toDataPath.flush 502 og2ForVector.io.ldCancel := io.mem.ldCancel 503 og2ForVector.io.fromOg1VfArith <> dataPath.io.toVecExu 504 og2ForVector.io.fromOg1VecMem.zip(dataPath.io.toMemExu.zip(params.memSchdParams.get.issueBlockParams).filter(_._2.needOg2Resp).map(_._1)) 505 .foreach { 506 case (og1Mem, datapathMem) => og1Mem <> datapathMem 507 } 508 og2ForVector.io.fromOg1ImmInfo := dataPath.io.og1ImmInfo.zip(params.allExuParams).filter(_._2.needOg2).map(_._1) 509 510 println(s"[Backend] BypassNetwork OG1 Mem Size: ${bypassNetwork.io.fromDataPath.mem.zip(params.memSchdParams.get.issueBlockParams).filterNot(_._2.needOg2Resp).size}") 511 println(s"[Backend] BypassNetwork OG2 Mem Size: ${bypassNetwork.io.fromDataPath.mem.zip(params.memSchdParams.get.issueBlockParams).filter(_._2.needOg2Resp).size}") 512 println(s"[Backend] bypassNetwork.io.fromDataPath.mem: ${bypassNetwork.io.fromDataPath.mem.size}, dataPath.io.toMemExu: ${dataPath.io.toMemExu.size}") 513 bypassNetwork.io.fromDataPath.int <> dataPath.io.toIntExu 514 bypassNetwork.io.fromDataPath.fp <> dataPath.io.toFpExu 515 bypassNetwork.io.fromDataPath.vf <> og2ForVector.io.toVfArithExu 516 bypassNetwork.io.fromDataPath.mem.lazyZip(params.memSchdParams.get.issueBlockParams).lazyZip(dataPath.io.toMemExu).filterNot(_._2.needOg2Resp) 517 .map(x => (x._1, x._3)).foreach { 518 case (bypassMem, datapathMem) => bypassMem <> datapathMem 519 } 520 bypassNetwork.io.fromDataPath.mem.zip(params.memSchdParams.get.issueBlockParams).filter(_._2.needOg2Resp).map(_._1) 521 .zip(og2ForVector.io.toVecMemExu).foreach { 522 case (bypassMem, og2Mem) => bypassMem <> og2Mem 523 } 524 bypassNetwork.io.fromDataPath.immInfo := dataPath.io.og1ImmInfo 525 bypassNetwork.io.fromDataPath.immInfo.zip(params.allExuParams).filter(_._2.needOg2).map(_._1) 526 .zip(og2ForVector.io.toBypassNetworkImmInfo).foreach { 527 case (immInfo, og2ImmInfo) => immInfo := og2ImmInfo 528 } 529 bypassNetwork.io.fromDataPath.rcData := dataPath.io.toBypassNetworkRCData 530 bypassNetwork.io.fromExus.connectExuOutput(_.int)(intExuBlock.io.out) 531 bypassNetwork.io.fromExus.connectExuOutput(_.fp)(fpExuBlock.io.out) 532 bypassNetwork.io.fromExus.connectExuOutput(_.vf)(vfExuBlock.io.out) 533 534 require(bypassNetwork.io.fromExus.mem.flatten.size == io.mem.writeBack.size, 535 s"bypassNetwork.io.fromExus.mem.flatten.size(${bypassNetwork.io.fromExus.mem.flatten.size}: ${bypassNetwork.io.fromExus.mem.map(_.size)}, " + 536 s"io.mem.writeback(${io.mem.writeBack.size})" 537 ) 538 bypassNetwork.io.fromExus.mem.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 539 sink.valid := source.valid 540 sink.bits.intWen := source.bits.uop.rfWen && source.bits.isFromLoadUnit 541 sink.bits.pdest := source.bits.uop.pdest 542 sink.bits.data := source.bits.data 543 } 544 545 546 intExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 547 for (i <- 0 until intExuBlock.io.in.length) { 548 for (j <- 0 until intExuBlock.io.in(i).length) { 549 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.int(i)(j).bits.loadDependency, io.mem.ldCancel) 550 NewPipelineConnect( 551 bypassNetwork.io.toExus.int(i)(j), intExuBlock.io.in(i)(j), intExuBlock.io.in(i)(j).fire, 552 Mux( 553 bypassNetwork.io.toExus.int(i)(j).fire, 554 bypassNetwork.io.toExus.int(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 555 intExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 556 ), 557 Option("bypassNetwork2intExuBlock") 558 ) 559 } 560 } 561 562 ctrlBlock.io.toDataPath.pcToDataPathIO <> dataPath.io.fromPcTargetMem 563 564 private val csrin = intExuBlock.io.csrin.get 565 csrin.hartId := io.fromTop.hartId 566 csrin.msiInfo.valid := RegNext(io.fromTop.msiInfo.valid) 567 csrin.msiInfo.bits := RegEnable(io.fromTop.msiInfo.bits, io.fromTop.msiInfo.valid) 568 csrin.clintTime.valid := RegNext(io.fromTop.clintTime.valid) 569 csrin.clintTime.bits := RegEnable(io.fromTop.clintTime.bits, io.fromTop.clintTime.valid) 570 csrin.l2FlushDone := RegNext(io.fromTop.l2FlushDone) 571 csrin.trapInstInfo := ctrlBlock.io.toCSR.trapInstInfo 572 csrin.fromVecExcpMod.busy := vecExcpMod.o.status.busy 573 csrin.criticalErrorState := backendCriticalError 574 575 private val csrio = intExuBlock.io.csrio.get 576 csrio.hartId := io.fromTop.hartId 577 csrio.fpu.fflags := ctrlBlock.io.robio.csr.fflags 578 csrio.fpu.isIllegal := false.B // Todo: remove it 579 csrio.fpu.dirty_fs := ctrlBlock.io.robio.csr.dirty_fs 580 csrio.vpu <> WireDefault(0.U.asTypeOf(csrio.vpu)) // Todo 581 582 val fromIntExuVsetVType = intExuBlock.io.vtype.getOrElse(0.U.asTypeOf((Valid(new VType)))) 583 val fromVfExuVsetVType = vfExuBlock.io.vtype.getOrElse(0.U.asTypeOf((Valid(new VType)))) 584 val fromVsetVType = Mux(fromIntExuVsetVType.valid, fromIntExuVsetVType.bits, fromVfExuVsetVType.bits) 585 val vsetvlVType = RegEnable(fromVsetVType, 0.U.asTypeOf(new VType), fromIntExuVsetVType.valid || fromVfExuVsetVType.valid) 586 ctrlBlock.io.toDecode.vsetvlVType := vsetvlVType 587 588 val commitVType = ctrlBlock.io.robio.commitVType.vtype 589 val hasVsetvl = ctrlBlock.io.robio.commitVType.hasVsetvl 590 val vtype = VType.toVtypeStruct(Mux(hasVsetvl, vsetvlVType, commitVType.bits)).asUInt 591 592 // csr not store the value of vl, so when using difftest we assign the value of vl to debugVl 593 val debugVl_s0 = WireInit(UInt(VlData().dataWidth.W), 0.U) 594 val debugVl_s1 = WireInit(UInt(VlData().dataWidth.W), 0.U) 595 debugVl_s0 := dataPath.io.diffVl.getOrElse(0.U.asTypeOf(UInt(VlData().dataWidth.W))) 596 debugVl_s1 := RegNext(debugVl_s0) 597 csrio.vpu.set_vxsat := ctrlBlock.io.robio.csr.vxsat 598 csrio.vpu.set_vstart.valid := ctrlBlock.io.robio.csr.vstart.valid 599 csrio.vpu.set_vstart.bits := ctrlBlock.io.robio.csr.vstart.bits 600 ctrlBlock.io.toDecode.vstart := csrio.vpu.vstart 601 //Todo here need change design 602 csrio.vpu.set_vtype.valid := commitVType.valid 603 csrio.vpu.set_vtype.bits := ZeroExt(vtype, XLEN) 604 csrio.vpu.vl := ZeroExt(debugVl_s1, XLEN) 605 csrio.vpu.dirty_vs := ctrlBlock.io.robio.csr.dirty_vs 606 csrio.exception := ctrlBlock.io.robio.exception 607 csrio.robDeqPtr := ctrlBlock.io.robio.robDeqPtr 608 csrio.memExceptionVAddr := io.mem.exceptionAddr.vaddr 609 csrio.memExceptionGPAddr := io.mem.exceptionAddr.gpaddr 610 csrio.memExceptionIsForVSnonLeafPTE := io.mem.exceptionAddr.isForVSnonLeafPTE 611 csrio.externalInterrupt := RegNext(io.fromTop.externalInterrupt) 612 csrio.perf <> io.perf 613 csrio.perf.retiredInstr <> ctrlBlock.io.robio.csr.perfinfo.retiredInstr 614 csrio.perf.ctrlInfo <> ctrlBlock.io.perfInfo.ctrlInfo 615 private val fenceio = intExuBlock.io.fenceio.get 616 io.fenceio <> fenceio 617 618 // to fpExuBlock 619 fpExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 620 for (i <- 0 until fpExuBlock.io.in.length) { 621 for (j <- 0 until fpExuBlock.io.in(i).length) { 622 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.fp(i)(j).bits.loadDependency, io.mem.ldCancel) 623 NewPipelineConnect( 624 bypassNetwork.io.toExus.fp(i)(j), fpExuBlock.io.in(i)(j), fpExuBlock.io.in(i)(j).fire, 625 Mux( 626 bypassNetwork.io.toExus.fp(i)(j).fire, 627 bypassNetwork.io.toExus.fp(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 628 fpExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 629 ), 630 Option("bypassNetwork2fpExuBlock") 631 ) 632 } 633 } 634 635 vfExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 636 for (i <- 0 until vfExuBlock.io.in.size) { 637 for (j <- 0 until vfExuBlock.io.in(i).size) { 638 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.vf(i)(j).bits.loadDependency, io.mem.ldCancel) 639 NewPipelineConnect( 640 bypassNetwork.io.toExus.vf(i)(j), vfExuBlock.io.in(i)(j), vfExuBlock.io.in(i)(j).fire, 641 Mux( 642 bypassNetwork.io.toExus.vf(i)(j).fire, 643 bypassNetwork.io.toExus.vf(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 644 vfExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 645 ), 646 Option("bypassNetwork2vfExuBlock") 647 ) 648 649 } 650 } 651 652 intExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 653 fpExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 654 fpExuBlock.io.vxrm.foreach(_ := csrio.vpu.vxrm) 655 vfExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 656 vfExuBlock.io.vxrm.foreach(_ := csrio.vpu.vxrm) 657 658 wbDataPath.io.flush := ctrlBlock.io.redirect 659 wbDataPath.io.fromTop.hartId := io.fromTop.hartId 660 wbDataPath.io.fromIntExu <> intExuBlock.io.out 661 wbDataPath.io.fromFpExu <> fpExuBlock.io.out 662 wbDataPath.io.fromVfExu <> vfExuBlock.io.out 663 wbDataPath.io.fromMemExu.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 664 sink.valid := source.valid 665 source.ready := sink.ready 666 sink.bits.data := VecInit(Seq.fill(sink.bits.params.wbPathNum)(source.bits.data)) 667 sink.bits.pdest := source.bits.uop.pdest 668 sink.bits.robIdx := source.bits.uop.robIdx 669 sink.bits.intWen.foreach(_ := source.bits.uop.rfWen) 670 sink.bits.fpWen.foreach(_ := source.bits.uop.fpWen) 671 sink.bits.vecWen.foreach(_ := source.bits.uop.vecWen) 672 sink.bits.v0Wen.foreach(_ := source.bits.uop.v0Wen) 673 sink.bits.vlWen.foreach(_ := source.bits.uop.vlWen) 674 sink.bits.exceptionVec.foreach(_ := source.bits.uop.exceptionVec) 675 sink.bits.flushPipe.foreach(_ := source.bits.uop.flushPipe) 676 sink.bits.replay.foreach(_ := source.bits.uop.replayInst) 677 sink.bits.debug := source.bits.debug 678 sink.bits.debugInfo := source.bits.uop.debugInfo 679 sink.bits.lqIdx.foreach(_ := source.bits.uop.lqIdx) 680 sink.bits.sqIdx.foreach(_ := source.bits.uop.sqIdx) 681 sink.bits.predecodeInfo.foreach(_ := source.bits.uop.preDecodeInfo) 682 sink.bits.vls.foreach(x => { 683 x.vdIdx := source.bits.vdIdx.get 684 x.vdIdxInField := source.bits.vdIdxInField.get 685 x.vpu := source.bits.uop.vpu 686 x.oldVdPsrc := source.bits.uop.psrc(2) 687 x.isIndexed := VlduType.isIndexed(source.bits.uop.fuOpType) 688 x.isMasked := VlduType.isMasked(source.bits.uop.fuOpType) 689 x.isStrided := VlduType.isStrided(source.bits.uop.fuOpType) 690 x.isWhole := VlduType.isWhole(source.bits.uop.fuOpType) 691 x.isVecLoad := VlduType.isVecLd(source.bits.uop.fuOpType) 692 x.isVlm := VlduType.isMasked(source.bits.uop.fuOpType) && VlduType.isVecLd(source.bits.uop.fuOpType) 693 }) 694 sink.bits.trigger.foreach(_ := source.bits.uop.trigger) 695 } 696 wbDataPath.io.fromCSR.vstart := csrio.vpu.vstart 697 698 vecExcpMod.i.fromExceptionGen := ctrlBlock.io.toVecExcpMod.excpInfo 699 vecExcpMod.i.fromRab.logicPhyRegMap := ctrlBlock.io.toVecExcpMod.logicPhyRegMap 700 vecExcpMod.i.fromRat := ctrlBlock.io.toVecExcpMod.ratOldPest 701 vecExcpMod.i.fromVprf := dataPath.io.toVecExcpMod 702 703 // to mem 704 private val memIssueParams = params.memSchdParams.get.issueBlockParams 705 private val memExuBlocksHasLDU = memIssueParams.map(_.exuBlockParams.map(x => x.hasLoadFu || x.hasHyldaFu)) 706 private val memExuBlocksHasVecLoad = memIssueParams.map(_.exuBlockParams.map(x => x.hasVLoadFu)) 707 println(s"[Backend] memExuBlocksHasLDU: $memExuBlocksHasLDU") 708 println(s"[Backend] memExuBlocksHasVecLoad: $memExuBlocksHasVecLoad") 709 710 private val toMem = Wire(bypassNetwork.io.toExus.mem.cloneType) 711 for (i <- toMem.indices) { 712 for (j <- toMem(i).indices) { 713 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.mem(i)(j).bits.loadDependency, io.mem.ldCancel) 714 val needIssueTimeout = memExuBlocksHasLDU(i)(j) || memExuBlocksHasVecLoad(i)(j) 715 val issueTimeout = 716 if (needIssueTimeout) 717 Counter(0 until 16, toMem(i)(j).valid && !toMem(i)(j).fire, bypassNetwork.io.toExus.mem(i)(j).fire)._2 718 else 719 false.B 720 721 if (memScheduler.io.loadFinalIssueResp(i).nonEmpty && memExuBlocksHasLDU(i)(j)) { 722 memScheduler.io.loadFinalIssueResp(i)(j).valid := issueTimeout 723 memScheduler.io.loadFinalIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType 724 memScheduler.io.loadFinalIssueResp(i)(j).bits.resp := RespType.block 725 memScheduler.io.loadFinalIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx 726 memScheduler.io.loadFinalIssueResp(i)(j).bits.uopIdx.foreach(_ := toMem(i)(j).bits.vpu.get.vuopIdx) 727 memScheduler.io.loadFinalIssueResp(i)(j).bits.sqIdx.foreach(_ := toMem(i)(j).bits.sqIdx.get) 728 memScheduler.io.loadFinalIssueResp(i)(j).bits.lqIdx.foreach(_ := toMem(i)(j).bits.lqIdx.get) 729 } 730 731 if (memScheduler.io.vecLoadFinalIssueResp(i).nonEmpty && memExuBlocksHasVecLoad(i)(j)) { 732 memScheduler.io.vecLoadFinalIssueResp(i)(j).valid := issueTimeout 733 memScheduler.io.vecLoadFinalIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType 734 memScheduler.io.vecLoadFinalIssueResp(i)(j).bits.resp := RespType.block 735 memScheduler.io.vecLoadFinalIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx 736 memScheduler.io.vecLoadFinalIssueResp(i)(j).bits.uopIdx.foreach(_ := toMem(i)(j).bits.vpu.get.vuopIdx) 737 memScheduler.io.vecLoadFinalIssueResp(i)(j).bits.sqIdx.foreach(_ := toMem(i)(j).bits.sqIdx.get) 738 memScheduler.io.vecLoadFinalIssueResp(i)(j).bits.lqIdx.foreach(_ := toMem(i)(j).bits.lqIdx.get) 739 } 740 741 NewPipelineConnect( 742 bypassNetwork.io.toExus.mem(i)(j), toMem(i)(j), toMem(i)(j).fire, 743 Mux( 744 bypassNetwork.io.toExus.mem(i)(j).fire, 745 bypassNetwork.io.toExus.mem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 746 toMem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || issueTimeout 747 ), 748 Option("bypassNetwork2toMemExus") 749 ) 750 751 if (memScheduler.io.memAddrIssueResp(i).nonEmpty && memExuBlocksHasLDU(i)(j)) { 752 memScheduler.io.memAddrIssueResp(i)(j).valid := toMem(i)(j).fire && FuType.isLoad(toMem(i)(j).bits.fuType) 753 memScheduler.io.memAddrIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType 754 memScheduler.io.memAddrIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx 755 memScheduler.io.memAddrIssueResp(i)(j).bits.sqIdx.foreach(_ := toMem(i)(j).bits.sqIdx.get) 756 memScheduler.io.memAddrIssueResp(i)(j).bits.lqIdx.foreach(_ := toMem(i)(j).bits.lqIdx.get) 757 memScheduler.io.memAddrIssueResp(i)(j).bits.resp := RespType.success // for load inst, firing at toMem means issuing successfully 758 } 759 760 if (memScheduler.io.vecLoadIssueResp(i).nonEmpty && memExuBlocksHasVecLoad(i)(j)) { 761 memScheduler.io.vecLoadIssueResp(i)(j) match { 762 case resp => 763 resp.valid := toMem(i)(j).fire && VlduType.isVecLd(toMem(i)(j).bits.fuOpType) 764 resp.bits.fuType := toMem(i)(j).bits.fuType 765 resp.bits.robIdx := toMem(i)(j).bits.robIdx 766 resp.bits.uopIdx.get := toMem(i)(j).bits.vpu.get.vuopIdx 767 resp.bits.sqIdx.get := toMem(i)(j).bits.sqIdx.get 768 resp.bits.lqIdx.get := toMem(i)(j).bits.lqIdx.get 769 resp.bits.resp := RespType.success 770 } 771 if (backendParams.debugEn){ 772 dontTouch(memScheduler.io.vecLoadIssueResp(i)(j)) 773 } 774 } 775 } 776 } 777 778 io.mem.redirect := ctrlBlock.io.redirect 779 io.mem.issueUops.zip(toMem.flatten).foreach { case (sink, source) => 780 val enableMdp = Constantin.createRecord("EnableMdp", true) 781 sink.valid := source.valid 782 source.ready := sink.ready 783 sink.bits.iqIdx := source.bits.iqIdx 784 sink.bits.isFirstIssue := source.bits.isFirstIssue 785 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 786 sink.bits.src := 0.U.asTypeOf(sink.bits.src) 787 sink.bits.src.zip(source.bits.src).foreach { case (l, r) => l := r} 788 sink.bits.uop.fuType := source.bits.fuType 789 sink.bits.uop.fuOpType := source.bits.fuOpType 790 sink.bits.uop.imm := source.bits.imm 791 sink.bits.uop.robIdx := source.bits.robIdx 792 sink.bits.uop.pdest := source.bits.pdest 793 sink.bits.uop.rfWen := source.bits.rfWen.getOrElse(false.B) 794 sink.bits.uop.fpWen := source.bits.fpWen.getOrElse(false.B) 795 sink.bits.uop.vecWen := source.bits.vecWen.getOrElse(false.B) 796 sink.bits.uop.v0Wen := source.bits.v0Wen.getOrElse(false.B) 797 sink.bits.uop.vlWen := source.bits.vlWen.getOrElse(false.B) 798 sink.bits.uop.flushPipe := source.bits.flushPipe.getOrElse(false.B) 799 sink.bits.uop.pc := source.bits.pc.getOrElse(0.U) + (source.bits.ftqOffset.getOrElse(0.U) << instOffsetBits) 800 sink.bits.uop.loadWaitBit := Mux(enableMdp, source.bits.loadWaitBit.getOrElse(false.B), false.B) 801 sink.bits.uop.waitForRobIdx := Mux(enableMdp, source.bits.waitForRobIdx.getOrElse(0.U.asTypeOf(new RobPtr)), 0.U.asTypeOf(new RobPtr)) 802 sink.bits.uop.storeSetHit := Mux(enableMdp, source.bits.storeSetHit.getOrElse(false.B), false.B) 803 sink.bits.uop.loadWaitStrict := Mux(enableMdp, source.bits.loadWaitStrict.getOrElse(false.B), false.B) 804 sink.bits.uop.ssid := Mux(enableMdp, source.bits.ssid.getOrElse(0.U(SSIDWidth.W)), 0.U(SSIDWidth.W)) 805 sink.bits.uop.lqIdx := source.bits.lqIdx.getOrElse(0.U.asTypeOf(new LqPtr)) 806 sink.bits.uop.sqIdx := source.bits.sqIdx.getOrElse(0.U.asTypeOf(new SqPtr)) 807 sink.bits.uop.ftqPtr := source.bits.ftqIdx.getOrElse(0.U.asTypeOf(new FtqPtr)) 808 sink.bits.uop.ftqOffset := source.bits.ftqOffset.getOrElse(0.U) 809 sink.bits.uop.debugInfo := source.bits.perfDebugInfo 810 sink.bits.uop.vpu := source.bits.vpu.getOrElse(0.U.asTypeOf(new VPUCtrlSignals)) 811 sink.bits.uop.preDecodeInfo := source.bits.preDecode.getOrElse(0.U.asTypeOf(new PreDecodeInfo)) 812 sink.bits.uop.numLsElem := source.bits.numLsElem.getOrElse(0.U) // Todo: remove this bundle, keep only the one below 813 sink.bits.flowNum.foreach(_ := source.bits.numLsElem.get) 814 } 815 io.mem.loadFastMatch := memScheduler.io.toMem.get.loadFastMatch.map(_.fastMatch) 816 io.mem.loadFastImm := memScheduler.io.toMem.get.loadFastMatch.map(_.fastImm) 817 io.mem.tlbCsr := csrio.tlb 818 io.mem.csrCtrl := csrio.customCtrl 819 io.mem.sfence := fenceio.sfence 820 io.mem.isStoreException := CommitType.lsInstIsStore(ctrlBlock.io.robio.exception.bits.commitType) 821 io.mem.isVlsException := ctrlBlock.io.robio.exception.bits.vls 822 823 io.mem.storePcRead.zipWithIndex.foreach { case (storePcRead, i) => 824 storePcRead := ctrlBlock.io.memStPcRead(i).data 825 ctrlBlock.io.memStPcRead(i).valid := io.mem.issueSta(i).valid 826 ctrlBlock.io.memStPcRead(i).ptr := io.mem.issueSta(i).bits.uop.ftqPtr 827 ctrlBlock.io.memStPcRead(i).offset := io.mem.issueSta(i).bits.uop.ftqOffset 828 } 829 830 io.mem.hyuPcRead.zipWithIndex.foreach( { case (hyuPcRead, i) => 831 hyuPcRead := ctrlBlock.io.memHyPcRead(i).data 832 ctrlBlock.io.memHyPcRead(i).valid := io.mem.issueHylda(i).valid 833 ctrlBlock.io.memHyPcRead(i).ptr := io.mem.issueHylda(i).bits.uop.ftqPtr 834 ctrlBlock.io.memHyPcRead(i).offset := io.mem.issueHylda(i).bits.uop.ftqOffset 835 }) 836 837 ctrlBlock.io.robio.robHeadLsIssue := io.mem.issueUops.map(deq => deq.fire && deq.bits.uop.robIdx === ctrlBlock.io.robio.robDeqPtr).reduce(_ || _) 838 839 // mem io 840 io.mem.robLsqIO <> ctrlBlock.io.robio.lsq 841 io.mem.storeDebugInfo <> ctrlBlock.io.robio.storeDebugInfo 842 843 io.frontendSfence := fenceio.sfence 844 io.frontendTlbCsr := csrio.tlb 845 io.frontendCsrCtrl := csrio.customCtrl 846 847 io.tlb <> csrio.tlb 848 849 io.csrCustomCtrl := csrio.customCtrl 850 851 io.toTop.cpuHalted := ctrlBlock.io.toTop.cpuHalt 852 853 io.traceCoreInterface <> ctrlBlock.io.traceCoreInterface 854 855 io.debugTopDown.fromRob := ctrlBlock.io.debugTopDown.fromRob 856 ctrlBlock.io.debugTopDown.fromCore := io.debugTopDown.fromCore 857 858 io.debugRolling := ctrlBlock.io.debugRolling 859 860 io.topDownInfo.noUopsIssued := RegNext(dataPath.io.topDownInfo.noUopsIssued) 861 862 if(backendParams.debugEn) { 863 dontTouch(memScheduler.io) 864 dontTouch(dataPath.io.toMemExu) 865 dontTouch(wbDataPath.io.fromMemExu) 866 } 867 868 // reset tree 869 if (p(DebugOptionsKey).ResetGen) { 870 val rightResetTree = ResetGenNode(Seq( 871 ModuleNode(dataPath), 872 ModuleNode(intExuBlock), 873 ModuleNode(fpExuBlock), 874 ModuleNode(vfExuBlock), 875 ModuleNode(bypassNetwork), 876 ModuleNode(wbDataPath) 877 )) 878 val leftResetTree = ResetGenNode(Seq( 879 ModuleNode(intScheduler), 880 ModuleNode(fpScheduler), 881 ModuleNode(vfScheduler), 882 ModuleNode(memScheduler), 883 ModuleNode(og2ForVector), 884 ModuleNode(wbFuBusyTable), 885 ResetGenNode(Seq( 886 ModuleNode(ctrlBlock), 887 // ResetGenNode(Seq( 888 CellNode(io.frontendReset) 889 // )) 890 )) 891 )) 892 ResetGen(leftResetTree, reset, sim = false) 893 ResetGen(rightResetTree, reset, sim = false) 894 } else { 895 io.frontendReset := DontCare 896 } 897 898 // perf events 899 val pfevent = Module(new PFEvent) 900 pfevent.io.distribute_csr := RegNext(csrio.customCtrl.distribute_csr) 901 val csrevents = pfevent.io.hpmevent.slice(8,16) 902 903 val ctrlBlockPerf = ctrlBlock.getPerfEvents 904 val intSchedulerPerf = intScheduler.asInstanceOf[SchedulerArithImp].getPerfEvents 905 val fpSchedulerPerf = fpScheduler.asInstanceOf[SchedulerArithImp].getPerfEvents 906 val vecSchedulerPerf = vfScheduler.asInstanceOf[SchedulerArithImp].getPerfEvents 907 val memSchedulerPerf = memScheduler.asInstanceOf[SchedulerMemImp].getPerfEvents 908 val dataPathPerf = dataPath.getPerfEvents 909 910 val perfBackend = Seq() 911 // let index = 0 be no event 912 val allPerfEvents = Seq(("noEvent", 0.U)) ++ ctrlBlockPerf ++ dataPathPerf ++ 913 intSchedulerPerf ++ fpSchedulerPerf ++ vecSchedulerPerf ++ memSchedulerPerf ++ perfBackend 914 915 916 if (printEventCoding) { 917 for (((name, inc), i) <- allPerfEvents.zipWithIndex) { 918 println("backend perfEvents Set", name, inc, i) 919 } 920 } 921 922 val allPerfInc = allPerfEvents.map(_._2.asTypeOf(new PerfEvent)) 923 val perfEvents = HPerfMonitor(csrevents, allPerfInc).getPerfEvents 924 csrio.perf.perfEventsBackend := VecInit(perfEvents.map(_._2.asTypeOf(new PerfEvent))) 925 926 val ctrlBlockError = ctrlBlock.getCriticalErrors 927 val intExuBlockError = intExuBlock.getCriticalErrors 928 val criticalErrors = ctrlBlockError ++ intExuBlockError 929 930 if (printCriticalError) { 931 for (((name, error), _) <- criticalErrors.zipWithIndex) { 932 XSError(error, s"critical error: $name \n") 933 } 934 } 935 936 // expand to collect frontend/memblock/L2 critical errors 937 backendCriticalError := criticalErrors.map(_._2).reduce(_ || _) 938 939 io.toTop.cpuCriticalError := csrio.criticalErrorState 940} 941 942class BackendMemIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 943 // Since fast load replay always use load unit 0, Backend flips two load port to avoid conflicts 944 val flippedLda = true 945 // params alias 946 private val LoadQueueSize = VirtualLoadQueueSize 947 // In/Out // Todo: split it into one-direction bundle 948 val lsqEnqIO = Flipped(new LsqEnqIO) 949 val robLsqIO = new RobLsqIO 950 val ldaIqFeedback = Vec(params.LduCnt, Flipped(new MemRSFeedbackIO)) 951 val staIqFeedback = Vec(params.StaCnt, Flipped(new MemRSFeedbackIO)) 952 val hyuIqFeedback = Vec(params.HyuCnt, Flipped(new MemRSFeedbackIO)) 953 val vstuIqFeedback = Flipped(Vec(params.VstuCnt, new MemRSFeedbackIO(isVector = true))) 954 val vlduIqFeedback = Flipped(Vec(params.VlduCnt, new MemRSFeedbackIO(isVector = true))) 955 val ldCancel = Vec(params.LdExuCnt, Input(new LoadCancelIO)) 956 val wakeup = Vec(params.LdExuCnt, Flipped(Valid(new DynInst))) 957 val storePcRead = Vec(params.StaCnt, Output(UInt(VAddrBits.W))) 958 val hyuPcRead = Vec(params.HyuCnt, Output(UInt(VAddrBits.W))) 959 // Input 960 val writebackLda = Vec(params.LduCnt, Flipped(DecoupledIO(new MemExuOutput))) 961 val writebackSta = Vec(params.StaCnt, Flipped(DecoupledIO(new MemExuOutput))) 962 val writebackStd = Vec(params.StdCnt, Flipped(DecoupledIO(new MemExuOutput))) 963 val writebackHyuLda = Vec(params.HyuCnt, Flipped(DecoupledIO(new MemExuOutput))) 964 val writebackHyuSta = Vec(params.HyuCnt, Flipped(DecoupledIO(new MemExuOutput))) 965 val writebackVldu = Vec(params.VlduCnt, Flipped(DecoupledIO(new MemExuOutput(true)))) 966 967 val s3_delayed_load_error = Input(Vec(LoadPipelineWidth, Bool())) 968 val stIn = Input(Vec(params.StaExuCnt, ValidIO(new DynInst()))) 969 val memoryViolation = Flipped(ValidIO(new Redirect)) 970 val exceptionAddr = Input(new Bundle { 971 val vaddr = UInt(XLEN.W) 972 val gpaddr = UInt(XLEN.W) 973 val isForVSnonLeafPTE = Bool() 974 }) 975 val sqDeq = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) 976 val lqDeq = Input(UInt(log2Up(CommitWidth + 1).W)) 977 val sqDeqPtr = Input(new SqPtr) 978 val lqDeqPtr = Input(new LqPtr) 979 980 val lqCancelCnt = Input(UInt(log2Up(VirtualLoadQueueSize + 1).W)) 981 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 982 983 val lqCanAccept = Input(Bool()) 984 val sqCanAccept = Input(Bool()) 985 986 val otherFastWakeup = Flipped(Vec(params.LduCnt + params.HyuCnt, ValidIO(new DynInst))) 987 val stIssuePtr = Input(new SqPtr()) 988 989 val debugLS = Flipped(Output(new DebugLSIO)) 990 991 val lsTopdownInfo = Vec(params.LduCnt + params.HyuCnt, Flipped(Output(new LsTopdownInfo))) 992 // Output 993 val redirect = ValidIO(new Redirect) // rob flush MemBlock 994 val issueLda = MixedVec(Seq.fill(params.LduCnt)(DecoupledIO(new MemExuInput()))) 995 val issueSta = MixedVec(Seq.fill(params.StaCnt)(DecoupledIO(new MemExuInput()))) 996 val issueStd = MixedVec(Seq.fill(params.StdCnt)(DecoupledIO(new MemExuInput()))) 997 val issueHylda = MixedVec(Seq.fill(params.HyuCnt)(DecoupledIO(new MemExuInput()))) 998 val issueHysta = MixedVec(Seq.fill(params.HyuCnt)(DecoupledIO(new MemExuInput()))) 999 val issueVldu = MixedVec(Seq.fill(params.VlduCnt)(DecoupledIO(new MemExuInput(true)))) 1000 1001 val loadFastMatch = Vec(params.LduCnt, Output(UInt(params.LduCnt.W))) 1002 val loadFastImm = Vec(params.LduCnt, Output(UInt(12.W))) // Imm_I 1003 1004 val tlbCsr = Output(new TlbCsrBundle) 1005 val csrCtrl = Output(new CustomCSRCtrlIO) 1006 val sfence = Output(new SfenceBundle) 1007 val isStoreException = Output(Bool()) 1008 val isVlsException = Output(Bool()) 1009 1010 // ATTENTION: The issue ports' sequence order should be the same as IQs' deq config 1011 private [backend] def issueUops: Seq[DecoupledIO[MemExuInput]] = { 1012 issueSta ++ 1013 issueHylda ++ issueHysta ++ 1014 issueLda ++ 1015 issueVldu ++ 1016 issueStd 1017 }.toSeq 1018 1019 // ATTENTION: The writeback ports' sequence order should be the same as IQs' deq config 1020 private [backend] def writeBack: Seq[DecoupledIO[MemExuOutput]] = { 1021 writebackSta ++ 1022 writebackHyuLda ++ writebackHyuSta ++ 1023 writebackLda ++ 1024 writebackVldu ++ 1025 writebackStd 1026 } 1027 1028 // store event difftest information 1029 val storeDebugInfo = Vec(EnsbufferWidth, new Bundle { 1030 val robidx = Input(new RobPtr) 1031 val pc = Output(UInt(VAddrBits.W)) 1032 }) 1033} 1034 1035class TopToBackendBundle(implicit p: Parameters) extends XSBundle { 1036 val hartId = Output(UInt(hartIdLen.W)) 1037 val externalInterrupt = Output(new ExternalInterruptIO) 1038 val msiInfo = Output(ValidIO(new MsiInfoBundle)) 1039 val clintTime = Output(ValidIO(UInt(64.W))) 1040 val l2FlushDone = Output(Bool()) 1041} 1042 1043class BackendToTopBundle extends Bundle { 1044 val cpuHalted = Output(Bool()) 1045 val cpuCriticalError = Output(Bool()) 1046} 1047 1048class BackendIO(implicit p: Parameters, params: BackendParams) extends XSBundle with HasSoCParameter { 1049 val fromTop = Flipped(new TopToBackendBundle) 1050 1051 val toTop = new BackendToTopBundle 1052 1053 val traceCoreInterface = new TraceCoreInterface(hasOffset = true) 1054 val fenceio = new FenceIO 1055 // Todo: merge these bundles into BackendFrontendIO 1056 val frontend = Flipped(new FrontendToCtrlIO) 1057 val frontendSfence = Output(new SfenceBundle) 1058 val frontendCsrCtrl = Output(new CustomCSRCtrlIO) 1059 val frontendTlbCsr = Output(new TlbCsrBundle) 1060 val frontendReset = Output(Reset()) 1061 1062 val mem = new BackendMemIO 1063 1064 val perf = Input(new PerfCounterIO) 1065 1066 val tlb = Output(new TlbCsrBundle) 1067 1068 val csrCustomCtrl = Output(new CustomCSRCtrlIO) 1069 1070 val debugTopDown = new Bundle { 1071 val fromRob = new RobCoreTopDownIO 1072 val fromCore = new CoreDispatchTopDownIO 1073 } 1074 val debugRolling = new RobDebugRollingIO 1075 val topDownInfo = new TopDownInfo 1076} 1077