1package xiangshan.backend 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utils.OptionWrapper 7import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 8import utility.{PipelineConnect, ZeroExt} 9import xiangshan._ 10import xiangshan.backend.Bundles.{DynInst, MemExuInput, MemExuOutput} 11import xiangshan.backend.ctrlblock.CtrlBlock 12import xiangshan.backend.datapath.WbConfig._ 13import xiangshan.backend.datapath.{BypassNetwork, DataPath, NewPipelineConnect, WbDataPath, WbFuBusyTable} 14import xiangshan.backend.exu.ExuBlock 15import xiangshan.backend.fu.vector.Bundles.{VConfig, VType} 16import xiangshan.backend.fu.{FenceIO, FenceToSbuffer, FuConfig, PerfCounterIO} 17import xiangshan.backend.issue.{IntScheduler, MemScheduler, Scheduler, VfScheduler} 18import xiangshan.backend.rob.RobLsqIO 19import xiangshan.frontend.{FtqPtr, FtqRead} 20import xiangshan.mem.{LqPtr, LsqEnqIO, SqPtr} 21 22class Backend(val params: BackendParams)(implicit p: Parameters) extends LazyModule 23 with HasXSParameter { 24 25 /* Only update the idx in mem-scheduler here 26 * Idx in other schedulers can be updated the same way if needed 27 * 28 * Also note that we filter out the 'stData issue-queues' when counting 29 */ 30 for ((ibp, idx) <- params.memSchdParams.get.issueBlockParams.filter(iq => iq.StdCnt == 0).zipWithIndex) { 31 ibp.updateIdx(idx) 32 } 33 34 println(params.iqWakeUpParams) 35 36 for ((schdCfg, i) <- params.allSchdParams.zipWithIndex) { 37 schdCfg.bindBackendParam(params) 38 } 39 40 for ((iqCfg, i) <- params.allIssueParams.zipWithIndex) { 41 iqCfg.bindBackendParam(params) 42 } 43 44 for ((exuCfg, i) <- params.allExuParams.zipWithIndex) { 45 exuCfg.updateIQWakeUpConfigs(params.iqWakeUpParams) 46 exuCfg.updateExuIdx(i) 47 exuCfg.bindBackendParam(params) 48 } 49 50 println("[Backend] ExuConfigs:") 51 for (exuCfg <- params.allExuParams) { 52 val fuConfigs = exuCfg.fuConfigs 53 val wbPortConfigs = exuCfg.wbPortConfigs 54 val immType = exuCfg.immType 55 56 println("[Backend] " + 57 s"${exuCfg.name}: " + 58 s"${ fuConfigs.map(_.name).mkString("fu(s): {", ",", "}") }, " + 59 s"${ wbPortConfigs.mkString("wb: {", ",", "}") }, " + 60 s"${ immType.map(SelImm.mkString(_)).mkString("imm: {", "," , "}") }, " + 61 s"latMax(${exuCfg.latencyValMax}), ${exuCfg.fuLatancySet.mkString("lat: {",",","}")}, ") 62 require(wbPortConfigs.collectFirst { case x: IntWB => x }.nonEmpty == 63 fuConfigs.map(_.writeIntRf).reduce(_ || _), 64 "int wb port has no priority" ) 65 require(wbPortConfigs.collectFirst { case x: VfWB => x }.nonEmpty == 66 fuConfigs.map(x => x.writeFpRf || x.writeVecRf).reduce(_ || _), 67 "vec wb port has no priority" ) 68 } 69 70 for (cfg <- FuConfig.allConfigs) { 71 println(s"[Backend] $cfg") 72 } 73 74 val ctrlBlock = LazyModule(new CtrlBlock(params)) 75 val intScheduler = params.intSchdParams.map(x => LazyModule(new Scheduler(x))) 76 val vfScheduler = params.vfSchdParams.map(x => LazyModule(new Scheduler(x))) 77 val memScheduler = params.memSchdParams.map(x => LazyModule(new Scheduler(x))) 78 val dataPath = LazyModule(new DataPath(params)) 79 val intExuBlock = params.intSchdParams.map(x => LazyModule(new ExuBlock(x))) 80 val vfExuBlock = params.vfSchdParams.map(x => LazyModule(new ExuBlock(x))) 81 val wbFuBusyTable = LazyModule(new WbFuBusyTable(params)) 82 83 lazy val module = new BackendImp(this) 84} 85 86class BackendImp(override val wrapper: Backend)(implicit p: Parameters) extends LazyModuleImp(wrapper) 87 with HasXSParameter{ 88 implicit private val params = wrapper.params 89 val io = IO(new BackendIO()(p, wrapper.params)) 90 91 private val ctrlBlock = wrapper.ctrlBlock.module 92 private val intScheduler = wrapper.intScheduler.get.module 93 private val vfScheduler = wrapper.vfScheduler.get.module 94 private val memScheduler = wrapper.memScheduler.get.module 95 private val dataPath = wrapper.dataPath.module 96 private val intExuBlock = wrapper.intExuBlock.get.module 97 private val vfExuBlock = wrapper.vfExuBlock.get.module 98 private val bypassNetwork = Module(new BypassNetwork) 99 private val wbDataPath = Module(new WbDataPath(params)) 100 private val wbFuBusyTable = wrapper.wbFuBusyTable.module 101 102 private val iqWakeUpMappedBundle: Map[String, ValidIO[Bundles.IssueQueueWakeUpBundle]] = ( 103 intScheduler.io.toSchedulers.wakeupVec ++ 104 vfScheduler.io.toSchedulers.wakeupVec ++ 105 memScheduler.io.toSchedulers.wakeupVec 106 ).map(x => (x.bits.wakeupSource, x)).toMap 107 108 println(s"[Backend] iq wake up keys: ${iqWakeUpMappedBundle.keys}") 109 110 wbFuBusyTable.io.in.intSchdBusyTable := intScheduler.io.wbFuBusyTable 111 wbFuBusyTable.io.in.vfSchdBusyTable := vfScheduler.io.wbFuBusyTable 112 wbFuBusyTable.io.in.memSchdBusyTable := memScheduler.io.wbFuBusyTable 113 intScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.intRespRead 114 vfScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.vfRespRead 115 memScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.memRespRead 116 dataPath.io.wbConfictRead := wbFuBusyTable.io.out.wbConflictRead 117 118 wbDataPath.io.fromIntExu.flatten.filter(x => x.bits.params.writeIntRf) 119 120 private val vconfig = dataPath.io.vconfigReadPort.data 121 122 ctrlBlock.io.fromTop.hartId := io.fromTop.hartId 123 ctrlBlock.io.frontend <> io.frontend 124 ctrlBlock.io.fromWB.wbData <> wbDataPath.io.toCtrlBlock.writeback 125 ctrlBlock.io.fromMem.stIn <> io.mem.stIn 126 ctrlBlock.io.fromMem.violation <> io.mem.memoryViolation 127 ctrlBlock.io.csrCtrl <> intExuBlock.io.csrio.get.customCtrl 128 ctrlBlock.io.robio.csr.intrBitSet := intExuBlock.io.csrio.get.interrupt 129 ctrlBlock.io.robio.csr.trapTarget := intExuBlock.io.csrio.get.trapTarget 130 ctrlBlock.io.robio.csr.isXRet := intExuBlock.io.csrio.get.isXRet 131 ctrlBlock.io.robio.csr.wfiEvent := intExuBlock.io.csrio.get.wfi_event 132 ctrlBlock.io.robio.lsq <> io.mem.robLsqIO 133 ctrlBlock.io.fromDataPath.vtype := vconfig(7, 0).asTypeOf(new VType) 134 135 intScheduler.io.fromTop.hartId := io.fromTop.hartId 136 intScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 137 intScheduler.io.fromCtrlBlock.pcVec := ctrlBlock.io.toIssueBlock.pcVec 138 intScheduler.io.fromCtrlBlock.targetVec := ctrlBlock.io.toIssueBlock.targetVec 139 intScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 140 intScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.intUops 141 intScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 142 intScheduler.io.vfWriteBack := 0.U.asTypeOf(intScheduler.io.vfWriteBack) 143 intScheduler.io.fromDataPath := dataPath.io.toIntIQ 144 intScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.wakeupSource) } 145 146 memScheduler.io.fromTop.hartId := io.fromTop.hartId 147 memScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 148 memScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 149 memScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.memUops 150 memScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 151 memScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 152 memScheduler.io.fromMem.get.scommit := io.mem.sqDeq 153 memScheduler.io.fromMem.get.lcommit := io.mem.lqDeq 154 memScheduler.io.fromMem.get.sqCancelCnt := io.mem.sqCancelCnt 155 memScheduler.io.fromMem.get.lqCancelCnt := io.mem.lqCancelCnt 156 memScheduler.io.fromMem.get.stIssuePtr := io.mem.stIssuePtr 157 memScheduler.io.fromMem.get.memWaitUpdateReq.staIssue.zip(io.mem.stIn).foreach { case (sink, source) => 158 sink.valid := source.valid 159 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 160 sink.bits.uop.robIdx := source.bits.robIdx 161 } 162 memScheduler.io.fromDataPath := dataPath.io.toMemIQ 163 memScheduler.io.fromMem.get.ldaFeedback := io.mem.ldaIqFeedback 164 memScheduler.io.fromMem.get.staFeedback := io.mem.staIqFeedback 165 memScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.wakeupSource) } 166 167 vfScheduler.io.fromTop.hartId := io.fromTop.hartId 168 vfScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 169 vfScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 170 vfScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.vfUops 171 vfScheduler.io.intWriteBack := 0.U.asTypeOf(vfScheduler.io.intWriteBack) 172 vfScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 173 vfScheduler.io.fromDataPath := dataPath.io.toVfIQ 174 vfScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.wakeupSource) } 175 176 dataPath.io.flush := ctrlBlock.io.toDataPath.flush 177 dataPath.io.vconfigReadPort.addr := ctrlBlock.io.toDataPath.vtypeAddr 178 179 for (i <- 0 until dataPath.io.fromIntIQ.length) { 180 for (j <- 0 until dataPath.io.fromIntIQ(i).length) { 181 NewPipelineConnect(intScheduler.io.toDataPath(i)(j), dataPath.io.fromIntIQ(i)(j), dataPath.io.fromIntIQ(i)(j).valid, 182 intScheduler.io.toDataPath(i)(j).bits.common.robIdx.needFlush(ctrlBlock.io.toDataPath.flush), Option("intScheduler2DataPathPipe")) 183 } 184 } 185 186 for (i <- 0 until dataPath.io.fromVfIQ.length) { 187 for (j <- 0 until dataPath.io.fromVfIQ(i).length) { 188 NewPipelineConnect(vfScheduler.io.toDataPath(i)(j), dataPath.io.fromVfIQ(i)(j), dataPath.io.fromVfIQ(i)(j).valid, 189 vfScheduler.io.toDataPath(i)(j).bits.common.robIdx.needFlush(ctrlBlock.io.toDataPath.flush), Option("vfScheduler2DataPathPipe")) 190 } 191 } 192 193 for (i <- 0 until dataPath.io.fromMemIQ.length) { 194 for (j <- 0 until dataPath.io.fromMemIQ(i).length) { 195 NewPipelineConnect(memScheduler.io.toDataPath(i)(j), dataPath.io.fromMemIQ(i)(j), dataPath.io.fromMemIQ(i)(j).valid, 196 memScheduler.io.toDataPath(i)(j).bits.common.robIdx.needFlush(ctrlBlock.io.toDataPath.flush), Option("memScheduler2DataPathPipe")) 197 } 198 } 199 200 println(s"[Backend] wbDataPath.io.toIntPreg: ${wbDataPath.io.toIntPreg.size}, dataPath.io.fromIntWb: ${dataPath.io.fromIntWb.size}") 201 println(s"[Backend] wbDataPath.io.toVfPreg: ${wbDataPath.io.toVfPreg.size}, dataPath.io.fromFpWb: ${dataPath.io.fromVfWb.size}") 202 dataPath.io.fromIntWb := wbDataPath.io.toIntPreg 203 dataPath.io.fromVfWb := wbDataPath.io.toVfPreg 204 dataPath.io.debugIntRat := ctrlBlock.io.debug_int_rat 205 dataPath.io.debugFpRat := ctrlBlock.io.debug_fp_rat 206 dataPath.io.debugVecRat := ctrlBlock.io.debug_vec_rat 207 dataPath.io.debugVconfigRat := ctrlBlock.io.debug_vconfig_rat 208 209 bypassNetwork.io.fromDataPath.int <> dataPath.io.toIntExu 210 bypassNetwork.io.fromDataPath.vf <> dataPath.io.toFpExu 211 bypassNetwork.io.fromDataPath.mem <> dataPath.io.toMemExu 212 bypassNetwork.io.fromExus.connectExuOutput(_.int)(intExuBlock.io.out) 213 bypassNetwork.io.fromExus.connectExuOutput(_.vf)(vfExuBlock.io.out) 214 bypassNetwork.io.fromExus.mem.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 215 sink.valid := source.valid 216 sink.bits.pdest := source.bits.uop.pdest 217 sink.bits.data := source.bits.data 218 } 219 220 intExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 221 for (i <- 0 until intExuBlock.io.in.length) { 222 for (j <- 0 until intExuBlock.io.in(i).length) { 223 NewPipelineConnect(bypassNetwork.io.toExus.int(i)(j), intExuBlock.io.in(i)(j), intExuBlock.io.in(i)(j).fire, 224 Mux(bypassNetwork.io.toExus.int(i)(j).fire, 225 bypassNetwork.io.toExus.int(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush), 226 intExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush))) 227 } 228 } 229 230 private val csrio = intExuBlock.io.csrio.get 231 csrio.hartId := io.fromTop.hartId 232 csrio.perf.retiredInstr <> ctrlBlock.io.robio.csr.perfinfo.retiredInstr 233 csrio.perf.ctrlInfo <> ctrlBlock.io.perfInfo.ctrlInfo 234 csrio.perf.perfEventsCtrl <> ctrlBlock.getPerf 235 csrio.fpu.fflags := ctrlBlock.io.robio.csr.fflags 236 csrio.fpu.isIllegal := false.B // Todo: remove it 237 csrio.fpu.dirty_fs := ctrlBlock.io.robio.csr.dirty_fs 238 csrio.vpu <> 0.U.asTypeOf(csrio.vpu) // Todo 239 240 val debugVconfig = dataPath.io.debugVconfig.asTypeOf(new VConfig) 241 val debugVtype = VType.toVtypeStruct(debugVconfig.vtype).asUInt 242 val debugVl = debugVconfig.vl 243 csrio.vpu.set_vxsat := ctrlBlock.io.robio.csr.vxsat 244 csrio.vpu.set_vstart.valid := ctrlBlock.io.robio.csr.vcsrFlag 245 csrio.vpu.set_vstart.bits := 0.U 246 csrio.vpu.set_vtype.valid := ctrlBlock.io.robio.csr.vcsrFlag 247 csrio.vpu.set_vtype.bits := ZeroExt(debugVtype, XLEN) 248 csrio.vpu.set_vl.valid := ctrlBlock.io.robio.csr.vcsrFlag 249 csrio.vpu.set_vl.bits := ZeroExt(debugVl, XLEN) 250 csrio.exception := ctrlBlock.io.robio.exception 251 csrio.memExceptionVAddr := io.mem.exceptionVAddr 252 csrio.externalInterrupt := io.fromTop.externalInterrupt 253 csrio.distributedUpdate(0) := io.mem.csrDistributedUpdate 254 csrio.distributedUpdate(1) := io.frontendCsrDistributedUpdate 255 csrio.perf <> io.perf 256 private val fenceio = intExuBlock.io.fenceio.get 257 fenceio.disableSfence := csrio.disableSfence 258 io.fenceio <> fenceio 259 260 vfExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 261 for (i <- 0 until vfExuBlock.io.in.size) { 262 for (j <- 0 until vfExuBlock.io.in(i).size) { 263 NewPipelineConnect(bypassNetwork.io.toExus.vf(i)(j), vfExuBlock.io.in(i)(j), vfExuBlock.io.in(i)(j).fire, 264 Mux(bypassNetwork.io.toExus.vf(i)(j).fire, 265 bypassNetwork.io.toExus.vf(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush), 266 vfExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush))) 267 } 268 } 269 vfExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 270 271 wbDataPath.io.flush := ctrlBlock.io.redirect 272 wbDataPath.io.fromTop.hartId := io.fromTop.hartId 273 wbDataPath.io.fromIntExu <> intExuBlock.io.out 274 wbDataPath.io.fromVfExu <> vfExuBlock.io.out 275 wbDataPath.io.fromMemExu.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 276 sink.valid := source.valid 277 source.ready := sink.ready 278 sink.bits.data := source.bits.data 279 sink.bits.pdest := source.bits.uop.pdest 280 sink.bits.robIdx := source.bits.uop.robIdx 281 sink.bits.intWen.foreach(_ := source.bits.uop.rfWen) 282 sink.bits.fpWen.foreach(_ := source.bits.uop.fpWen) 283 sink.bits.vecWen.foreach(_ := source.bits.uop.vecWen) 284 sink.bits.exceptionVec.foreach(_ := source.bits.uop.exceptionVec) 285 sink.bits.flushPipe.foreach(_ := source.bits.uop.flushPipe) 286 sink.bits.replay.foreach(_ := source.bits.uop.replayInst) 287 sink.bits.debug := source.bits.debug 288 sink.bits.debugInfo := 0.U.asTypeOf(sink.bits.debugInfo) 289 sink.bits.lqIdx.foreach(_ := source.bits.uop.lqIdx) 290 sink.bits.sqIdx.foreach(_ := source.bits.uop.sqIdx) 291 sink.bits.ftqIdx.foreach(_ := source.bits.uop.ftqPtr) 292 sink.bits.ftqOffset.foreach(_ := source.bits.uop.ftqOffset) 293 } 294 295 // to mem 296 private val toMem = Wire(bypassNetwork.io.toExus.mem.cloneType) 297 for (i <- toMem.indices) { 298 for (j <- toMem(i).indices) { 299 NewPipelineConnect( 300 bypassNetwork.io.toExus.mem(i)(j), toMem(i)(j), toMem(i)(j).fire, 301 Mux( 302 bypassNetwork.io.toExus.mem(i)(j).fire, 303 bypassNetwork.io.toExus.mem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush), 304 toMem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 305 ) 306 ) 307 } 308 } 309 310 io.mem.redirect := ctrlBlock.io.redirect 311 io.mem.issueUops.zip(toMem.flatten).foreach { case (sink, source) => 312 sink.valid := source.valid 313 source.ready := sink.ready 314 sink.bits.iqIdx := source.bits.iqIdx 315 sink.bits.isFirstIssue := source.bits.isFirstIssue 316 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 317 sink.bits.src := 0.U.asTypeOf(sink.bits.src) 318 sink.bits.src.zip(source.bits.src).foreach { case (l, r) => l := r} 319 sink.bits.uop.fuType := source.bits.fuType 320 sink.bits.uop.fuOpType := source.bits.fuOpType 321 sink.bits.uop.imm := source.bits.imm 322 sink.bits.uop.robIdx := source.bits.robIdx 323 sink.bits.uop.pdest := source.bits.pdest 324 sink.bits.uop.rfWen := source.bits.rfWen.getOrElse(false.B) 325 sink.bits.uop.fpWen := source.bits.fpWen.getOrElse(false.B) 326 sink.bits.uop.vecWen := source.bits.vecWen.getOrElse(false.B) 327 sink.bits.uop.flushPipe := source.bits.flushPipe.getOrElse(false.B) 328 sink.bits.uop.pc := source.bits.pc.getOrElse(0.U) 329 sink.bits.uop.lqIdx := source.bits.lqIdx.getOrElse(0.U.asTypeOf(new LqPtr)) 330 sink.bits.uop.sqIdx := source.bits.sqIdx.getOrElse(0.U.asTypeOf(new SqPtr)) 331 sink.bits.uop.ftqPtr := source.bits.ftqIdx.getOrElse(0.U.asTypeOf(new FtqPtr)) 332 sink.bits.uop.ftqOffset := source.bits.ftqOffset.getOrElse(0.U) 333 } 334 io.mem.loadFastMatch := memScheduler.io.toMem.get.loadFastMatch.map(_.fastMatch) 335 io.mem.loadFastImm := memScheduler.io.toMem.get.loadFastMatch.map(_.fastImm) 336 io.mem.tlbCsr := csrio.tlb 337 io.mem.csrCtrl := csrio.customCtrl 338 io.mem.sfence := fenceio.sfence 339 io.mem.isStoreException := CommitType.lsInstIsStore(ctrlBlock.io.robio.exception.bits.commitType) 340 require(io.mem.loadPcRead.size == params.LduCnt) 341 io.mem.loadPcRead.zipWithIndex.foreach { case (loadPcRead, i) => 342 loadPcRead.data := ctrlBlock.io.memLdPcRead(i).data 343 ctrlBlock.io.memLdPcRead(i).ptr := loadPcRead.ptr 344 ctrlBlock.io.memLdPcRead(i).offset := loadPcRead.offset 345 } 346 // mem io 347 io.mem.lsqEnqIO <> memScheduler.io.memIO.get.lsqEnqIO 348 io.mem.robLsqIO <> ctrlBlock.io.robio.lsq 349 io.mem.toSbuffer <> fenceio.sbuffer 350 351 io.frontendSfence := fenceio.sfence 352 io.frontendTlbCsr := csrio.tlb 353 io.frontendCsrCtrl := csrio.customCtrl 354 355 io.tlb <> csrio.tlb 356 357 io.csrCustomCtrl := csrio.customCtrl 358 359 dontTouch(memScheduler.io) 360 dontTouch(io.mem) 361 dontTouch(dataPath.io.toMemExu) 362 dontTouch(wbDataPath.io.fromMemExu) 363} 364 365class BackendMemIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 366 // params alias 367 private val LoadQueueSize = VirtualLoadQueueSize 368 // In/Out // Todo: split it into one-direction bundle 369 val lsqEnqIO = Flipped(new LsqEnqIO) 370 val robLsqIO = new RobLsqIO 371 val toSbuffer = new FenceToSbuffer 372 val ldaIqFeedback = Vec(params.LduCnt, Flipped(new MemRSFeedbackIO)) 373 val staIqFeedback = Vec(params.StaCnt, Flipped(new MemRSFeedbackIO)) 374 val loadPcRead = Vec(params.LduCnt, Flipped(new FtqRead(UInt(VAddrBits.W)))) 375 376 // Input 377 val writeBack = MixedVec(Seq.fill(params.LduCnt + params.StaCnt * 2)(Flipped(DecoupledIO(new MemExuOutput()))) ++ Seq.fill(params.VlduCnt)(Flipped(DecoupledIO(new MemExuOutput(true))))) 378 379 val s3_delayed_load_error = Input(Vec(LoadPipelineWidth, Bool())) 380 val stIn = Input(Vec(params.StaCnt, ValidIO(new DynInst()))) 381 val memoryViolation = Flipped(ValidIO(new Redirect)) 382 val exceptionVAddr = Input(UInt(VAddrBits.W)) 383 val sqDeq = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) 384 val lqDeq = Input(UInt(log2Up(CommitWidth + 1).W)) 385 386 val lqCancelCnt = Input(UInt(log2Up(VirtualLoadQueueSize + 1).W)) 387 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 388 389 val otherFastWakeup = Flipped(Vec(params.LduCnt + 2 * params.StaCnt, ValidIO(new DynInst))) 390 val stIssuePtr = Input(new SqPtr()) 391 392 val csrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 393 394 // Output 395 val redirect = ValidIO(new Redirect) // rob flush MemBlock 396 val issueUops = MixedVec(Seq.fill(params.LduCnt + params.StaCnt * 2)(DecoupledIO(new MemExuInput())) ++ Seq.fill(params.VlduCnt)(DecoupledIO(new MemExuInput(true)))) 397 val loadFastMatch = Vec(params.LduCnt, Output(UInt(params.LduCnt.W))) 398 val loadFastImm = Vec(params.LduCnt, Output(UInt(12.W))) // Imm_I 399 400 val tlbCsr = Output(new TlbCsrBundle) 401 val csrCtrl = Output(new CustomCSRCtrlIO) 402 val sfence = Output(new SfenceBundle) 403 val isStoreException = Output(Bool()) 404} 405 406class BackendIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 407 val fromTop = new Bundle { 408 val hartId = Input(UInt(8.W)) 409 val externalInterrupt = new ExternalInterruptIO 410 } 411 412 val toTop = new Bundle { 413 val cpuHalted = Output(Bool()) 414 } 415 416 val fenceio = new FenceIO 417 // Todo: merge these bundles into BackendFrontendIO 418 val frontend = Flipped(new FrontendToCtrlIO) 419 val frontendSfence = Output(new SfenceBundle) 420 val frontendCsrCtrl = Output(new CustomCSRCtrlIO) 421 val frontendTlbCsr = Output(new TlbCsrBundle) 422 // distributed csr write 423 val frontendCsrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 424 425 val mem = new BackendMemIO 426 427 val perf = Input(new PerfCounterIO) 428 429 val tlb = Output(new TlbCsrBundle) 430 431 val csrCustomCtrl = Output(new CustomCSRCtrlIO) 432} 433