1package xiangshan.backend 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utils.OptionWrapper 7import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 8import utility.ZeroExt 9import xiangshan._ 10import xiangshan.backend.Bundles.{DynInst, IssueQueueIQWakeUpBundle, MemExuInput, MemExuOutput} 11import xiangshan.backend.ctrlblock.CtrlBlock 12import xiangshan.backend.datapath.WbConfig._ 13import xiangshan.backend.datapath.{BypassNetwork, DataPath, NewPipelineConnect, WbDataPath, WbFuBusyTable} 14import xiangshan.backend.exu.ExuBlock 15import xiangshan.backend.fu.vector.Bundles.{VConfig, VType} 16import xiangshan.backend.fu.{FenceIO, FenceToSbuffer, FuConfig, PerfCounterIO} 17import xiangshan.backend.issue.{CancelNetwork, Scheduler} 18import xiangshan.backend.rob.RobLsqIO 19import xiangshan.frontend.{FtqPtr, FtqRead} 20import xiangshan.mem.{LqPtr, LsqEnqIO, SqPtr} 21 22class Backend(val params: BackendParams)(implicit p: Parameters) extends LazyModule 23 with HasXSParameter { 24 25 /* Only update the idx in mem-scheduler here 26 * Idx in other schedulers can be updated the same way if needed 27 * 28 * Also note that we filter out the 'stData issue-queues' when counting 29 */ 30 for ((ibp, idx) <- params.memSchdParams.get.issueBlockParams.filter(iq => iq.StdCnt == 0).zipWithIndex) { 31 ibp.updateIdx(idx) 32 } 33 34 println(params.iqWakeUpParams) 35 36 for ((schdCfg, i) <- params.allSchdParams.zipWithIndex) { 37 schdCfg.bindBackendParam(params) 38 } 39 40 for ((iqCfg, i) <- params.allIssueParams.zipWithIndex) { 41 iqCfg.bindBackendParam(params) 42 } 43 44 for ((exuCfg, i) <- params.allExuParams.zipWithIndex) { 45 exuCfg.updateIQWakeUpConfigs(params.iqWakeUpParams) 46 exuCfg.updateExuIdx(i) 47 exuCfg.bindBackendParam(params) 48 } 49 50 println("[Backend] ExuConfigs:") 51 for (exuCfg <- params.allExuParams) { 52 val fuConfigs = exuCfg.fuConfigs 53 val wbPortConfigs = exuCfg.wbPortConfigs 54 val immType = exuCfg.immType 55 56 println("[Backend] " + 57 s"${exuCfg.name}: " + 58 s"${fuConfigs.map(_.name).mkString("fu(s): {", ",", "}")}, " + 59 s"${wbPortConfigs.mkString("wb: {", ",", "}")}, " + 60 s"${immType.map(SelImm.mkString(_)).mkString("imm: {", ",", "}")}, " + 61 s"latMax(${exuCfg.latencyValMax}), ${exuCfg.fuLatancySet.mkString("lat: {", ",", "}")}, " 62 ) 63 require( 64 wbPortConfigs.collectFirst { case x: IntWB => x }.nonEmpty == 65 fuConfigs.map(_.writeIntRf).reduce(_ || _), 66 "int wb port has no priority" 67 ) 68 require( 69 wbPortConfigs.collectFirst { case x: VfWB => x }.nonEmpty == 70 fuConfigs.map(x => x.writeFpRf || x.writeVecRf).reduce(_ || _), 71 "vec wb port has no priority" 72 ) 73 } 74 75 for (cfg <- FuConfig.allConfigs) { 76 println(s"[Backend] $cfg") 77 } 78 79 val ctrlBlock = LazyModule(new CtrlBlock(params)) 80 val intScheduler = params.intSchdParams.map(x => LazyModule(new Scheduler(x))) 81 val vfScheduler = params.vfSchdParams.map(x => LazyModule(new Scheduler(x))) 82 val memScheduler = params.memSchdParams.map(x => LazyModule(new Scheduler(x))) 83 val cancelNetwork = LazyModule(new CancelNetwork(params)) 84 val dataPath = LazyModule(new DataPath(params)) 85 val intExuBlock = params.intSchdParams.map(x => LazyModule(new ExuBlock(x))) 86 val vfExuBlock = params.vfSchdParams.map(x => LazyModule(new ExuBlock(x))) 87 val wbFuBusyTable = LazyModule(new WbFuBusyTable(params)) 88 89 lazy val module = new BackendImp(this) 90} 91 92class BackendImp(override val wrapper: Backend)(implicit p: Parameters) extends LazyModuleImp(wrapper) 93 with HasXSParameter { 94 implicit private val params = wrapper.params 95 val io = IO(new BackendIO()(p, wrapper.params)) 96 97 private val ctrlBlock = wrapper.ctrlBlock.module 98 private val intScheduler = wrapper.intScheduler.get.module 99 private val vfScheduler = wrapper.vfScheduler.get.module 100 private val memScheduler = wrapper.memScheduler.get.module 101 private val cancelNetwork = wrapper.cancelNetwork.module 102 private val dataPath = wrapper.dataPath.module 103 private val intExuBlock = wrapper.intExuBlock.get.module 104 private val vfExuBlock = wrapper.vfExuBlock.get.module 105 private val bypassNetwork = Module(new BypassNetwork) 106 private val wbDataPath = Module(new WbDataPath(params)) 107 private val wbFuBusyTable = wrapper.wbFuBusyTable.module 108 109 private val iqWakeUpMappedBundle: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = ( 110 intScheduler.io.toSchedulers.wakeupVec ++ 111 vfScheduler.io.toSchedulers.wakeupVec ++ 112 memScheduler.io.toSchedulers.wakeupVec 113 ).map(x => (x.bits.exuIdx, x)).toMap 114 115 println(s"[Backend] iq wake up keys: ${iqWakeUpMappedBundle.keys}") 116 117 wbFuBusyTable.io.in.intSchdBusyTable := intScheduler.io.wbFuBusyTable 118 wbFuBusyTable.io.in.vfSchdBusyTable := vfScheduler.io.wbFuBusyTable 119 wbFuBusyTable.io.in.memSchdBusyTable := memScheduler.io.wbFuBusyTable 120 intScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.intRespRead 121 vfScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.vfRespRead 122 memScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.memRespRead 123 dataPath.io.wbConfictRead := wbFuBusyTable.io.out.wbConflictRead 124 125 wbDataPath.io.fromIntExu.flatten.filter(x => x.bits.params.writeIntRf) 126 127 private val vconfig = dataPath.io.vconfigReadPort.data 128 private val og1CancelVec: Vec[Bool] = dataPath.io.og1CancelVec 129 private val og0CancelVecFromDataPath: Vec[Bool] = dataPath.io.og0CancelVec 130 private val og0CancelVecFromCancelNet: Vec[Bool] = cancelNetwork.io.out.og0CancelVec 131 private val og0CancelVec: Vec[Bool] = VecInit(og0CancelVecFromDataPath.zip(og0CancelVecFromCancelNet).map(x => x._1 | x._2)) 132 dontTouch(og0CancelVecFromDataPath) 133 dontTouch(og0CancelVecFromCancelNet) 134 dontTouch(og0CancelVec) 135 dontTouch(og1CancelVec) 136 137 ctrlBlock.io.fromTop.hartId := io.fromTop.hartId 138 ctrlBlock.io.frontend <> io.frontend 139 ctrlBlock.io.fromWB.wbData <> wbDataPath.io.toCtrlBlock.writeback 140 ctrlBlock.io.fromMem.stIn <> io.mem.stIn 141 ctrlBlock.io.fromMem.violation <> io.mem.memoryViolation 142 ctrlBlock.io.csrCtrl <> intExuBlock.io.csrio.get.customCtrl 143 ctrlBlock.io.robio.csr.intrBitSet := intExuBlock.io.csrio.get.interrupt 144 ctrlBlock.io.robio.csr.trapTarget := intExuBlock.io.csrio.get.trapTarget 145 ctrlBlock.io.robio.csr.isXRet := intExuBlock.io.csrio.get.isXRet 146 ctrlBlock.io.robio.csr.wfiEvent := intExuBlock.io.csrio.get.wfi_event 147 ctrlBlock.io.robio.lsq <> io.mem.robLsqIO 148 ctrlBlock.io.fromDataPath.vtype := vconfig(7, 0).asTypeOf(new VType) 149 150 intScheduler.io.fromTop.hartId := io.fromTop.hartId 151 intScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 152 intScheduler.io.fromCtrlBlock.pcVec := ctrlBlock.io.toIssueBlock.pcVec 153 intScheduler.io.fromCtrlBlock.targetVec := ctrlBlock.io.toIssueBlock.targetVec 154 intScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 155 intScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.intUops 156 intScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 157 intScheduler.io.vfWriteBack := 0.U.asTypeOf(intScheduler.io.vfWriteBack) 158 intScheduler.io.fromDataPath.resp := dataPath.io.toIntIQ 159 intScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 160 intScheduler.io.fromDataPath.og0Cancel := og0CancelVec 161 intScheduler.io.fromDataPath.og1Cancel := og1CancelVec 162 163 memScheduler.io.fromTop.hartId := io.fromTop.hartId 164 memScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 165 memScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 166 memScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.memUops 167 memScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 168 memScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 169 memScheduler.io.fromMem.get.scommit := io.mem.sqDeq 170 memScheduler.io.fromMem.get.lcommit := io.mem.lqDeq 171 memScheduler.io.fromMem.get.sqCancelCnt := io.mem.sqCancelCnt 172 memScheduler.io.fromMem.get.lqCancelCnt := io.mem.lqCancelCnt 173 memScheduler.io.fromMem.get.stIssuePtr := io.mem.stIssuePtr 174 memScheduler.io.fromMem.get.memWaitUpdateReq.staIssue.zip(io.mem.stIn).foreach { case (sink, source) => 175 sink.valid := source.valid 176 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 177 sink.bits.uop.robIdx := source.bits.robIdx 178 } 179 memScheduler.io.fromDataPath.resp := dataPath.io.toMemIQ 180 memScheduler.io.fromMem.get.ldaFeedback := io.mem.ldaIqFeedback 181 memScheduler.io.fromMem.get.staFeedback := io.mem.staIqFeedback 182 memScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 183 memScheduler.io.fromDataPath.og0Cancel := og0CancelVec 184 memScheduler.io.fromDataPath.og1Cancel := og1CancelVec 185 186 vfScheduler.io.fromTop.hartId := io.fromTop.hartId 187 vfScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 188 vfScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 189 vfScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.vfUops 190 vfScheduler.io.intWriteBack := 0.U.asTypeOf(vfScheduler.io.intWriteBack) 191 vfScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 192 vfScheduler.io.fromDataPath.resp := dataPath.io.toVfIQ 193 vfScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 194 vfScheduler.io.fromDataPath.og0Cancel := og0CancelVec 195 vfScheduler.io.fromDataPath.og1Cancel := og1CancelVec 196 197 cancelNetwork.io.in.int <> intScheduler.io.toDataPath 198 cancelNetwork.io.in.vf <> vfScheduler.io.toDataPath 199 cancelNetwork.io.in.mem <> memScheduler.io.toDataPath 200 cancelNetwork.io.in.og0CancelVec := og0CancelVecFromDataPath 201 cancelNetwork.io.in.og1CancelVec := og1CancelVec 202 intScheduler.io.fromCancelNetwork <> cancelNetwork.io.out.int 203 vfScheduler.io.fromCancelNetwork <> cancelNetwork.io.out.vf 204 memScheduler.io.fromCancelNetwork <> cancelNetwork.io.out.mem 205 206 dataPath.io.flush := ctrlBlock.io.toDataPath.flush 207 dataPath.io.vconfigReadPort.addr := ctrlBlock.io.toDataPath.vtypeAddr 208 209 dataPath.io.fromIntIQ <> intScheduler.io.toDataPathAfterDelay 210 dataPath.io.fromVfIQ <> vfScheduler.io.toDataPathAfterDelay 211 dataPath.io.fromMemIQ <> memScheduler.io.toDataPathAfterDelay 212 213 println(s"[Backend] wbDataPath.io.toIntPreg: ${wbDataPath.io.toIntPreg.size}, dataPath.io.fromIntWb: ${dataPath.io.fromIntWb.size}") 214 println(s"[Backend] wbDataPath.io.toVfPreg: ${wbDataPath.io.toVfPreg.size}, dataPath.io.fromFpWb: ${dataPath.io.fromVfWb.size}") 215 dataPath.io.fromIntWb := wbDataPath.io.toIntPreg 216 dataPath.io.fromVfWb := wbDataPath.io.toVfPreg 217 dataPath.io.debugIntRat := ctrlBlock.io.debug_int_rat 218 dataPath.io.debugFpRat := ctrlBlock.io.debug_fp_rat 219 dataPath.io.debugVecRat := ctrlBlock.io.debug_vec_rat 220 dataPath.io.debugVconfigRat := ctrlBlock.io.debug_vconfig_rat 221 222 bypassNetwork.io.fromDataPath.int <> dataPath.io.toIntExu 223 bypassNetwork.io.fromDataPath.vf <> dataPath.io.toFpExu 224 bypassNetwork.io.fromDataPath.mem <> dataPath.io.toMemExu 225 bypassNetwork.io.fromExus.connectExuOutput(_.int)(intExuBlock.io.out) 226 bypassNetwork.io.fromExus.connectExuOutput(_.vf)(vfExuBlock.io.out) 227 bypassNetwork.io.fromExus.mem.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 228 sink.valid := source.valid 229 sink.bits.pdest := source.bits.uop.pdest 230 sink.bits.data := source.bits.data 231 } 232 233 intExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 234 for (i <- 0 until intExuBlock.io.in.length) { 235 for (j <- 0 until intExuBlock.io.in(i).length) { 236 NewPipelineConnect( 237 bypassNetwork.io.toExus.int(i)(j), intExuBlock.io.in(i)(j), intExuBlock.io.in(i)(j).fire, 238 Mux( 239 bypassNetwork.io.toExus.int(i)(j).fire, 240 bypassNetwork.io.toExus.int(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush), 241 intExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 242 ) 243 ) 244 } 245 } 246 247 private val csrio = intExuBlock.io.csrio.get 248 csrio.hartId := io.fromTop.hartId 249 csrio.perf.retiredInstr <> ctrlBlock.io.robio.csr.perfinfo.retiredInstr 250 csrio.perf.ctrlInfo <> ctrlBlock.io.perfInfo.ctrlInfo 251 csrio.perf.perfEventsCtrl <> ctrlBlock.getPerf 252 csrio.fpu.fflags := ctrlBlock.io.robio.csr.fflags 253 csrio.fpu.isIllegal := false.B // Todo: remove it 254 csrio.fpu.dirty_fs := ctrlBlock.io.robio.csr.dirty_fs 255 csrio.vpu <> 0.U.asTypeOf(csrio.vpu) // Todo 256 257 val debugVconfig = dataPath.io.debugVconfig.asTypeOf(new VConfig) 258 val debugVtype = VType.toVtypeStruct(debugVconfig.vtype).asUInt 259 val debugVl = debugVconfig.vl 260 csrio.vpu.set_vxsat := ctrlBlock.io.robio.csr.vxsat 261 csrio.vpu.set_vstart.valid := ctrlBlock.io.robio.csr.vcsrFlag 262 csrio.vpu.set_vstart.bits := 0.U 263 csrio.vpu.set_vtype.valid := ctrlBlock.io.robio.csr.vcsrFlag 264 csrio.vpu.set_vtype.bits := ZeroExt(debugVtype, XLEN) 265 csrio.vpu.set_vl.valid := ctrlBlock.io.robio.csr.vcsrFlag 266 csrio.vpu.set_vl.bits := ZeroExt(debugVl, XLEN) 267 csrio.exception := ctrlBlock.io.robio.exception 268 csrio.memExceptionVAddr := io.mem.exceptionVAddr 269 csrio.externalInterrupt := io.fromTop.externalInterrupt 270 csrio.distributedUpdate(0) := io.mem.csrDistributedUpdate 271 csrio.distributedUpdate(1) := io.frontendCsrDistributedUpdate 272 csrio.perf <> io.perf 273 private val fenceio = intExuBlock.io.fenceio.get 274 fenceio.disableSfence := csrio.disableSfence 275 io.fenceio <> fenceio 276 277 vfExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 278 for (i <- 0 until vfExuBlock.io.in.size) { 279 for (j <- 0 until vfExuBlock.io.in(i).size) { 280 NewPipelineConnect( 281 bypassNetwork.io.toExus.vf(i)(j), vfExuBlock.io.in(i)(j), vfExuBlock.io.in(i)(j).fire, 282 Mux( 283 bypassNetwork.io.toExus.vf(i)(j).fire, 284 bypassNetwork.io.toExus.vf(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush), 285 vfExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 286 ) 287 ) 288 } 289 } 290 vfExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 291 292 wbDataPath.io.flush := ctrlBlock.io.redirect 293 wbDataPath.io.fromTop.hartId := io.fromTop.hartId 294 wbDataPath.io.fromIntExu <> intExuBlock.io.out 295 wbDataPath.io.fromVfExu <> vfExuBlock.io.out 296 wbDataPath.io.fromMemExu.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 297 sink.valid := source.valid 298 source.ready := sink.ready 299 sink.bits.data := source.bits.data 300 sink.bits.pdest := source.bits.uop.pdest 301 sink.bits.robIdx := source.bits.uop.robIdx 302 sink.bits.intWen.foreach(_ := source.bits.uop.rfWen) 303 sink.bits.fpWen.foreach(_ := source.bits.uop.fpWen) 304 sink.bits.vecWen.foreach(_ := source.bits.uop.vecWen) 305 sink.bits.exceptionVec.foreach(_ := source.bits.uop.exceptionVec) 306 sink.bits.flushPipe.foreach(_ := source.bits.uop.flushPipe) 307 sink.bits.replay.foreach(_ := source.bits.uop.replayInst) 308 sink.bits.debug := source.bits.debug 309 sink.bits.debugInfo := 0.U.asTypeOf(sink.bits.debugInfo) 310 sink.bits.lqIdx.foreach(_ := source.bits.uop.lqIdx) 311 sink.bits.sqIdx.foreach(_ := source.bits.uop.sqIdx) 312 sink.bits.ftqIdx.foreach(_ := source.bits.uop.ftqPtr) 313 sink.bits.ftqOffset.foreach(_ := source.bits.uop.ftqOffset) 314 } 315 316 // to mem 317 private val toMem = Wire(bypassNetwork.io.toExus.mem.cloneType) 318 for (i <- toMem.indices) { 319 for (j <- toMem(i).indices) { 320 NewPipelineConnect( 321 bypassNetwork.io.toExus.mem(i)(j), toMem(i)(j), toMem(i)(j).fire, 322 Mux( 323 bypassNetwork.io.toExus.mem(i)(j).fire, 324 bypassNetwork.io.toExus.mem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush), 325 toMem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 326 ) 327 ) 328 } 329 } 330 331 io.mem.redirect := ctrlBlock.io.redirect 332 io.mem.issueUops.zip(toMem.flatten).foreach { case (sink, source) => 333 sink.valid := source.valid 334 source.ready := sink.ready 335 sink.bits.iqIdx := source.bits.iqIdx 336 sink.bits.isFirstIssue := source.bits.isFirstIssue 337 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 338 sink.bits.src := 0.U.asTypeOf(sink.bits.src) 339 sink.bits.src.zip(source.bits.src).foreach { case (l, r) => l := r} 340 sink.bits.uop.fuType := source.bits.fuType 341 sink.bits.uop.fuOpType := source.bits.fuOpType 342 sink.bits.uop.imm := source.bits.imm 343 sink.bits.uop.robIdx := source.bits.robIdx 344 sink.bits.uop.pdest := source.bits.pdest 345 sink.bits.uop.rfWen := source.bits.rfWen.getOrElse(false.B) 346 sink.bits.uop.fpWen := source.bits.fpWen.getOrElse(false.B) 347 sink.bits.uop.vecWen := source.bits.vecWen.getOrElse(false.B) 348 sink.bits.uop.flushPipe := source.bits.flushPipe.getOrElse(false.B) 349 sink.bits.uop.pc := source.bits.pc.getOrElse(0.U) 350 sink.bits.uop.lqIdx := source.bits.lqIdx.getOrElse(0.U.asTypeOf(new LqPtr)) 351 sink.bits.uop.sqIdx := source.bits.sqIdx.getOrElse(0.U.asTypeOf(new SqPtr)) 352 sink.bits.uop.ftqPtr := source.bits.ftqIdx.getOrElse(0.U.asTypeOf(new FtqPtr)) 353 sink.bits.uop.ftqOffset := source.bits.ftqOffset.getOrElse(0.U) 354 } 355 io.mem.loadFastMatch := memScheduler.io.toMem.get.loadFastMatch.map(_.fastMatch) 356 io.mem.loadFastImm := memScheduler.io.toMem.get.loadFastMatch.map(_.fastImm) 357 io.mem.tlbCsr := csrio.tlb 358 io.mem.csrCtrl := csrio.customCtrl 359 io.mem.sfence := fenceio.sfence 360 io.mem.isStoreException := CommitType.lsInstIsStore(ctrlBlock.io.robio.exception.bits.commitType) 361 require(io.mem.loadPcRead.size == params.LduCnt) 362 io.mem.loadPcRead.zipWithIndex.foreach { case (loadPcRead, i) => 363 loadPcRead.data := ctrlBlock.io.memLdPcRead(i).data 364 ctrlBlock.io.memLdPcRead(i).ptr := loadPcRead.ptr 365 ctrlBlock.io.memLdPcRead(i).offset := loadPcRead.offset 366 } 367 // mem io 368 io.mem.lsqEnqIO <> memScheduler.io.memIO.get.lsqEnqIO 369 io.mem.robLsqIO <> ctrlBlock.io.robio.lsq 370 io.mem.toSbuffer <> fenceio.sbuffer 371 372 io.frontendSfence := fenceio.sfence 373 io.frontendTlbCsr := csrio.tlb 374 io.frontendCsrCtrl := csrio.customCtrl 375 376 io.tlb <> csrio.tlb 377 378 io.csrCustomCtrl := csrio.customCtrl 379 380 dontTouch(memScheduler.io) 381 dontTouch(io.mem) 382 dontTouch(dataPath.io.toMemExu) 383 dontTouch(wbDataPath.io.fromMemExu) 384} 385 386class BackendMemIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 387 // params alias 388 private val LoadQueueSize = VirtualLoadQueueSize 389 // In/Out // Todo: split it into one-direction bundle 390 val lsqEnqIO = Flipped(new LsqEnqIO) 391 val robLsqIO = new RobLsqIO 392 val toSbuffer = new FenceToSbuffer 393 val ldaIqFeedback = Vec(params.LduCnt, Flipped(new MemRSFeedbackIO)) 394 val staIqFeedback = Vec(params.StaCnt, Flipped(new MemRSFeedbackIO)) 395 val loadPcRead = Vec(params.LduCnt, Flipped(new FtqRead(UInt(VAddrBits.W)))) 396 397 // Input 398 val writeBack = MixedVec(Seq.fill(params.LduCnt + params.StaCnt * 2)(Flipped(DecoupledIO(new MemExuOutput()))) ++ Seq.fill(params.VlduCnt)(Flipped(DecoupledIO(new MemExuOutput(true))))) 399 400 val s3_delayed_load_error = Input(Vec(LoadPipelineWidth, Bool())) 401 val stIn = Input(Vec(params.StaCnt, ValidIO(new DynInst()))) 402 val memoryViolation = Flipped(ValidIO(new Redirect)) 403 val exceptionVAddr = Input(UInt(VAddrBits.W)) 404 val sqDeq = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) 405 val lqDeq = Input(UInt(log2Up(CommitWidth + 1).W)) 406 407 val lqCancelCnt = Input(UInt(log2Up(VirtualLoadQueueSize + 1).W)) 408 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 409 410 val otherFastWakeup = Flipped(Vec(params.LduCnt + 2 * params.StaCnt, ValidIO(new DynInst))) 411 val stIssuePtr = Input(new SqPtr()) 412 413 val csrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 414 415 // Output 416 val redirect = ValidIO(new Redirect) // rob flush MemBlock 417 val issueUops = MixedVec(Seq.fill(params.LduCnt + params.StaCnt * 2)(DecoupledIO(new MemExuInput())) ++ Seq.fill(params.VlduCnt)(DecoupledIO(new MemExuInput(true)))) 418 val loadFastMatch = Vec(params.LduCnt, Output(UInt(params.LduCnt.W))) 419 val loadFastImm = Vec(params.LduCnt, Output(UInt(12.W))) // Imm_I 420 421 val tlbCsr = Output(new TlbCsrBundle) 422 val csrCtrl = Output(new CustomCSRCtrlIO) 423 val sfence = Output(new SfenceBundle) 424 val isStoreException = Output(Bool()) 425} 426 427class BackendIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 428 val fromTop = new Bundle { 429 val hartId = Input(UInt(8.W)) 430 val externalInterrupt = new ExternalInterruptIO 431 } 432 433 val toTop = new Bundle { 434 val cpuHalted = Output(Bool()) 435 } 436 437 val fenceio = new FenceIO 438 // Todo: merge these bundles into BackendFrontendIO 439 val frontend = Flipped(new FrontendToCtrlIO) 440 val frontendSfence = Output(new SfenceBundle) 441 val frontendCsrCtrl = Output(new CustomCSRCtrlIO) 442 val frontendTlbCsr = Output(new TlbCsrBundle) 443 // distributed csr write 444 val frontendCsrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 445 446 val mem = new BackendMemIO 447 448 val perf = Input(new PerfCounterIO) 449 450 val tlb = Output(new TlbCsrBundle) 451 452 val csrCustomCtrl = Output(new CustomCSRCtrlIO) 453} 454