1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15* 16* 17* Acknowledgement 18* 19* This implementation is inspired by several key papers: 20* [1] Robert. M. Tomasulo. "[An efficient algorithm for exploiting multiple arithmetic units.] 21* (https://doi.org/10.1147/rd.111.0025)" IBM Journal of Research and Development (IBMJ) 11.1: 25-33. 1967. 22***************************************************************************************/ 23 24package xiangshan.backend 25 26import org.chipsalliance.cde.config.Parameters 27import chisel3._ 28import chisel3.util._ 29import device.MsiInfoBundle 30import difftest._ 31import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 32import system.HasSoCParameter 33import utility._ 34import xiangshan._ 35import xiangshan.backend.Bundles.{DynInst, IssueQueueIQWakeUpBundle, LoadShouldCancel, MemExuInput, MemExuOutput, VPUCtrlSignals} 36import xiangshan.backend.ctrlblock.{DebugLSIO, LsTopdownInfo} 37import xiangshan.backend.datapath.DataConfig.{IntData, VecData, FpData} 38import xiangshan.backend.datapath.RdConfig.{IntRD, VfRD} 39import xiangshan.backend.datapath.WbConfig._ 40import xiangshan.backend.datapath.DataConfig._ 41import xiangshan.backend.datapath._ 42import xiangshan.backend.dispatch.CoreDispatchTopDownIO 43import xiangshan.backend.exu.ExuBlock 44import xiangshan.backend.fu.vector.Bundles.{VConfig, VType} 45import xiangshan.backend.fu.{FenceIO, FenceToSbuffer, FuConfig, FuType, PerfCounterIO} 46import xiangshan.backend.fu.NewCSR.PFEvent 47import xiangshan.backend.issue.EntryBundles._ 48import xiangshan.backend.issue.{Scheduler, SchedulerArithImp, SchedulerImpBase, SchedulerMemImp} 49import xiangshan.backend.rob.{RobCoreTopDownIO, RobDebugRollingIO, RobLsqIO, RobPtr} 50import xiangshan.backend.trace.TraceCoreInterface 51import xiangshan.frontend.{FtqPtr, FtqRead, PreDecodeInfo} 52import xiangshan.mem.{LqPtr, LsqEnqIO, SqPtr} 53 54import scala.collection.mutable 55 56class Backend(val params: BackendParams)(implicit p: Parameters) extends LazyModule 57 with HasXSParameter { 58 override def shouldBeInlined: Boolean = false 59 val inner = LazyModule(new BackendInlined(params)) 60 lazy val module = new BackendImp(this) 61} 62 63class BackendImp(wrapper: Backend)(implicit p: Parameters) extends LazyModuleImp(wrapper) { 64 val io = IO(new BackendIO()(p, wrapper.params)) 65 io <> wrapper.inner.module.io 66 if (p(DebugOptionsKey).ResetGen) { 67 ResetGen(ResetGenNode(Seq(ModuleNode(wrapper.inner.module))), reset, sim = false, io.dft_reset) 68 } 69} 70 71class BackendInlined(val params: BackendParams)(implicit p: Parameters) extends LazyModule 72 with HasXSParameter { 73 74 override def shouldBeInlined: Boolean = true 75 76 // check read & write port config 77 params.configChecks 78 79 /* Only update the idx in mem-scheduler here 80 * Idx in other schedulers can be updated the same way if needed 81 * 82 * Also note that we filter out the 'stData issue-queues' when counting 83 */ 84 for ((ibp, idx) <- params.memSchdParams.get.issueBlockParams.filter(iq => iq.StdCnt == 0).zipWithIndex) { 85 ibp.updateIdx(idx) 86 } 87 88 println(params.iqWakeUpParams) 89 90 for ((schdCfg, i) <- params.allSchdParams.zipWithIndex) { 91 schdCfg.bindBackendParam(params) 92 } 93 94 for ((iqCfg, i) <- params.allIssueParams.zipWithIndex) { 95 iqCfg.bindBackendParam(params) 96 } 97 98 for ((exuCfg, i) <- params.allExuParams.zipWithIndex) { 99 exuCfg.bindBackendParam(params) 100 exuCfg.updateIQWakeUpConfigs(params.iqWakeUpParams) 101 exuCfg.updateExuIdx(i) 102 } 103 104 println("[Backend] ExuConfigs:") 105 for (exuCfg <- params.allExuParams) { 106 val fuConfigs = exuCfg.fuConfigs 107 val wbPortConfigs = exuCfg.wbPortConfigs 108 val immType = exuCfg.immType 109 110 println("[Backend] " + 111 s"${exuCfg.name}: " + 112 (if (exuCfg.fakeUnit) "fake, " else "") + 113 (if (exuCfg.hasLoadFu || exuCfg.hasHyldaFu) s"LdExuIdx(${backendParams.getLdExuIdx(exuCfg)})" else "") + 114 s"${fuConfigs.map(_.name).mkString("fu(s): {", ",", "}")}, " + 115 s"${wbPortConfigs.mkString("wb: {", ",", "}")}, " + 116 s"${immType.map(SelImm.mkString(_)).mkString("imm: {", ",", "}")}, " + 117 s"latMax(${exuCfg.latencyValMax}), ${exuCfg.fuLatancySet.mkString("lat: {", ",", "}")}, " + 118 s"srcReg(${exuCfg.numRegSrc})" 119 ) 120 require( 121 wbPortConfigs.collectFirst { case x: IntWB => x }.nonEmpty == 122 fuConfigs.map(_.writeIntRf).reduce(_ || _), 123 s"${exuCfg.name} int wb port has no priority" 124 ) 125 require( 126 wbPortConfigs.collectFirst { case x: FpWB => x }.nonEmpty == 127 fuConfigs.map(x => x.writeFpRf).reduce(_ || _), 128 s"${exuCfg.name} fp wb port has no priority" 129 ) 130 require( 131 wbPortConfigs.collectFirst { case x: VfWB => x }.nonEmpty == 132 fuConfigs.map(x => x.writeVecRf).reduce(_ || _), 133 s"${exuCfg.name} vec wb port has no priority" 134 ) 135 } 136 137 println(s"[Backend] all fu configs") 138 for (cfg <- FuConfig.allConfigs) { 139 println(s"[Backend] $cfg") 140 } 141 142 println(s"[Backend] Int RdConfigs: ExuName(Priority)") 143 for ((port, seq) <- params.getRdPortParams(IntData())) { 144 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 145 } 146 147 println(s"[Backend] Int WbConfigs: ExuName(Priority)") 148 for ((port, seq) <- params.getWbPortParams(IntData())) { 149 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 150 } 151 152 println(s"[Backend] Fp RdConfigs: ExuName(Priority)") 153 for ((port, seq) <- params.getRdPortParams(FpData())) { 154 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 155 } 156 157 println(s"[Backend] Fp WbConfigs: ExuName(Priority)") 158 for ((port, seq) <- params.getWbPortParams(FpData())) { 159 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 160 } 161 162 println(s"[Backend] Vf RdConfigs: ExuName(Priority)") 163 for ((port, seq) <- params.getRdPortParams(VecData())) { 164 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 165 } 166 167 println(s"[Backend] Vf WbConfigs: ExuName(Priority)") 168 for ((port, seq) <- params.getWbPortParams(VecData())) { 169 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 170 } 171 172 println(s"[Backend] Dispatch Configs:") 173 println(s"[Backend] Load IQ enq width(${params.numLoadDp}), Store IQ enq width(${params.numStoreDp})") 174 println(s"[Backend] Load DP width(${LSQLdEnqWidth}), Store DP width(${LSQStEnqWidth})") 175 176 params.updateCopyPdestInfo 177 println(s"[Backend] copyPdestInfo ${params.copyPdestInfo}") 178 params.allExuParams.map(_.copyNum) 179 val ctrlBlock = LazyModule(new CtrlBlock(params)) 180 val intScheduler = params.intSchdParams.map(x => LazyModule(new Scheduler(x))) 181 val fpScheduler = params.fpSchdParams.map(x => LazyModule(new Scheduler(x))) 182 val vfScheduler = params.vfSchdParams.map(x => LazyModule(new Scheduler(x))) 183 val memScheduler = params.memSchdParams.map(x => LazyModule(new Scheduler(x))) 184 val dataPath = LazyModule(new DataPath(params)) 185 val intExuBlock = params.intSchdParams.map(x => LazyModule(new ExuBlock(x))) 186 val fpExuBlock = params.fpSchdParams.map(x => LazyModule(new ExuBlock(x))) 187 val vfExuBlock = params.vfSchdParams.map(x => LazyModule(new ExuBlock(x))) 188 val wbFuBusyTable = LazyModule(new WbFuBusyTable(params)) 189 190 lazy val module = new BackendInlinedImp(this) 191} 192 193class BackendInlinedImp(override val wrapper: BackendInlined)(implicit p: Parameters) extends LazyModuleImp(wrapper) 194 with HasXSParameter 195 with HasPerfEvents 196 with HasCriticalErrors { 197 implicit private val params: BackendParams = wrapper.params 198 199 val io = IO(new BackendIO()(p, wrapper.params)) 200 201 private val ctrlBlock = wrapper.ctrlBlock.module 202 private val intScheduler: SchedulerImpBase = wrapper.intScheduler.get.module 203 private val fpScheduler = wrapper.fpScheduler.get.module 204 private val vfScheduler = wrapper.vfScheduler.get.module 205 private val memScheduler = wrapper.memScheduler.get.module 206 private val dataPath = wrapper.dataPath.module 207 private val intExuBlock = wrapper.intExuBlock.get.module 208 private val fpExuBlock = wrapper.fpExuBlock.get.module 209 private val vfExuBlock = wrapper.vfExuBlock.get.module 210 private val og2ForVector = Module(new Og2ForVector(params)) 211 private val bypassNetwork = Module(new BypassNetwork) 212 private val wbDataPath = Module(new WbDataPath(params)) 213 private val wbFuBusyTable = wrapper.wbFuBusyTable.module 214 private val vecExcpMod = Module(new VecExcpDataMergeModule) 215 216 private val iqWakeUpMappedBundle: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = ( 217 intScheduler.io.toSchedulers.wakeupVec ++ 218 fpScheduler.io.toSchedulers.wakeupVec ++ 219 vfScheduler.io.toSchedulers.wakeupVec ++ 220 memScheduler.io.toSchedulers.wakeupVec 221 ).map(x => (x.bits.exuIdx, x)).toMap 222 223 private val iqWakeUpMappedBundleDelayed: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = ( 224 intScheduler.io.toSchedulers.wakeupVec ++ 225 fpScheduler.io.toSchedulers.wakeupVec ++ 226 vfScheduler.io.toSchedulers.wakeupVec ++ 227 memScheduler.io.toSchedulers.wakeupVec 228 ).map{ case x => 229 val delayed = Wire(chiselTypeOf(x)) 230 // TODO: add clock gate use Wen, remove issuequeue wakeupToIQ logic Wen = Wen && valid 231 delayed := RegNext(x) 232 (x.bits.exuIdx, delayed) 233 }.toMap 234 235 println(s"[Backend] iq wake up keys: ${iqWakeUpMappedBundle.keys}") 236 237 wbFuBusyTable.io.in.intSchdBusyTable := intScheduler.io.wbFuBusyTable 238 wbFuBusyTable.io.in.fpSchdBusyTable := fpScheduler.io.wbFuBusyTable 239 wbFuBusyTable.io.in.vfSchdBusyTable := vfScheduler.io.wbFuBusyTable 240 wbFuBusyTable.io.in.memSchdBusyTable := memScheduler.io.wbFuBusyTable 241 intScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.intRespRead 242 fpScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.fpRespRead 243 vfScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.vfRespRead 244 memScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.memRespRead 245 dataPath.io.wbConfictRead := wbFuBusyTable.io.out.wbConflictRead 246 247 private val og1Cancel = dataPath.io.og1Cancel 248 private val og0Cancel = dataPath.io.og0Cancel 249 private val vlFromIntIsZero = intExuBlock.io.vlIsZero.get 250 private val vlFromIntIsVlmax = intExuBlock.io.vlIsVlmax.get 251 private val vlFromVfIsZero = vfExuBlock.io.vlIsZero.get 252 private val vlFromVfIsVlmax = vfExuBlock.io.vlIsVlmax.get 253 254 private val backendCriticalError = Wire(Bool()) 255 256 ctrlBlock.io.fromTop.hartId := io.fromTop.hartId 257 ctrlBlock.io.frontend <> io.frontend 258 ctrlBlock.io.fromCSR.toDecode := intExuBlock.io.csrToDecode.get 259 ctrlBlock.io.fromCSR.traceCSR := intExuBlock.io.csrio.get.traceCSR 260 ctrlBlock.io.fromCSR.instrAddrTransType := RegNext(intExuBlock.io.csrio.get.instrAddrTransType) 261 ctrlBlock.io.fromWB.wbData <> wbDataPath.io.toCtrlBlock.writeback 262 ctrlBlock.io.fromMem.stIn <> io.mem.stIn 263 ctrlBlock.io.fromMem.violation <> io.mem.memoryViolation 264 ctrlBlock.io.lqCanAccept := io.mem.lqCanAccept 265 ctrlBlock.io.sqCanAccept := io.mem.sqCanAccept 266 267 io.mem.lsqEnqIO <> ctrlBlock.io.toMem.lsqEnqIO 268 ctrlBlock.io.fromMemToDispatch.scommit := io.mem.sqDeq 269 ctrlBlock.io.fromMemToDispatch.lcommit := io.mem.lqDeq 270 ctrlBlock.io.fromMemToDispatch.sqDeqPtr := io.mem.sqDeqPtr 271 ctrlBlock.io.fromMemToDispatch.lqDeqPtr := io.mem.lqDeqPtr 272 ctrlBlock.io.fromMemToDispatch.sqCancelCnt := io.mem.sqCancelCnt 273 ctrlBlock.io.fromMemToDispatch.lqCancelCnt := io.mem.lqCancelCnt 274 ctrlBlock.io.toDispatch.wakeUpInt := intScheduler.io.toSchedulers.wakeupVec 275 ctrlBlock.io.toDispatch.wakeUpFp := fpScheduler.io.toSchedulers.wakeupVec 276 ctrlBlock.io.toDispatch.wakeUpVec := vfScheduler.io.toSchedulers.wakeupVec 277 ctrlBlock.io.toDispatch.wakeUpMem := memScheduler.io.toSchedulers.wakeupVec 278 ctrlBlock.io.toDispatch.IQValidNumVec := intScheduler.io.IQValidNumVec ++ fpScheduler.io.IQValidNumVec ++ vfScheduler.io.IQValidNumVec ++ memScheduler.io.IQValidNumVec 279 ctrlBlock.io.toDispatch.ldCancel := io.mem.ldCancel 280 ctrlBlock.io.toDispatch.og0Cancel := og0Cancel 281 ctrlBlock.io.toDispatch.wbPregsInt.zip(wbDataPath.io.toIntPreg).map(x => { 282 x._1.valid := x._2.wen && x._2.intWen 283 x._1.bits := x._2.addr 284 }) 285 ctrlBlock.io.toDispatch.wbPregsFp.zip(wbDataPath.io.toFpPreg).map(x => { 286 x._1.valid := x._2.wen && x._2.fpWen 287 x._1.bits := x._2.addr 288 }) 289 ctrlBlock.io.toDispatch.wbPregsVec.zip(wbDataPath.io.toVfPreg).map(x => { 290 x._1.valid := x._2.wen && x._2.vecWen 291 x._1.bits := x._2.addr 292 }) 293 ctrlBlock.io.toDispatch.wbPregsV0.zip(wbDataPath.io.toV0Preg).map(x => { 294 x._1.valid := x._2.wen && x._2.v0Wen 295 x._1.bits := x._2.addr 296 }) 297 ctrlBlock.io.toDispatch.wbPregsVl.zip(wbDataPath.io.toVlPreg).map(x => { 298 x._1.valid := x._2.wen && x._2.vlWen 299 x._1.bits := x._2.addr 300 }) 301 ctrlBlock.io.toDispatch.vlWriteBackInfo.vlFromIntIsZero := vlFromIntIsZero 302 ctrlBlock.io.toDispatch.vlWriteBackInfo.vlFromIntIsVlmax := vlFromIntIsVlmax 303 ctrlBlock.io.toDispatch.vlWriteBackInfo.vlFromVfIsZero := vlFromVfIsZero 304 ctrlBlock.io.toDispatch.vlWriteBackInfo.vlFromVfIsVlmax := vlFromVfIsVlmax 305 ctrlBlock.io.csrCtrl <> intExuBlock.io.csrio.get.customCtrl 306 ctrlBlock.io.robio.csr.intrBitSet := intExuBlock.io.csrio.get.interrupt 307 ctrlBlock.io.robio.csr.trapTarget := intExuBlock.io.csrio.get.trapTarget 308 ctrlBlock.io.robio.csr.isXRet := intExuBlock.io.csrio.get.isXRet 309 ctrlBlock.io.robio.csr.wfiEvent := intExuBlock.io.csrio.get.wfi_event 310 ctrlBlock.io.robio.csr.criticalErrorState := intExuBlock.io.csrio.get.criticalErrorState 311 ctrlBlock.io.robio.lsq <> io.mem.robLsqIO 312 ctrlBlock.io.robio.lsTopdownInfo <> io.mem.lsTopdownInfo 313 ctrlBlock.io.robio.debug_ls <> io.mem.debugLS 314 ctrlBlock.io.debugEnqLsq.canAccept := io.mem.lsqEnqIO.canAccept 315 ctrlBlock.io.debugEnqLsq.resp := io.mem.lsqEnqIO.resp 316 ctrlBlock.io.debugEnqLsq.req := ctrlBlock.io.toMem.lsqEnqIO.req 317 ctrlBlock.io.debugEnqLsq.needAlloc := ctrlBlock.io.toMem.lsqEnqIO.needAlloc 318 ctrlBlock.io.debugEnqLsq.iqAccept := ctrlBlock.io.toMem.lsqEnqIO.iqAccept 319 ctrlBlock.io.fromVecExcpMod.busy := vecExcpMod.o.status.busy 320 321 val intWriteBackDelayed = Wire(chiselTypeOf(wbDataPath.io.toIntPreg)) 322 intWriteBackDelayed.zip(wbDataPath.io.toIntPreg).map{ case (sink, source) => 323 sink := DontCare 324 sink.wen := RegNext(source.wen) 325 sink.intWen := RegNext(source.intWen) 326 sink.addr := RegEnable(source.addr, source.wen) 327 } 328 val fpWriteBackDelayed = Wire(chiselTypeOf(wbDataPath.io.toFpPreg)) 329 fpWriteBackDelayed.zip(wbDataPath.io.toFpPreg).map { case (sink, source) => 330 sink := DontCare 331 sink.wen := RegNext(source.wen) 332 sink.fpWen := RegNext(source.fpWen) 333 sink.addr := RegEnable(source.addr, source.wen) 334 } 335 val vfWriteBackDelayed = Wire(chiselTypeOf(wbDataPath.io.toVfPreg)) 336 vfWriteBackDelayed.zip(wbDataPath.io.toVfPreg).map { case (sink, source) => 337 sink := DontCare 338 sink.wen := RegNext(source.wen) 339 sink.vecWen := RegNext(source.vecWen) 340 sink.addr := RegEnable(source.addr, source.wen) 341 } 342 val v0WriteBackDelayed = Wire(chiselTypeOf(wbDataPath.io.toV0Preg)) 343 v0WriteBackDelayed.zip(wbDataPath.io.toV0Preg).map { case (sink, source) => 344 sink := DontCare 345 sink.wen := RegNext(source.wen) 346 sink.v0Wen := RegNext(source.v0Wen) 347 sink.addr := RegEnable(source.addr, source.wen) 348 } 349 val vlWriteBackDelayed = Wire(chiselTypeOf(wbDataPath.io.toVlPreg)) 350 vlWriteBackDelayed.zip(wbDataPath.io.toVlPreg).map { case (sink, source) => 351 sink := DontCare 352 sink.wen := RegNext(source.wen) 353 sink.vlWen := RegNext(source.vlWen) 354 sink.addr := RegEnable(source.addr, source.wen) 355 } 356 intScheduler.io.fromTop.hartId := io.fromTop.hartId 357 intScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 358 intScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.intUops 359 intScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 360 intScheduler.io.fpWriteBack := 0.U.asTypeOf(intScheduler.io.fpWriteBack) 361 intScheduler.io.vfWriteBack := 0.U.asTypeOf(intScheduler.io.vfWriteBack) 362 intScheduler.io.v0WriteBack := 0.U.asTypeOf(intScheduler.io.v0WriteBack) 363 intScheduler.io.vlWriteBack := 0.U.asTypeOf(intScheduler.io.vlWriteBack) 364 intScheduler.io.intWriteBackDelayed := intWriteBackDelayed 365 intScheduler.io.fpWriteBackDelayed := 0.U.asTypeOf(intScheduler.io.fpWriteBackDelayed) 366 intScheduler.io.vfWriteBackDelayed := 0.U.asTypeOf(intScheduler.io.vfWriteBackDelayed) 367 intScheduler.io.v0WriteBackDelayed := 0.U.asTypeOf(intScheduler.io.v0WriteBackDelayed) 368 intScheduler.io.vlWriteBackDelayed := 0.U.asTypeOf(intScheduler.io.vlWriteBackDelayed) 369 intScheduler.io.fromDataPath.resp := dataPath.io.toIntIQ 370 intScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 371 intScheduler.io.fromSchedulers.wakeupVecDelayed.foreach { wakeup => wakeup := iqWakeUpMappedBundleDelayed(wakeup.bits.exuIdx) } 372 intScheduler.io.fromDataPath.og0Cancel := og0Cancel 373 intScheduler.io.fromDataPath.og1Cancel := og1Cancel 374 intScheduler.io.ldCancel := io.mem.ldCancel 375 intScheduler.io.fromDataPath.replaceRCIdx.get := dataPath.io.toWakeupQueueRCIdx.take(params.getIntExuRCWriteSize) 376 intScheduler.io.vlWriteBackInfo.vlFromIntIsZero := false.B 377 intScheduler.io.vlWriteBackInfo.vlFromIntIsVlmax := false.B 378 intScheduler.io.vlWriteBackInfo.vlFromVfIsZero := false.B 379 intScheduler.io.vlWriteBackInfo.vlFromVfIsVlmax := false.B 380 381 fpScheduler.io.fromTop.hartId := io.fromTop.hartId 382 fpScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 383 fpScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.fpUops 384 fpScheduler.io.intWriteBack := 0.U.asTypeOf(fpScheduler.io.intWriteBack) 385 fpScheduler.io.fpWriteBack := wbDataPath.io.toFpPreg 386 fpScheduler.io.vfWriteBack := 0.U.asTypeOf(fpScheduler.io.vfWriteBack) 387 fpScheduler.io.v0WriteBack := 0.U.asTypeOf(fpScheduler.io.v0WriteBack) 388 fpScheduler.io.vlWriteBack := 0.U.asTypeOf(fpScheduler.io.vlWriteBack) 389 fpScheduler.io.intWriteBackDelayed := 0.U.asTypeOf(intWriteBackDelayed) 390 fpScheduler.io.fpWriteBackDelayed := fpWriteBackDelayed 391 fpScheduler.io.vfWriteBackDelayed := 0.U.asTypeOf(intScheduler.io.vfWriteBackDelayed) 392 fpScheduler.io.v0WriteBackDelayed := 0.U.asTypeOf(intScheduler.io.v0WriteBackDelayed) 393 fpScheduler.io.vlWriteBackDelayed := 0.U.asTypeOf(intScheduler.io.vlWriteBackDelayed) 394 fpScheduler.io.fromDataPath.resp := dataPath.io.toFpIQ 395 fpScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 396 fpScheduler.io.fromSchedulers.wakeupVecDelayed.foreach { wakeup => wakeup := iqWakeUpMappedBundleDelayed(wakeup.bits.exuIdx) } 397 fpScheduler.io.fromDataPath.og0Cancel := og0Cancel 398 fpScheduler.io.fromDataPath.og1Cancel := og1Cancel 399 fpScheduler.io.ldCancel := io.mem.ldCancel 400 fpScheduler.io.vlWriteBackInfo.vlFromIntIsZero := false.B 401 fpScheduler.io.vlWriteBackInfo.vlFromIntIsVlmax := false.B 402 fpScheduler.io.vlWriteBackInfo.vlFromVfIsZero := false.B 403 fpScheduler.io.vlWriteBackInfo.vlFromVfIsVlmax := false.B 404 405 memScheduler.io.fromTop.hartId := io.fromTop.hartId 406 memScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 407 memScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.memUops 408 memScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 409 memScheduler.io.fpWriteBack := wbDataPath.io.toFpPreg 410 memScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 411 memScheduler.io.v0WriteBack := wbDataPath.io.toV0Preg 412 memScheduler.io.vlWriteBack := wbDataPath.io.toVlPreg 413 memScheduler.io.intWriteBackDelayed := intWriteBackDelayed 414 memScheduler.io.fpWriteBackDelayed := fpWriteBackDelayed 415 memScheduler.io.vfWriteBackDelayed := vfWriteBackDelayed 416 memScheduler.io.v0WriteBackDelayed := v0WriteBackDelayed 417 memScheduler.io.vlWriteBackDelayed := vlWriteBackDelayed 418 memScheduler.io.fromMem.get.scommit := io.mem.sqDeq 419 memScheduler.io.fromMem.get.lcommit := io.mem.lqDeq 420 memScheduler.io.fromMem.get.wakeup := io.mem.wakeup 421 memScheduler.io.fromMem.get.sqDeqPtr := io.mem.sqDeqPtr 422 memScheduler.io.fromMem.get.lqDeqPtr := io.mem.lqDeqPtr 423 memScheduler.io.fromMem.get.sqCancelCnt := io.mem.sqCancelCnt 424 memScheduler.io.fromMem.get.lqCancelCnt := io.mem.lqCancelCnt 425 memScheduler.io.fromMem.get.stIssuePtr := io.mem.stIssuePtr 426 require(memScheduler.io.fromMem.get.memWaitUpdateReq.robIdx.length == io.mem.stIn.length) 427 memScheduler.io.fromMem.get.memWaitUpdateReq.robIdx.zip(io.mem.stIn).foreach { case (sink, source) => 428 sink.valid := source.valid 429 sink.bits := source.bits.robIdx 430 } 431 memScheduler.io.fromMem.get.memWaitUpdateReq.sqIdx := DontCare // TODO 432 memScheduler.io.fromDataPath.resp := dataPath.io.toMemIQ 433 memScheduler.io.fromMem.get.ldaFeedback := io.mem.ldaIqFeedback 434 memScheduler.io.fromMem.get.staFeedback := io.mem.staIqFeedback 435 memScheduler.io.fromMem.get.hyuFeedback := io.mem.hyuIqFeedback 436 memScheduler.io.fromMem.get.vstuFeedback := io.mem.vstuIqFeedback 437 memScheduler.io.fromMem.get.vlduFeedback := io.mem.vlduIqFeedback 438 memScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 439 memScheduler.io.fromSchedulers.wakeupVecDelayed.foreach { wakeup => wakeup := iqWakeUpMappedBundleDelayed(wakeup.bits.exuIdx) } 440 memScheduler.io.fromDataPath.og0Cancel := og0Cancel 441 memScheduler.io.fromDataPath.og1Cancel := og1Cancel 442 memScheduler.io.ldCancel := io.mem.ldCancel 443 memScheduler.io.fromDataPath.replaceRCIdx.get := dataPath.io.toWakeupQueueRCIdx.takeRight(params.getMemExuRCWriteSize) 444 memScheduler.io.vlWriteBackInfo.vlFromIntIsZero := vlFromIntIsZero 445 memScheduler.io.vlWriteBackInfo.vlFromIntIsVlmax := vlFromIntIsVlmax 446 memScheduler.io.vlWriteBackInfo.vlFromVfIsZero := vlFromVfIsZero 447 memScheduler.io.vlWriteBackInfo.vlFromVfIsVlmax := vlFromVfIsVlmax 448 memScheduler.io.fromOg2Resp.get := og2ForVector.io.toMemIQOg2Resp 449 450 vfScheduler.io.fromTop.hartId := io.fromTop.hartId 451 vfScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 452 vfScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.vfUops 453 vfScheduler.io.intWriteBack := 0.U.asTypeOf(vfScheduler.io.intWriteBack) 454 vfScheduler.io.fpWriteBack := 0.U.asTypeOf(vfScheduler.io.fpWriteBack) 455 vfScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 456 vfScheduler.io.v0WriteBack := wbDataPath.io.toV0Preg 457 vfScheduler.io.vlWriteBack := wbDataPath.io.toVlPreg 458 vfScheduler.io.intWriteBackDelayed := 0.U.asTypeOf(intWriteBackDelayed) 459 vfScheduler.io.fpWriteBackDelayed := 0.U.asTypeOf(fpWriteBackDelayed) 460 vfScheduler.io.vfWriteBackDelayed := vfWriteBackDelayed 461 vfScheduler.io.v0WriteBackDelayed := v0WriteBackDelayed 462 vfScheduler.io.vlWriteBackDelayed := vlWriteBackDelayed 463 vfScheduler.io.fromDataPath.resp := dataPath.io.toVfIQ 464 vfScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 465 vfScheduler.io.fromSchedulers.wakeupVecDelayed.foreach { wakeup => wakeup := iqWakeUpMappedBundleDelayed(wakeup.bits.exuIdx) } 466 vfScheduler.io.fromDataPath.og0Cancel := og0Cancel 467 vfScheduler.io.fromDataPath.og1Cancel := og1Cancel 468 vfScheduler.io.ldCancel := io.mem.ldCancel 469 vfScheduler.io.vlWriteBackInfo.vlFromIntIsZero := vlFromIntIsZero 470 vfScheduler.io.vlWriteBackInfo.vlFromIntIsVlmax := vlFromIntIsVlmax 471 vfScheduler.io.vlWriteBackInfo.vlFromVfIsZero := vlFromVfIsZero 472 vfScheduler.io.vlWriteBackInfo.vlFromVfIsVlmax := vlFromVfIsVlmax 473 vfScheduler.io.fromOg2Resp.get := og2ForVector.io.toVfIQOg2Resp 474 475 dataPath.io.hartId := io.fromTop.hartId 476 dataPath.io.flush := ctrlBlock.io.toDataPath.flush 477 478 dataPath.io.fromIntIQ <> intScheduler.io.toDataPathAfterDelay 479 dataPath.io.fromFpIQ <> fpScheduler.io.toDataPathAfterDelay 480 dataPath.io.fromVfIQ <> vfScheduler.io.toDataPathAfterDelay 481 dataPath.io.fromMemIQ <> memScheduler.io.toDataPathAfterDelay 482 483 dataPath.io.ldCancel := io.mem.ldCancel 484 485 println(s"[Backend] wbDataPath.io.toIntPreg: ${wbDataPath.io.toIntPreg.size}, dataPath.io.fromIntWb: ${dataPath.io.fromIntWb.size}") 486 println(s"[Backend] wbDataPath.io.toVfPreg: ${wbDataPath.io.toVfPreg.size}, dataPath.io.fromFpWb: ${dataPath.io.fromVfWb.size}") 487 dataPath.io.fromIntWb := wbDataPath.io.toIntPreg 488 dataPath.io.fromFpWb := wbDataPath.io.toFpPreg 489 dataPath.io.fromVfWb := wbDataPath.io.toVfPreg 490 dataPath.io.fromV0Wb := wbDataPath.io.toV0Preg 491 dataPath.io.fromVlWb := wbDataPath.io.toVlPreg 492 dataPath.io.diffIntRat.foreach(_ := ctrlBlock.io.diff_int_rat.get) 493 dataPath.io.diffFpRat .foreach(_ := ctrlBlock.io.diff_fp_rat.get) 494 dataPath.io.diffVecRat.foreach(_ := ctrlBlock.io.diff_vec_rat.get) 495 dataPath.io.diffV0Rat .foreach(_ := ctrlBlock.io.diff_v0_rat.get) 496 dataPath.io.diffVlRat .foreach(_ := ctrlBlock.io.diff_vl_rat.get) 497 dataPath.io.fromBypassNetwork := bypassNetwork.io.toDataPath 498 dataPath.io.fromVecExcpMod.r := vecExcpMod.o.toVPRF.r 499 dataPath.io.fromVecExcpMod.w := vecExcpMod.o.toVPRF.w 500 dataPath.io.topDownInfo.lqEmpty := DelayN(io.topDownInfo.lqEmpty, 2) 501 dataPath.io.topDownInfo.sqEmpty := DelayN(io.topDownInfo.sqEmpty, 2) 502 dataPath.io.topDownInfo.l1Miss := RegNext(io.topDownInfo.l1Miss) 503 dataPath.io.topDownInfo.l2TopMiss.l2Miss := io.topDownInfo.l2TopMiss.l2Miss 504 dataPath.io.topDownInfo.l2TopMiss.l3Miss := io.topDownInfo.l2TopMiss.l3Miss 505 506 og2ForVector.io.flush := ctrlBlock.io.toDataPath.flush 507 og2ForVector.io.ldCancel := io.mem.ldCancel 508 og2ForVector.io.fromOg1VfArith <> dataPath.io.toVecExu 509 og2ForVector.io.fromOg1VecMem.zip(dataPath.io.toMemExu.zip(params.memSchdParams.get.issueBlockParams).filter(_._2.needOg2Resp).map(_._1)) 510 .foreach { 511 case (og1Mem, datapathMem) => og1Mem <> datapathMem 512 } 513 og2ForVector.io.fromOg1ImmInfo := dataPath.io.og1ImmInfo.zip(params.allExuParams).filter(_._2.needOg2).map(_._1) 514 515 println(s"[Backend] BypassNetwork OG1 Mem Size: ${bypassNetwork.io.fromDataPath.mem.zip(params.memSchdParams.get.issueBlockParams).filterNot(_._2.needOg2Resp).size}") 516 println(s"[Backend] BypassNetwork OG2 Mem Size: ${bypassNetwork.io.fromDataPath.mem.zip(params.memSchdParams.get.issueBlockParams).filter(_._2.needOg2Resp).size}") 517 println(s"[Backend] bypassNetwork.io.fromDataPath.mem: ${bypassNetwork.io.fromDataPath.mem.size}, dataPath.io.toMemExu: ${dataPath.io.toMemExu.size}") 518 bypassNetwork.io.fromDataPath.int <> dataPath.io.toIntExu 519 bypassNetwork.io.fromDataPath.fp <> dataPath.io.toFpExu 520 bypassNetwork.io.fromDataPath.vf <> og2ForVector.io.toVfArithExu 521 bypassNetwork.io.fromDataPath.mem.lazyZip(params.memSchdParams.get.issueBlockParams).lazyZip(dataPath.io.toMemExu).filterNot(_._2.needOg2Resp) 522 .map(x => (x._1, x._3)).foreach { 523 case (bypassMem, datapathMem) => bypassMem <> datapathMem 524 } 525 bypassNetwork.io.fromDataPath.mem.zip(params.memSchdParams.get.issueBlockParams).filter(_._2.needOg2Resp).map(_._1) 526 .zip(og2ForVector.io.toVecMemExu).foreach { 527 case (bypassMem, og2Mem) => bypassMem <> og2Mem 528 } 529 bypassNetwork.io.fromDataPath.immInfo := dataPath.io.og1ImmInfo 530 bypassNetwork.io.fromDataPath.immInfo.zip(params.allExuParams).filter(_._2.needOg2).map(_._1) 531 .zip(og2ForVector.io.toBypassNetworkImmInfo).foreach { 532 case (immInfo, og2ImmInfo) => immInfo := og2ImmInfo 533 } 534 bypassNetwork.io.fromDataPath.rcData := dataPath.io.toBypassNetworkRCData 535 bypassNetwork.io.fromExus.connectExuOutput(_.int)(intExuBlock.io.out) 536 bypassNetwork.io.fromExus.connectExuOutput(_.fp)(fpExuBlock.io.out) 537 bypassNetwork.io.fromExus.connectExuOutput(_.vf)(vfExuBlock.io.out) 538 539 require(bypassNetwork.io.fromExus.mem.flatten.size == io.mem.writeBack.size, 540 s"bypassNetwork.io.fromExus.mem.flatten.size(${bypassNetwork.io.fromExus.mem.flatten.size}: ${bypassNetwork.io.fromExus.mem.map(_.size)}, " + 541 s"io.mem.writeback(${io.mem.writeBack.size})" 542 ) 543 bypassNetwork.io.fromExus.mem.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 544 sink.valid := source.valid 545 sink.bits.intWen := source.bits.uop.rfWen && source.bits.isFromLoadUnit 546 sink.bits.pdest := source.bits.uop.pdest 547 sink.bits.data := source.bits.data 548 } 549 550 551 intExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 552 for (i <- 0 until intExuBlock.io.in.length) { 553 for (j <- 0 until intExuBlock.io.in(i).length) { 554 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.int(i)(j).bits.loadDependency, io.mem.ldCancel) 555 NewPipelineConnect( 556 bypassNetwork.io.toExus.int(i)(j), intExuBlock.io.in(i)(j), intExuBlock.io.in(i)(j).fire, 557 Mux( 558 bypassNetwork.io.toExus.int(i)(j).fire, 559 bypassNetwork.io.toExus.int(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 560 intExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 561 ), 562 Option("bypassNetwork2intExuBlock") 563 ) 564 } 565 } 566 567 ctrlBlock.io.toDataPath.pcToDataPathIO <> dataPath.io.fromPcTargetMem 568 569 private val csrin = intExuBlock.io.csrin.get 570 csrin.hartId := io.fromTop.hartId 571 csrin.msiInfo.valid := RegNext(io.fromTop.msiInfo.valid) 572 csrin.msiInfo.bits := RegEnable(io.fromTop.msiInfo.bits, io.fromTop.msiInfo.valid) 573 csrin.clintTime.valid := RegNext(io.fromTop.clintTime.valid) 574 csrin.clintTime.bits := RegEnable(io.fromTop.clintTime.bits, io.fromTop.clintTime.valid) 575 csrin.l2FlushDone := RegNext(io.fromTop.l2FlushDone) 576 csrin.trapInstInfo := ctrlBlock.io.toCSR.trapInstInfo 577 csrin.fromVecExcpMod.busy := vecExcpMod.o.status.busy 578 csrin.criticalErrorState := backendCriticalError 579 580 private val csrio = intExuBlock.io.csrio.get 581 csrio.hartId := io.fromTop.hartId 582 csrio.fpu.fflags := ctrlBlock.io.robio.csr.fflags 583 csrio.fpu.isIllegal := false.B // Todo: remove it 584 csrio.fpu.dirty_fs := ctrlBlock.io.robio.csr.dirty_fs 585 csrio.vpu <> WireDefault(0.U.asTypeOf(csrio.vpu)) // Todo 586 587 val fromIntExuVsetVType = intExuBlock.io.vtype.getOrElse(0.U.asTypeOf((Valid(new VType)))) 588 val fromVfExuVsetVType = vfExuBlock.io.vtype.getOrElse(0.U.asTypeOf((Valid(new VType)))) 589 val fromVsetVType = Mux(fromIntExuVsetVType.valid, fromIntExuVsetVType.bits, fromVfExuVsetVType.bits) 590 val vsetvlVType = RegEnable(fromVsetVType, 0.U.asTypeOf(new VType), fromIntExuVsetVType.valid || fromVfExuVsetVType.valid) 591 ctrlBlock.io.toDecode.vsetvlVType := vsetvlVType 592 593 val commitVType = ctrlBlock.io.robio.commitVType.vtype 594 val hasVsetvl = ctrlBlock.io.robio.commitVType.hasVsetvl 595 val vtype = VType.toVtypeStruct(Mux(hasVsetvl, vsetvlVType, commitVType.bits)).asUInt 596 597 // csr not store the value of vl, so when using difftest we assign the value of vl to debugVl 598 val debugVl_s0 = WireInit(UInt(VlData().dataWidth.W), 0.U) 599 val debugVl_s1 = WireInit(UInt(VlData().dataWidth.W), 0.U) 600 debugVl_s0 := dataPath.io.diffVl.getOrElse(0.U.asTypeOf(UInt(VlData().dataWidth.W))) 601 debugVl_s1 := RegNext(debugVl_s0) 602 csrio.vpu.set_vxsat := ctrlBlock.io.robio.csr.vxsat 603 csrio.vpu.set_vstart.valid := ctrlBlock.io.robio.csr.vstart.valid 604 csrio.vpu.set_vstart.bits := ctrlBlock.io.robio.csr.vstart.bits 605 ctrlBlock.io.toDecode.vstart := csrio.vpu.vstart 606 //Todo here need change design 607 csrio.vpu.set_vtype.valid := commitVType.valid 608 csrio.vpu.set_vtype.bits := ZeroExt(vtype, XLEN) 609 csrio.vpu.vl := ZeroExt(debugVl_s1, XLEN) 610 csrio.vpu.dirty_vs := ctrlBlock.io.robio.csr.dirty_vs 611 csrio.exception := ctrlBlock.io.robio.exception 612 csrio.robDeqPtr := ctrlBlock.io.robio.robDeqPtr 613 csrio.memExceptionVAddr := io.mem.exceptionAddr.vaddr 614 csrio.memExceptionGPAddr := io.mem.exceptionAddr.gpaddr 615 csrio.memExceptionIsForVSnonLeafPTE := io.mem.exceptionAddr.isForVSnonLeafPTE 616 csrio.externalInterrupt := RegNext(io.fromTop.externalInterrupt) 617 csrio.perf <> io.perf 618 csrio.perf.retiredInstr <> ctrlBlock.io.robio.csr.perfinfo.retiredInstr 619 csrio.perf.ctrlInfo <> ctrlBlock.io.perfInfo.ctrlInfo 620 private val fenceio = intExuBlock.io.fenceio.get 621 io.fenceio <> fenceio 622 623 // to fpExuBlock 624 fpExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 625 for (i <- 0 until fpExuBlock.io.in.length) { 626 for (j <- 0 until fpExuBlock.io.in(i).length) { 627 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.fp(i)(j).bits.loadDependency, io.mem.ldCancel) 628 NewPipelineConnect( 629 bypassNetwork.io.toExus.fp(i)(j), fpExuBlock.io.in(i)(j), fpExuBlock.io.in(i)(j).fire, 630 Mux( 631 bypassNetwork.io.toExus.fp(i)(j).fire, 632 bypassNetwork.io.toExus.fp(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 633 fpExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 634 ), 635 Option("bypassNetwork2fpExuBlock") 636 ) 637 } 638 } 639 640 vfExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 641 for (i <- 0 until vfExuBlock.io.in.size) { 642 for (j <- 0 until vfExuBlock.io.in(i).size) { 643 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.vf(i)(j).bits.loadDependency, io.mem.ldCancel) 644 NewPipelineConnect( 645 bypassNetwork.io.toExus.vf(i)(j), vfExuBlock.io.in(i)(j), vfExuBlock.io.in(i)(j).fire, 646 Mux( 647 bypassNetwork.io.toExus.vf(i)(j).fire, 648 bypassNetwork.io.toExus.vf(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 649 vfExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 650 ), 651 Option("bypassNetwork2vfExuBlock") 652 ) 653 654 } 655 } 656 657 intExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 658 fpExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 659 fpExuBlock.io.vxrm.foreach(_ := csrio.vpu.vxrm) 660 vfExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 661 vfExuBlock.io.vxrm.foreach(_ := csrio.vpu.vxrm) 662 663 wbDataPath.io.flush := ctrlBlock.io.redirect 664 wbDataPath.io.fromTop.hartId := io.fromTop.hartId 665 wbDataPath.io.fromIntExu <> intExuBlock.io.out 666 wbDataPath.io.fromFpExu <> fpExuBlock.io.out 667 wbDataPath.io.fromVfExu <> vfExuBlock.io.out 668 wbDataPath.io.fromMemExu.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 669 sink.valid := source.valid 670 source.ready := sink.ready 671 sink.bits.data := VecInit(Seq.fill(sink.bits.params.wbPathNum)(source.bits.data)) 672 sink.bits.pdest := source.bits.uop.pdest 673 sink.bits.robIdx := source.bits.uop.robIdx 674 sink.bits.intWen.foreach(_ := source.bits.uop.rfWen) 675 sink.bits.fpWen.foreach(_ := source.bits.uop.fpWen) 676 sink.bits.vecWen.foreach(_ := source.bits.uop.vecWen) 677 sink.bits.v0Wen.foreach(_ := source.bits.uop.v0Wen) 678 sink.bits.vlWen.foreach(_ := source.bits.uop.vlWen) 679 sink.bits.exceptionVec.foreach(_ := source.bits.uop.exceptionVec) 680 sink.bits.flushPipe.foreach(_ := source.bits.uop.flushPipe) 681 sink.bits.replay.foreach(_ := source.bits.uop.replayInst) 682 sink.bits.debug := source.bits.debug 683 sink.bits.debugInfo := source.bits.uop.debugInfo 684 sink.bits.lqIdx.foreach(_ := source.bits.uop.lqIdx) 685 sink.bits.sqIdx.foreach(_ := source.bits.uop.sqIdx) 686 sink.bits.predecodeInfo.foreach(_ := source.bits.uop.preDecodeInfo) 687 sink.bits.vls.foreach(x => { 688 x.vdIdx := source.bits.vdIdx.get 689 x.vdIdxInField := source.bits.vdIdxInField.get 690 x.vpu := source.bits.uop.vpu 691 x.oldVdPsrc := source.bits.uop.psrc(2) 692 x.isIndexed := VlduType.isIndexed(source.bits.uop.fuOpType) 693 x.isMasked := VlduType.isMasked(source.bits.uop.fuOpType) 694 x.isStrided := VlduType.isStrided(source.bits.uop.fuOpType) 695 x.isWhole := VlduType.isWhole(source.bits.uop.fuOpType) 696 x.isVecLoad := VlduType.isVecLd(source.bits.uop.fuOpType) 697 x.isVlm := VlduType.isMasked(source.bits.uop.fuOpType) && VlduType.isVecLd(source.bits.uop.fuOpType) 698 }) 699 sink.bits.trigger.foreach(_ := source.bits.uop.trigger) 700 } 701 wbDataPath.io.fromCSR.vstart := csrio.vpu.vstart 702 703 vecExcpMod.i.fromExceptionGen := ctrlBlock.io.toVecExcpMod.excpInfo 704 vecExcpMod.i.fromRab.logicPhyRegMap := ctrlBlock.io.toVecExcpMod.logicPhyRegMap 705 vecExcpMod.i.fromRat := ctrlBlock.io.toVecExcpMod.ratOldPest 706 vecExcpMod.i.fromVprf := dataPath.io.toVecExcpMod 707 708 // to mem 709 private val memIssueParams = params.memSchdParams.get.issueBlockParams 710 private val memExuBlocksHasLDU = memIssueParams.map(_.exuBlockParams.map(x => x.hasLoadFu || x.hasHyldaFu)) 711 private val memExuBlocksHasVecLoad = memIssueParams.map(_.exuBlockParams.map(x => x.hasVLoadFu)) 712 println(s"[Backend] memExuBlocksHasLDU: $memExuBlocksHasLDU") 713 println(s"[Backend] memExuBlocksHasVecLoad: $memExuBlocksHasVecLoad") 714 715 private val toMem = Wire(bypassNetwork.io.toExus.mem.cloneType) 716 for (i <- toMem.indices) { 717 for (j <- toMem(i).indices) { 718 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.mem(i)(j).bits.loadDependency, io.mem.ldCancel) 719 val needIssueTimeout = memExuBlocksHasLDU(i)(j) || memExuBlocksHasVecLoad(i)(j) 720 val issueTimeout = 721 if (needIssueTimeout) 722 Counter(0 until 16, toMem(i)(j).valid && !toMem(i)(j).fire, bypassNetwork.io.toExus.mem(i)(j).fire)._2 723 else 724 false.B 725 726 if (memScheduler.io.loadFinalIssueResp(i).nonEmpty && memExuBlocksHasLDU(i)(j)) { 727 memScheduler.io.loadFinalIssueResp(i)(j).valid := issueTimeout 728 memScheduler.io.loadFinalIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType 729 memScheduler.io.loadFinalIssueResp(i)(j).bits.resp := RespType.block 730 memScheduler.io.loadFinalIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx 731 memScheduler.io.loadFinalIssueResp(i)(j).bits.uopIdx.foreach(_ := toMem(i)(j).bits.vpu.get.vuopIdx) 732 memScheduler.io.loadFinalIssueResp(i)(j).bits.sqIdx.foreach(_ := toMem(i)(j).bits.sqIdx.get) 733 memScheduler.io.loadFinalIssueResp(i)(j).bits.lqIdx.foreach(_ := toMem(i)(j).bits.lqIdx.get) 734 } 735 736 if (memScheduler.io.vecLoadFinalIssueResp(i).nonEmpty && memExuBlocksHasVecLoad(i)(j)) { 737 memScheduler.io.vecLoadFinalIssueResp(i)(j).valid := issueTimeout 738 memScheduler.io.vecLoadFinalIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType 739 memScheduler.io.vecLoadFinalIssueResp(i)(j).bits.resp := RespType.block 740 memScheduler.io.vecLoadFinalIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx 741 memScheduler.io.vecLoadFinalIssueResp(i)(j).bits.uopIdx.foreach(_ := toMem(i)(j).bits.vpu.get.vuopIdx) 742 memScheduler.io.vecLoadFinalIssueResp(i)(j).bits.sqIdx.foreach(_ := toMem(i)(j).bits.sqIdx.get) 743 memScheduler.io.vecLoadFinalIssueResp(i)(j).bits.lqIdx.foreach(_ := toMem(i)(j).bits.lqIdx.get) 744 } 745 746 NewPipelineConnect( 747 bypassNetwork.io.toExus.mem(i)(j), toMem(i)(j), toMem(i)(j).fire, 748 Mux( 749 bypassNetwork.io.toExus.mem(i)(j).fire, 750 bypassNetwork.io.toExus.mem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 751 toMem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || issueTimeout 752 ), 753 Option("bypassNetwork2toMemExus") 754 ) 755 756 if (memScheduler.io.memAddrIssueResp(i).nonEmpty && memExuBlocksHasLDU(i)(j)) { 757 memScheduler.io.memAddrIssueResp(i)(j).valid := toMem(i)(j).fire && FuType.isLoad(toMem(i)(j).bits.fuType) 758 memScheduler.io.memAddrIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType 759 memScheduler.io.memAddrIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx 760 memScheduler.io.memAddrIssueResp(i)(j).bits.sqIdx.foreach(_ := toMem(i)(j).bits.sqIdx.get) 761 memScheduler.io.memAddrIssueResp(i)(j).bits.lqIdx.foreach(_ := toMem(i)(j).bits.lqIdx.get) 762 memScheduler.io.memAddrIssueResp(i)(j).bits.resp := RespType.success // for load inst, firing at toMem means issuing successfully 763 } 764 765 if (memScheduler.io.vecLoadIssueResp(i).nonEmpty && memExuBlocksHasVecLoad(i)(j)) { 766 memScheduler.io.vecLoadIssueResp(i)(j) match { 767 case resp => 768 resp.valid := toMem(i)(j).fire && VlduType.isVecLd(toMem(i)(j).bits.fuOpType) 769 resp.bits.fuType := toMem(i)(j).bits.fuType 770 resp.bits.robIdx := toMem(i)(j).bits.robIdx 771 resp.bits.uopIdx.get := toMem(i)(j).bits.vpu.get.vuopIdx 772 resp.bits.sqIdx.get := toMem(i)(j).bits.sqIdx.get 773 resp.bits.lqIdx.get := toMem(i)(j).bits.lqIdx.get 774 resp.bits.resp := RespType.success 775 } 776 if (backendParams.debugEn){ 777 dontTouch(memScheduler.io.vecLoadIssueResp(i)(j)) 778 } 779 } 780 } 781 } 782 783 io.mem.redirect := ctrlBlock.io.redirect 784 io.mem.issueUops.zip(toMem.flatten).foreach { case (sink, source) => 785 val enableMdp = Constantin.createRecord("EnableMdp", true) 786 sink.valid := source.valid 787 source.ready := sink.ready 788 sink.bits.iqIdx := source.bits.iqIdx 789 sink.bits.isFirstIssue := source.bits.isFirstIssue 790 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 791 sink.bits.src := 0.U.asTypeOf(sink.bits.src) 792 sink.bits.src.zip(source.bits.src).foreach { case (l, r) => l := r} 793 sink.bits.uop.fuType := source.bits.fuType 794 sink.bits.uop.fuOpType := source.bits.fuOpType 795 sink.bits.uop.imm := source.bits.imm 796 sink.bits.uop.robIdx := source.bits.robIdx 797 sink.bits.uop.pdest := source.bits.pdest 798 sink.bits.uop.rfWen := source.bits.rfWen.getOrElse(false.B) 799 sink.bits.uop.fpWen := source.bits.fpWen.getOrElse(false.B) 800 sink.bits.uop.vecWen := source.bits.vecWen.getOrElse(false.B) 801 sink.bits.uop.v0Wen := source.bits.v0Wen.getOrElse(false.B) 802 sink.bits.uop.vlWen := source.bits.vlWen.getOrElse(false.B) 803 sink.bits.uop.flushPipe := source.bits.flushPipe.getOrElse(false.B) 804 sink.bits.uop.pc := source.bits.pc.getOrElse(0.U) + (source.bits.ftqOffset.getOrElse(0.U) << instOffsetBits) 805 sink.bits.uop.loadWaitBit := Mux(enableMdp, source.bits.loadWaitBit.getOrElse(false.B), false.B) 806 sink.bits.uop.waitForRobIdx := Mux(enableMdp, source.bits.waitForRobIdx.getOrElse(0.U.asTypeOf(new RobPtr)), 0.U.asTypeOf(new RobPtr)) 807 sink.bits.uop.storeSetHit := Mux(enableMdp, source.bits.storeSetHit.getOrElse(false.B), false.B) 808 sink.bits.uop.loadWaitStrict := Mux(enableMdp, source.bits.loadWaitStrict.getOrElse(false.B), false.B) 809 sink.bits.uop.ssid := Mux(enableMdp, source.bits.ssid.getOrElse(0.U(SSIDWidth.W)), 0.U(SSIDWidth.W)) 810 sink.bits.uop.lqIdx := source.bits.lqIdx.getOrElse(0.U.asTypeOf(new LqPtr)) 811 sink.bits.uop.sqIdx := source.bits.sqIdx.getOrElse(0.U.asTypeOf(new SqPtr)) 812 sink.bits.uop.ftqPtr := source.bits.ftqIdx.getOrElse(0.U.asTypeOf(new FtqPtr)) 813 sink.bits.uop.ftqOffset := source.bits.ftqOffset.getOrElse(0.U) 814 sink.bits.uop.debugInfo := source.bits.perfDebugInfo 815 sink.bits.uop.vpu := source.bits.vpu.getOrElse(0.U.asTypeOf(new VPUCtrlSignals)) 816 sink.bits.uop.preDecodeInfo := source.bits.preDecode.getOrElse(0.U.asTypeOf(new PreDecodeInfo)) 817 sink.bits.uop.numLsElem := source.bits.numLsElem.getOrElse(0.U) // Todo: remove this bundle, keep only the one below 818 sink.bits.flowNum.foreach(_ := source.bits.numLsElem.get) 819 } 820 io.mem.loadFastMatch := memScheduler.io.toMem.get.loadFastMatch.map(_.fastMatch) 821 io.mem.loadFastImm := memScheduler.io.toMem.get.loadFastMatch.map(_.fastImm) 822 io.mem.tlbCsr := csrio.tlb 823 io.mem.csrCtrl := csrio.customCtrl 824 io.mem.sfence := fenceio.sfence 825 io.mem.isStoreException := CommitType.lsInstIsStore(ctrlBlock.io.robio.exception.bits.commitType) 826 io.mem.isVlsException := ctrlBlock.io.robio.exception.bits.vls 827 828 io.mem.storePcRead.zipWithIndex.foreach { case (storePcRead, i) => 829 storePcRead := ctrlBlock.io.memStPcRead(i).data 830 ctrlBlock.io.memStPcRead(i).valid := io.mem.issueSta(i).valid 831 ctrlBlock.io.memStPcRead(i).ptr := io.mem.issueSta(i).bits.uop.ftqPtr 832 ctrlBlock.io.memStPcRead(i).offset := io.mem.issueSta(i).bits.uop.ftqOffset 833 } 834 835 io.mem.hyuPcRead.zipWithIndex.foreach( { case (hyuPcRead, i) => 836 hyuPcRead := ctrlBlock.io.memHyPcRead(i).data 837 ctrlBlock.io.memHyPcRead(i).valid := io.mem.issueHylda(i).valid 838 ctrlBlock.io.memHyPcRead(i).ptr := io.mem.issueHylda(i).bits.uop.ftqPtr 839 ctrlBlock.io.memHyPcRead(i).offset := io.mem.issueHylda(i).bits.uop.ftqOffset 840 }) 841 842 ctrlBlock.io.robio.robHeadLsIssue := io.mem.issueUops.map(deq => deq.fire && deq.bits.uop.robIdx === ctrlBlock.io.robio.robDeqPtr).reduce(_ || _) 843 844 // mem io 845 io.mem.robLsqIO <> ctrlBlock.io.robio.lsq 846 io.mem.storeDebugInfo <> ctrlBlock.io.robio.storeDebugInfo 847 848 io.frontendSfence := fenceio.sfence 849 io.frontendTlbCsr := csrio.tlb 850 io.frontendCsrCtrl := csrio.customCtrl 851 852 io.tlb <> csrio.tlb 853 854 io.csrCustomCtrl := csrio.customCtrl 855 856 io.toTop.cpuHalted := ctrlBlock.io.toTop.cpuHalt 857 858 io.traceCoreInterface <> ctrlBlock.io.traceCoreInterface 859 860 io.debugTopDown.fromRob := ctrlBlock.io.debugTopDown.fromRob 861 ctrlBlock.io.debugTopDown.fromCore := io.debugTopDown.fromCore 862 863 io.debugRolling := ctrlBlock.io.debugRolling 864 865 io.topDownInfo.noUopsIssued := RegNext(dataPath.io.topDownInfo.noUopsIssued) 866 867 private val cg = ClockGate.genTeSrc 868 dontTouch(cg) 869 if(hasMbist) { 870 cg.cgen := io.dft_cgen.get 871 } else { 872 cg.cgen := false.B 873 } 874 875 if(backendParams.debugEn) { 876 dontTouch(memScheduler.io) 877 dontTouch(dataPath.io.toMemExu) 878 dontTouch(wbDataPath.io.fromMemExu) 879 } 880 881 // reset tree 882 if (p(DebugOptionsKey).ResetGen) { 883 val rightResetTree = ResetGenNode(Seq( 884 ModuleNode(dataPath), 885 ModuleNode(intExuBlock), 886 ModuleNode(fpExuBlock), 887 ModuleNode(vfExuBlock), 888 ModuleNode(bypassNetwork), 889 ModuleNode(wbDataPath) 890 )) 891 val leftResetTree = ResetGenNode(Seq( 892 ModuleNode(intScheduler), 893 ModuleNode(fpScheduler), 894 ModuleNode(vfScheduler), 895 ModuleNode(memScheduler), 896 ModuleNode(og2ForVector), 897 ModuleNode(wbFuBusyTable), 898 ResetGenNode(Seq( 899 ModuleNode(ctrlBlock), 900 // ResetGenNode(Seq( 901 CellNode(io.frontendReset) 902 // )) 903 )) 904 )) 905 ResetGen(leftResetTree, reset, sim = false, io.dft_reset) 906 ResetGen(rightResetTree, reset, sim = false, io.dft_reset) 907 } else { 908 io.frontendReset := DontCare 909 } 910 911 // perf events 912 val pfevent = Module(new PFEvent) 913 pfevent.io.distribute_csr := RegNext(csrio.customCtrl.distribute_csr) 914 val csrevents = pfevent.io.hpmevent.slice(8,16) 915 916 val ctrlBlockPerf = ctrlBlock.getPerfEvents 917 val intSchedulerPerf = intScheduler.asInstanceOf[SchedulerArithImp].getPerfEvents 918 val fpSchedulerPerf = fpScheduler.asInstanceOf[SchedulerArithImp].getPerfEvents 919 val vecSchedulerPerf = vfScheduler.asInstanceOf[SchedulerArithImp].getPerfEvents 920 val memSchedulerPerf = memScheduler.asInstanceOf[SchedulerMemImp].getPerfEvents 921 val dataPathPerf = dataPath.getPerfEvents 922 923 val perfBackend = Seq() 924 // let index = 0 be no event 925 val allPerfEvents = Seq(("noEvent", 0.U)) ++ ctrlBlockPerf ++ dataPathPerf ++ 926 intSchedulerPerf ++ fpSchedulerPerf ++ vecSchedulerPerf ++ memSchedulerPerf ++ perfBackend 927 928 929 if (printEventCoding) { 930 for (((name, inc), i) <- allPerfEvents.zipWithIndex) { 931 println("backend perfEvents Set", name, inc, i) 932 } 933 } 934 935 val allPerfInc = allPerfEvents.map(_._2.asTypeOf(new PerfEvent)) 936 val perfEvents = HPerfMonitor(csrevents, allPerfInc).getPerfEvents 937 csrio.perf.perfEventsBackend := VecInit(perfEvents.map(_._2.asTypeOf(new PerfEvent))) 938 939 val ctrlBlockError = ctrlBlock.getCriticalErrors 940 val intExuBlockError = intExuBlock.getCriticalErrors 941 val criticalErrors = ctrlBlockError ++ intExuBlockError 942 943 if (printCriticalError) { 944 for (((name, error), _) <- criticalErrors.zipWithIndex) { 945 XSError(error, s"critical error: $name \n") 946 } 947 } 948 949 // expand to collect frontend/memblock/L2 critical errors 950 backendCriticalError := criticalErrors.map(_._2).reduce(_ || _) 951 952 io.toTop.cpuCriticalError := csrio.criticalErrorState 953} 954 955class BackendMemIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 956 // Since fast load replay always use load unit 0, Backend flips two load port to avoid conflicts 957 val flippedLda = true 958 // params alias 959 private val LoadQueueSize = VirtualLoadQueueSize 960 // In/Out // Todo: split it into one-direction bundle 961 val lsqEnqIO = Flipped(new LsqEnqIO) 962 val robLsqIO = new RobLsqIO 963 val ldaIqFeedback = Vec(params.LduCnt, Flipped(new MemRSFeedbackIO)) 964 val staIqFeedback = Vec(params.StaCnt, Flipped(new MemRSFeedbackIO)) 965 val hyuIqFeedback = Vec(params.HyuCnt, Flipped(new MemRSFeedbackIO)) 966 val vstuIqFeedback = Flipped(Vec(params.VstuCnt, new MemRSFeedbackIO(isVector = true))) 967 val vlduIqFeedback = Flipped(Vec(params.VlduCnt, new MemRSFeedbackIO(isVector = true))) 968 val ldCancel = Vec(params.LdExuCnt, Input(new LoadCancelIO)) 969 val wakeup = Vec(params.LdExuCnt, Flipped(Valid(new DynInst))) 970 val storePcRead = Vec(params.StaCnt, Output(UInt(VAddrBits.W))) 971 val hyuPcRead = Vec(params.HyuCnt, Output(UInt(VAddrBits.W))) 972 // Input 973 val writebackLda = Vec(params.LduCnt, Flipped(DecoupledIO(new MemExuOutput))) 974 val writebackSta = Vec(params.StaCnt, Flipped(DecoupledIO(new MemExuOutput))) 975 val writebackStd = Vec(params.StdCnt, Flipped(DecoupledIO(new MemExuOutput))) 976 val writebackHyuLda = Vec(params.HyuCnt, Flipped(DecoupledIO(new MemExuOutput))) 977 val writebackHyuSta = Vec(params.HyuCnt, Flipped(DecoupledIO(new MemExuOutput))) 978 val writebackVldu = Vec(params.VlduCnt, Flipped(DecoupledIO(new MemExuOutput(true)))) 979 980 val s3_delayed_load_error = Input(Vec(LoadPipelineWidth, Bool())) 981 val stIn = Input(Vec(params.StaExuCnt, ValidIO(new DynInst()))) 982 val memoryViolation = Flipped(ValidIO(new Redirect)) 983 val exceptionAddr = Input(new Bundle { 984 val vaddr = UInt(XLEN.W) 985 val gpaddr = UInt(XLEN.W) 986 val isForVSnonLeafPTE = Bool() 987 }) 988 val sqDeq = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) 989 val lqDeq = Input(UInt(log2Up(CommitWidth + 1).W)) 990 val sqDeqPtr = Input(new SqPtr) 991 val lqDeqPtr = Input(new LqPtr) 992 993 val lqCancelCnt = Input(UInt(log2Up(VirtualLoadQueueSize + 1).W)) 994 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 995 996 val lqCanAccept = Input(Bool()) 997 val sqCanAccept = Input(Bool()) 998 999 val otherFastWakeup = Flipped(Vec(params.LduCnt + params.HyuCnt, ValidIO(new DynInst))) 1000 val stIssuePtr = Input(new SqPtr()) 1001 1002 val debugLS = Flipped(Output(new DebugLSIO)) 1003 1004 val lsTopdownInfo = Vec(params.LduCnt + params.HyuCnt, Flipped(Output(new LsTopdownInfo))) 1005 // Output 1006 val redirect = ValidIO(new Redirect) // rob flush MemBlock 1007 val issueLda = MixedVec(Seq.fill(params.LduCnt)(DecoupledIO(new MemExuInput()))) 1008 val issueSta = MixedVec(Seq.fill(params.StaCnt)(DecoupledIO(new MemExuInput()))) 1009 val issueStd = MixedVec(Seq.fill(params.StdCnt)(DecoupledIO(new MemExuInput()))) 1010 val issueHylda = MixedVec(Seq.fill(params.HyuCnt)(DecoupledIO(new MemExuInput()))) 1011 val issueHysta = MixedVec(Seq.fill(params.HyuCnt)(DecoupledIO(new MemExuInput()))) 1012 val issueVldu = MixedVec(Seq.fill(params.VlduCnt)(DecoupledIO(new MemExuInput(true)))) 1013 1014 val loadFastMatch = Vec(params.LduCnt, Output(UInt(params.LduCnt.W))) 1015 val loadFastImm = Vec(params.LduCnt, Output(UInt(12.W))) // Imm_I 1016 1017 val tlbCsr = Output(new TlbCsrBundle) 1018 val csrCtrl = Output(new CustomCSRCtrlIO) 1019 val sfence = Output(new SfenceBundle) 1020 val isStoreException = Output(Bool()) 1021 val isVlsException = Output(Bool()) 1022 1023 // ATTENTION: The issue ports' sequence order should be the same as IQs' deq config 1024 private [backend] def issueUops: Seq[DecoupledIO[MemExuInput]] = { 1025 issueSta ++ 1026 issueHylda ++ issueHysta ++ 1027 issueLda ++ 1028 issueVldu ++ 1029 issueStd 1030 }.toSeq 1031 1032 // ATTENTION: The writeback ports' sequence order should be the same as IQs' deq config 1033 private [backend] def writeBack: Seq[DecoupledIO[MemExuOutput]] = { 1034 writebackSta ++ 1035 writebackHyuLda ++ writebackHyuSta ++ 1036 writebackLda ++ 1037 writebackVldu ++ 1038 writebackStd 1039 } 1040 1041 // store event difftest information 1042 val storeDebugInfo = Vec(EnsbufferWidth, new Bundle { 1043 val robidx = Input(new RobPtr) 1044 val pc = Output(UInt(VAddrBits.W)) 1045 }) 1046} 1047 1048class TopToBackendBundle(implicit p: Parameters) extends XSBundle { 1049 val hartId = Output(UInt(hartIdLen.W)) 1050 val externalInterrupt = Output(new ExternalInterruptIO) 1051 val msiInfo = Output(ValidIO(new MsiInfoBundle)) 1052 val clintTime = Output(ValidIO(UInt(64.W))) 1053 val l2FlushDone = Output(Bool()) 1054} 1055 1056class BackendToTopBundle extends Bundle { 1057 val cpuHalted = Output(Bool()) 1058 val cpuCriticalError = Output(Bool()) 1059} 1060 1061class BackendIO(implicit p: Parameters, params: BackendParams) extends XSBundle with HasSoCParameter { 1062 val fromTop = Flipped(new TopToBackendBundle) 1063 1064 val toTop = new BackendToTopBundle 1065 1066 val traceCoreInterface = new TraceCoreInterface(hasOffset = true) 1067 val fenceio = new FenceIO 1068 // Todo: merge these bundles into BackendFrontendIO 1069 val frontend = Flipped(new FrontendToCtrlIO) 1070 val frontendSfence = Output(new SfenceBundle) 1071 val frontendCsrCtrl = Output(new CustomCSRCtrlIO) 1072 val frontendTlbCsr = Output(new TlbCsrBundle) 1073 val frontendReset = Output(Reset()) 1074 1075 val mem = new BackendMemIO 1076 1077 val perf = Input(new PerfCounterIO) 1078 1079 val tlb = Output(new TlbCsrBundle) 1080 1081 val csrCustomCtrl = Output(new CustomCSRCtrlIO) 1082 1083 val debugTopDown = new Bundle { 1084 val fromRob = new RobCoreTopDownIO 1085 val fromCore = new CoreDispatchTopDownIO 1086 } 1087 val debugRolling = new RobDebugRollingIO 1088 val topDownInfo = new TopDownInfo 1089 val dft_reset = if(hasMbist) Some(Input(new DFTResetSignals)) else None 1090 val dft_cgen = if(hasMbist) Some(Input(Bool())) else None 1091} 1092