1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 23import utility.{Constantin, ZeroExt} 24import xiangshan._ 25import xiangshan.backend.Bundles.{DynInst, IssueQueueIQWakeUpBundle, LoadShouldCancel, MemExuInput, MemExuOutput, VPUCtrlSignals} 26import xiangshan.backend.ctrlblock.{DebugLSIO, LsTopdownInfo} 27import xiangshan.backend.datapath.DataConfig.{IntData, VecData, FpData} 28import xiangshan.backend.datapath.RdConfig.{IntRD, VfRD} 29import xiangshan.backend.datapath.WbConfig._ 30import xiangshan.backend.datapath._ 31import xiangshan.backend.dispatch.CoreDispatchTopDownIO 32import xiangshan.backend.exu.ExuBlock 33import xiangshan.backend.fu.vector.Bundles.{VConfig, VType} 34import xiangshan.backend.fu.{FenceIO, FenceToSbuffer, FuConfig, FuType, PerfCounterIO} 35import xiangshan.backend.issue.EntryBundles._ 36import xiangshan.backend.issue.{CancelNetwork, Scheduler, SchedulerImpBase} 37import xiangshan.backend.rob.{RobCoreTopDownIO, RobDebugRollingIO, RobLsqIO, RobPtr} 38import xiangshan.frontend.{FtqPtr, FtqRead, PreDecodeInfo} 39import xiangshan.mem.{LqPtr, LsqEnqIO, SqPtr} 40import scala.collection.mutable 41 42class Backend(val params: BackendParams)(implicit p: Parameters) extends LazyModule 43 with HasXSParameter { 44 45 override def shouldBeInlined: Boolean = false 46 47 // check read & write port config 48 params.configChecks 49 50 /* Only update the idx in mem-scheduler here 51 * Idx in other schedulers can be updated the same way if needed 52 * 53 * Also note that we filter out the 'stData issue-queues' when counting 54 */ 55 for ((ibp, idx) <- params.memSchdParams.get.issueBlockParams.filter(iq => iq.StdCnt == 0).zipWithIndex) { 56 ibp.updateIdx(idx) 57 } 58 59 println(params.iqWakeUpParams) 60 61 for ((schdCfg, i) <- params.allSchdParams.zipWithIndex) { 62 schdCfg.bindBackendParam(params) 63 } 64 65 for ((iqCfg, i) <- params.allIssueParams.zipWithIndex) { 66 iqCfg.bindBackendParam(params) 67 } 68 69 for ((exuCfg, i) <- params.allExuParams.zipWithIndex) { 70 exuCfg.bindBackendParam(params) 71 exuCfg.updateIQWakeUpConfigs(params.iqWakeUpParams) 72 exuCfg.updateExuIdx(i) 73 } 74 75 println("[Backend] ExuConfigs:") 76 for (exuCfg <- params.allExuParams) { 77 val fuConfigs = exuCfg.fuConfigs 78 val wbPortConfigs = exuCfg.wbPortConfigs 79 val immType = exuCfg.immType 80 81 println("[Backend] " + 82 s"${exuCfg.name}: " + 83 (if (exuCfg.fakeUnit) "fake, " else "") + 84 (if (exuCfg.hasLoadFu || exuCfg.hasHyldaFu) s"LdExuIdx(${backendParams.getLdExuIdx(exuCfg)})" else "") + 85 s"${fuConfigs.map(_.name).mkString("fu(s): {", ",", "}")}, " + 86 s"${wbPortConfigs.mkString("wb: {", ",", "}")}, " + 87 s"${immType.map(SelImm.mkString(_)).mkString("imm: {", ",", "}")}, " + 88 s"latMax(${exuCfg.latencyValMax}), ${exuCfg.fuLatancySet.mkString("lat: {", ",", "}")}, " + 89 s"srcReg(${exuCfg.numRegSrc})" 90 ) 91 require( 92 wbPortConfigs.collectFirst { case x: IntWB => x }.nonEmpty == 93 fuConfigs.map(_.writeIntRf).reduce(_ || _), 94 s"${exuCfg.name} int wb port has no priority" 95 ) 96 require( 97 wbPortConfigs.collectFirst { case x: FpWB => x }.nonEmpty == 98 fuConfigs.map(x => x.writeFpRf).reduce(_ || _), 99 s"${exuCfg.name} fp wb port has no priority" 100 ) 101 require( 102 wbPortConfigs.collectFirst { case x: VfWB => x }.nonEmpty == 103 fuConfigs.map(x => x.writeVecRf).reduce(_ || _), 104 s"${exuCfg.name} vec wb port has no priority" 105 ) 106 } 107 108 println(s"[Backend] all fu configs") 109 for (cfg <- FuConfig.allConfigs) { 110 println(s"[Backend] $cfg") 111 } 112 113 println(s"[Backend] Int RdConfigs: ExuName(Priority)") 114 for ((port, seq) <- params.getRdPortParams(IntData())) { 115 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 116 } 117 118 println(s"[Backend] Int WbConfigs: ExuName(Priority)") 119 for ((port, seq) <- params.getWbPortParams(IntData())) { 120 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 121 } 122 123 println(s"[Backend] Fp RdConfigs: ExuName(Priority)") 124 for ((port, seq) <- params.getRdPortParams(FpData())) { 125 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 126 } 127 128 println(s"[Backend] Fp WbConfigs: ExuName(Priority)") 129 for ((port, seq) <- params.getWbPortParams(FpData())) { 130 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 131 } 132 133 println(s"[Backend] Vf RdConfigs: ExuName(Priority)") 134 for ((port, seq) <- params.getRdPortParams(VecData())) { 135 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 136 } 137 138 println(s"[Backend] Vf WbConfigs: ExuName(Priority)") 139 for ((port, seq) <- params.getWbPortParams(VecData())) { 140 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 141 } 142 143 println(s"[Backend] Dispatch Configs:") 144 println(s"[Backend] Load IQ enq width(${params.numLoadDp}), Store IQ enq width(${params.numStoreDp})") 145 println(s"[Backend] Load DP width(${LSQLdEnqWidth}), Store DP width(${LSQStEnqWidth})") 146 147 params.updateCopyPdestInfo 148 println(s"[Backend] copyPdestInfo ${params.copyPdestInfo}") 149 params.allExuParams.map(_.copyNum) 150 val ctrlBlock = LazyModule(new CtrlBlock(params)) 151 val pcTargetMem = LazyModule(new PcTargetMem(params)) 152 val intScheduler = params.intSchdParams.map(x => LazyModule(new Scheduler(x))) 153 val fpScheduler = params.fpSchdParams.map(x => LazyModule(new Scheduler(x))) 154 val vfScheduler = params.vfSchdParams.map(x => LazyModule(new Scheduler(x))) 155 val memScheduler = params.memSchdParams.map(x => LazyModule(new Scheduler(x))) 156 val dataPath = LazyModule(new DataPath(params)) 157 val intExuBlock = params.intSchdParams.map(x => LazyModule(new ExuBlock(x))) 158 val fpExuBlock = params.fpSchdParams.map(x => LazyModule(new ExuBlock(x))) 159 val vfExuBlock = params.vfSchdParams.map(x => LazyModule(new ExuBlock(x))) 160 val wbFuBusyTable = LazyModule(new WbFuBusyTable(params)) 161 162 lazy val module = new BackendImp(this) 163} 164 165class BackendImp(override val wrapper: Backend)(implicit p: Parameters) extends LazyModuleImp(wrapper) 166 with HasXSParameter { 167 implicit private val params = wrapper.params 168 169 val io = IO(new BackendIO()(p, wrapper.params)) 170 171 private val ctrlBlock = wrapper.ctrlBlock.module 172 private val pcTargetMem = wrapper.pcTargetMem.module 173 private val intScheduler: SchedulerImpBase = wrapper.intScheduler.get.module 174 private val fpScheduler = wrapper.fpScheduler.get.module 175 private val vfScheduler = wrapper.vfScheduler.get.module 176 private val memScheduler = wrapper.memScheduler.get.module 177 private val dataPath = wrapper.dataPath.module 178 private val intExuBlock = wrapper.intExuBlock.get.module 179 private val fpExuBlock = wrapper.fpExuBlock.get.module 180 private val vfExuBlock = wrapper.vfExuBlock.get.module 181 private val og2ForVector = Module(new Og2ForVector(params)) 182 private val bypassNetwork = Module(new BypassNetwork) 183 private val wbDataPath = Module(new WbDataPath(params)) 184 private val wbFuBusyTable = wrapper.wbFuBusyTable.module 185 186 private val iqWakeUpMappedBundle: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = ( 187 intScheduler.io.toSchedulers.wakeupVec ++ 188 fpScheduler.io.toSchedulers.wakeupVec ++ 189 vfScheduler.io.toSchedulers.wakeupVec ++ 190 memScheduler.io.toSchedulers.wakeupVec 191 ).map(x => (x.bits.exuIdx, x)).toMap 192 193 println(s"[Backend] iq wake up keys: ${iqWakeUpMappedBundle.keys}") 194 195 wbFuBusyTable.io.in.intSchdBusyTable := intScheduler.io.wbFuBusyTable 196 wbFuBusyTable.io.in.fpSchdBusyTable := fpScheduler.io.wbFuBusyTable 197 wbFuBusyTable.io.in.vfSchdBusyTable := vfScheduler.io.wbFuBusyTable 198 wbFuBusyTable.io.in.memSchdBusyTable := memScheduler.io.wbFuBusyTable 199 intScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.intRespRead 200 fpScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.fpRespRead 201 vfScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.vfRespRead 202 memScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.memRespRead 203 dataPath.io.wbConfictRead := wbFuBusyTable.io.out.wbConflictRead 204 205 private val og1CancelOH: UInt = dataPath.io.og1CancelOH 206 private val og0CancelOH: UInt = dataPath.io.og0CancelOH 207 private val cancelToBusyTable = dataPath.io.cancelToBusyTable 208 209 ctrlBlock.io.IQValidNumVec := intScheduler.io.IQValidNumVec 210 ctrlBlock.io.fromTop.hartId := io.fromTop.hartId 211 ctrlBlock.io.frontend <> io.frontend 212 ctrlBlock.io.fromWB.wbData <> wbDataPath.io.toCtrlBlock.writeback 213 ctrlBlock.io.fromMem.stIn <> io.mem.stIn 214 ctrlBlock.io.fromMem.violation <> io.mem.memoryViolation 215 ctrlBlock.io.lqCanAccept := io.mem.lqCanAccept 216 ctrlBlock.io.sqCanAccept := io.mem.sqCanAccept 217 ctrlBlock.io.csrCtrl <> intExuBlock.io.csrio.get.customCtrl 218 ctrlBlock.io.robio.csr.intrBitSet := intExuBlock.io.csrio.get.interrupt 219 ctrlBlock.io.robio.csr.trapTarget := intExuBlock.io.csrio.get.trapTarget 220 ctrlBlock.io.robio.csr.isXRet := intExuBlock.io.csrio.get.isXRet 221 ctrlBlock.io.robio.csr.wfiEvent := intExuBlock.io.csrio.get.wfi_event 222 ctrlBlock.io.robio.lsq <> io.mem.robLsqIO 223 ctrlBlock.io.robio.lsTopdownInfo <> io.mem.lsTopdownInfo 224 ctrlBlock.io.robio.debug_ls <> io.mem.debugLS 225 ctrlBlock.perfinfo := DontCare // TODO: Implement backend hpm 226 ctrlBlock.io.debugEnqLsq.canAccept := io.mem.lsqEnqIO.canAccept 227 ctrlBlock.io.debugEnqLsq.resp := io.mem.lsqEnqIO.resp 228 ctrlBlock.io.debugEnqLsq.req := memScheduler.io.memIO.get.lsqEnqIO.req 229 ctrlBlock.io.debugEnqLsq.needAlloc := memScheduler.io.memIO.get.lsqEnqIO.needAlloc 230 231 intScheduler.io.fromTop.hartId := io.fromTop.hartId 232 intScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 233 intScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 234 intScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.intUops 235 intScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 236 intScheduler.io.fpWriteBack := 0.U.asTypeOf(intScheduler.io.fpWriteBack) 237 intScheduler.io.vfWriteBack := 0.U.asTypeOf(intScheduler.io.vfWriteBack) 238 intScheduler.io.fromDataPath.resp := dataPath.io.toIntIQ 239 intScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 240 intScheduler.io.fromDataPath.og0Cancel := og0CancelOH 241 intScheduler.io.fromDataPath.og1Cancel := og1CancelOH 242 intScheduler.io.ldCancel := io.mem.ldCancel 243 intScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 244 245 fpScheduler.io.fromTop.hartId := io.fromTop.hartId 246 fpScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 247 fpScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 248 fpScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.fpUops 249 fpScheduler.io.intWriteBack := 0.U.asTypeOf(fpScheduler.io.intWriteBack) 250 fpScheduler.io.fpWriteBack := wbDataPath.io.toFpPreg 251 fpScheduler.io.vfWriteBack := 0.U.asTypeOf(fpScheduler.io.vfWriteBack) 252 fpScheduler.io.fromDataPath.resp := dataPath.io.toFpIQ 253 fpScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 254 fpScheduler.io.fromDataPath.og0Cancel := og0CancelOH 255 fpScheduler.io.fromDataPath.og1Cancel := og1CancelOH 256 fpScheduler.io.ldCancel := io.mem.ldCancel 257 fpScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 258 259 memScheduler.io.fromTop.hartId := io.fromTop.hartId 260 memScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 261 memScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 262 memScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.memUops 263 memScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 264 memScheduler.io.fpWriteBack := wbDataPath.io.toFpPreg 265 memScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 266 memScheduler.io.fromMem.get.scommit := io.mem.sqDeq 267 memScheduler.io.fromMem.get.lcommit := io.mem.lqDeq 268 memScheduler.io.fromMem.get.wakeup := io.mem.wakeup 269 memScheduler.io.fromMem.get.sqDeqPtr := io.mem.sqDeqPtr 270 memScheduler.io.fromMem.get.lqDeqPtr := io.mem.lqDeqPtr 271 memScheduler.io.fromMem.get.sqCancelCnt := io.mem.sqCancelCnt 272 memScheduler.io.fromMem.get.lqCancelCnt := io.mem.lqCancelCnt 273 memScheduler.io.fromMem.get.stIssuePtr := io.mem.stIssuePtr 274 require(memScheduler.io.fromMem.get.memWaitUpdateReq.robIdx.length == io.mem.stIn.length) 275 memScheduler.io.fromMem.get.memWaitUpdateReq.robIdx.zip(io.mem.stIn).foreach { case (sink, source) => 276 sink.valid := source.valid 277 sink.bits := source.bits.robIdx 278 } 279 memScheduler.io.fromMem.get.memWaitUpdateReq.sqIdx := DontCare // TODO 280 memScheduler.io.fromDataPath.resp := dataPath.io.toMemIQ 281 memScheduler.io.fromMem.get.ldaFeedback := io.mem.ldaIqFeedback 282 memScheduler.io.fromMem.get.staFeedback := io.mem.staIqFeedback 283 memScheduler.io.fromMem.get.hyuFeedback := io.mem.hyuIqFeedback 284 memScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 285 memScheduler.io.fromDataPath.og0Cancel := og0CancelOH 286 memScheduler.io.fromDataPath.og1Cancel := og1CancelOH 287 memScheduler.io.ldCancel := io.mem.ldCancel 288 memScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 289 290 vfScheduler.io.fromTop.hartId := io.fromTop.hartId 291 vfScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 292 vfScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 293 vfScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.vfUops 294 vfScheduler.io.intWriteBack := 0.U.asTypeOf(vfScheduler.io.intWriteBack) 295 vfScheduler.io.fpWriteBack := 0.U.asTypeOf(vfScheduler.io.fpWriteBack) 296 vfScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 297 vfScheduler.io.fromDataPath.resp := dataPath.io.toVfIQ 298 vfScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 299 vfScheduler.io.fromDataPath.og0Cancel := og0CancelOH 300 vfScheduler.io.fromDataPath.og1Cancel := og1CancelOH 301 vfScheduler.io.ldCancel := io.mem.ldCancel 302 vfScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 303 vfScheduler.io.fromOg2.get := og2ForVector.io.toVfIQ 304 305 dataPath.io.hartId := io.fromTop.hartId 306 dataPath.io.flush := ctrlBlock.io.toDataPath.flush 307 308 dataPath.io.fromIntIQ <> intScheduler.io.toDataPathAfterDelay 309 dataPath.io.fromFpIQ <> fpScheduler.io.toDataPathAfterDelay 310 dataPath.io.fromVfIQ <> vfScheduler.io.toDataPathAfterDelay 311 dataPath.io.fromMemIQ <> memScheduler.io.toDataPathAfterDelay 312 313 dataPath.io.ldCancel := io.mem.ldCancel 314 315 println(s"[Backend] wbDataPath.io.toIntPreg: ${wbDataPath.io.toIntPreg.size}, dataPath.io.fromIntWb: ${dataPath.io.fromIntWb.size}") 316 println(s"[Backend] wbDataPath.io.toVfPreg: ${wbDataPath.io.toVfPreg.size}, dataPath.io.fromFpWb: ${dataPath.io.fromVfWb.size}") 317 dataPath.io.fromIntWb := wbDataPath.io.toIntPreg 318 dataPath.io.fromFpWb := wbDataPath.io.toFpPreg 319 dataPath.io.fromVfWb := wbDataPath.io.toVfPreg 320 dataPath.io.debugIntRat .foreach(_ := ctrlBlock.io.debug_int_rat.get) 321 dataPath.io.debugFpRat .foreach(_ := ctrlBlock.io.debug_fp_rat.get) 322 dataPath.io.debugVecRat .foreach(_ := ctrlBlock.io.debug_vec_rat.get) 323 dataPath.io.debugVconfigRat.foreach(_ := ctrlBlock.io.debug_vconfig_rat.get) 324 325 og2ForVector.io.flush := ctrlBlock.io.toDataPath.flush 326 og2ForVector.io.ldCancel := io.mem.ldCancel 327 og2ForVector.io.fromOg1NoReg <> dataPath.io.toVecExu 328 329 bypassNetwork.io.fromDataPath.int <> dataPath.io.toIntExu 330 bypassNetwork.io.fromDataPath.fp <> dataPath.io.toFpExu 331 bypassNetwork.io.fromDataPath.vf <> og2ForVector.io.toVfExu 332 bypassNetwork.io.fromDataPath.mem <> dataPath.io.toMemExu 333 bypassNetwork.io.fromDataPath.immInfo := dataPath.io.og1ImmInfo 334 bypassNetwork.io.fromExus.connectExuOutput(_.int)(intExuBlock.io.out) 335 bypassNetwork.io.fromExus.connectExuOutput(_.fp)(fpExuBlock.io.out) 336 bypassNetwork.io.fromExus.connectExuOutput(_.vf)(vfExuBlock.io.out) 337 338 require(bypassNetwork.io.fromExus.mem.flatten.size == io.mem.writeBack.size, 339 s"bypassNetwork.io.fromExus.mem.flatten.size(${bypassNetwork.io.fromExus.mem.flatten.size}: ${bypassNetwork.io.fromExus.mem.map(_.size)}, " + 340 s"io.mem.writeback(${io.mem.writeBack.size})" 341 ) 342 bypassNetwork.io.fromExus.mem.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 343 sink.valid := source.valid 344 sink.bits.pdest := source.bits.uop.pdest 345 sink.bits.data := source.bits.data 346 } 347 348 349 intExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 350 for (i <- 0 until intExuBlock.io.in.length) { 351 for (j <- 0 until intExuBlock.io.in(i).length) { 352 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.int(i)(j).bits.loadDependency, io.mem.ldCancel) 353 NewPipelineConnect( 354 bypassNetwork.io.toExus.int(i)(j), intExuBlock.io.in(i)(j), intExuBlock.io.in(i)(j).fire, 355 Mux( 356 bypassNetwork.io.toExus.int(i)(j).fire, 357 bypassNetwork.io.toExus.int(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 358 intExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 359 ), 360 Option("bypassNetwork2intExuBlock") 361 ) 362 } 363 } 364 365 pcTargetMem.io.fromFrontendFtq := io.frontend.fromFtq 366 pcTargetMem.io.toDataPath <> dataPath.io.fromPcTargetMem 367 368 private val csrio = intExuBlock.io.csrio.get 369 csrio.hartId := io.fromTop.hartId 370 csrio.fpu.fflags := ctrlBlock.io.robio.csr.fflags 371 csrio.fpu.isIllegal := false.B // Todo: remove it 372 csrio.fpu.dirty_fs := ctrlBlock.io.robio.csr.dirty_fs 373 csrio.vpu <> 0.U.asTypeOf(csrio.vpu) // Todo 374 375 val vsetvlVType = intExuBlock.io.vtype.getOrElse(0.U.asTypeOf(new VType)) 376 ctrlBlock.io.robio.vsetvlVType := vsetvlVType 377 378 val debugVconfig = dataPath.io.debugVconfig match { 379 case Some(x) => dataPath.io.debugVconfig.get.asTypeOf(new VConfig) 380 case None => 0.U.asTypeOf(new VConfig) 381 } 382 val commitVType = ctrlBlock.io.robio.commitVType.vtype 383 val hasVsetvl = ctrlBlock.io.robio.commitVType.hasVsetvl 384 val vtype = VType.toVtypeStruct(Mux(hasVsetvl, vsetvlVType, commitVType.bits)).asUInt 385 val debugVl = debugVconfig.vl 386 csrio.vpu.set_vxsat := ctrlBlock.io.robio.csr.vxsat 387 csrio.vpu.set_vstart.valid := ctrlBlock.io.robio.csr.vstart.valid 388 csrio.vpu.set_vstart.bits := ctrlBlock.io.robio.csr.vstart.bits 389 csrio.vpu.set_vtype.valid := ctrlBlock.io.robio.csr.vcsrFlag 390 //Todo here need change design 391 csrio.vpu.set_vtype.valid := commitVType.valid 392 csrio.vpu.set_vtype.bits := ZeroExt(vtype, XLEN) 393 csrio.vpu.set_vl.valid := ctrlBlock.io.robio.csr.vcsrFlag 394 csrio.vpu.set_vl.bits := ZeroExt(debugVl, XLEN) 395 csrio.vpu.dirty_vs := ctrlBlock.io.robio.csr.dirty_vs 396 csrio.exception := ctrlBlock.io.robio.exception 397 csrio.memExceptionVAddr := io.mem.exceptionAddr.vaddr 398 csrio.memExceptionGPAddr := io.mem.exceptionAddr.gpaddr 399 csrio.externalInterrupt := io.fromTop.externalInterrupt 400 csrio.distributedUpdate(0) := io.mem.csrDistributedUpdate 401 csrio.distributedUpdate(1) := io.frontendCsrDistributedUpdate 402 csrio.perf <> io.perf 403 csrio.perf.retiredInstr <> ctrlBlock.io.robio.csr.perfinfo.retiredInstr 404 csrio.perf.ctrlInfo <> ctrlBlock.io.perfInfo.ctrlInfo 405 csrio.perf.perfEventsCtrl <> ctrlBlock.getPerf 406 private val fenceio = intExuBlock.io.fenceio.get 407 io.fenceio <> fenceio 408 fenceio.disableSfence := csrio.disableSfence 409 fenceio.disableHfenceg := csrio.disableHfenceg 410 fenceio.disableHfencev := csrio.disableHfencev 411 fenceio.virtMode := csrio.customCtrl.virtMode 412 413 // to fpExuBlock 414 fpExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 415 for (i <- 0 until fpExuBlock.io.in.length) { 416 for (j <- 0 until fpExuBlock.io.in(i).length) { 417 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.fp(i)(j).bits.loadDependency, io.mem.ldCancel) 418 NewPipelineConnect( 419 bypassNetwork.io.toExus.fp(i)(j), fpExuBlock.io.in(i)(j), fpExuBlock.io.in(i)(j).fire, 420 Mux( 421 bypassNetwork.io.toExus.fp(i)(j).fire, 422 bypassNetwork.io.toExus.fp(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 423 fpExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 424 ), 425 Option("bypassNetwork2fpExuBlock") 426 ) 427 } 428 } 429 430 vfExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 431 for (i <- 0 until vfExuBlock.io.in.size) { 432 for (j <- 0 until vfExuBlock.io.in(i).size) { 433 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.vf(i)(j).bits.loadDependency, io.mem.ldCancel) 434 NewPipelineConnect( 435 bypassNetwork.io.toExus.vf(i)(j), vfExuBlock.io.in(i)(j), vfExuBlock.io.in(i)(j).fire, 436 Mux( 437 bypassNetwork.io.toExus.vf(i)(j).fire, 438 bypassNetwork.io.toExus.vf(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 439 vfExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 440 ), 441 Option("bypassNetwork2vfExuBlock") 442 ) 443 444 vfExuBlock.io.in(i)(j).bits.vpu.foreach(_.vstart := csrio.vpu.vstart) 445 } 446 } 447 448 intExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 449 fpExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 450 fpExuBlock.io.vxrm.foreach(_ := csrio.vpu.vxrm) 451 vfExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 452 vfExuBlock.io.vxrm.foreach(_ := csrio.vpu.vxrm) 453 454 wbDataPath.io.flush := ctrlBlock.io.redirect 455 wbDataPath.io.fromTop.hartId := io.fromTop.hartId 456 wbDataPath.io.fromIntExu <> intExuBlock.io.out 457 wbDataPath.io.fromFpExu <> fpExuBlock.io.out 458 wbDataPath.io.fromVfExu <> vfExuBlock.io.out 459 wbDataPath.io.fromMemExu.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 460 sink.valid := source.valid 461 source.ready := sink.ready 462 sink.bits.data := source.bits.data 463 sink.bits.pdest := source.bits.uop.pdest 464 sink.bits.robIdx := source.bits.uop.robIdx 465 sink.bits.intWen.foreach(_ := source.bits.uop.rfWen) 466 sink.bits.fpWen.foreach(_ := source.bits.uop.fpWen) 467 sink.bits.vecWen.foreach(_ := source.bits.uop.vecWen) 468 sink.bits.exceptionVec.foreach(_ := source.bits.uop.exceptionVec) 469 sink.bits.flushPipe.foreach(_ := source.bits.uop.flushPipe) 470 sink.bits.replay.foreach(_ := source.bits.uop.replayInst) 471 sink.bits.debug := source.bits.debug 472 sink.bits.debugInfo := source.bits.uop.debugInfo 473 sink.bits.lqIdx.foreach(_ := source.bits.uop.lqIdx) 474 sink.bits.sqIdx.foreach(_ := source.bits.uop.sqIdx) 475 sink.bits.predecodeInfo.foreach(_ := source.bits.uop.preDecodeInfo) 476 sink.bits.vls.foreach(x => { 477 x.vdIdx := source.bits.vdIdx.get 478 x.vdIdxInField := source.bits.vdIdxInField.get 479 x.vpu := source.bits.uop.vpu 480 x.oldVdPsrc := source.bits.uop.psrc(2) 481 x.isIndexed := VlduType.isIndexed(source.bits.uop.fuOpType) 482 x.isMasked := VlduType.isMasked(source.bits.uop.fuOpType) 483 }) 484 sink.bits.trigger.foreach(_ := source.bits.uop.trigger) 485 } 486 487 // to mem 488 private val memIssueParams = params.memSchdParams.get.issueBlockParams 489 private val memExuBlocksHasLDU = memIssueParams.map(_.exuBlockParams.map(x => x.hasLoadFu || x.hasHyldaFu)) 490 println(s"[Backend] memExuBlocksHasLDU: $memExuBlocksHasLDU") 491 492 private val toMem = Wire(bypassNetwork.io.toExus.mem.cloneType) 493 for (i <- toMem.indices) { 494 for (j <- toMem(i).indices) { 495 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.mem(i)(j).bits.loadDependency, io.mem.ldCancel) 496 val issueTimeout = 497 if (memExuBlocksHasLDU(i)(j)) 498 Counter(0 until 16, toMem(i)(j).valid && !toMem(i)(j).fire, bypassNetwork.io.toExus.mem(i)(j).fire)._2 499 else 500 false.B 501 502 if (memScheduler.io.loadFinalIssueResp(i).nonEmpty && memExuBlocksHasLDU(i)(j)) { 503 memScheduler.io.loadFinalIssueResp(i)(j).valid := issueTimeout 504 memScheduler.io.loadFinalIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType 505 memScheduler.io.loadFinalIssueResp(i)(j).bits.resp := RespType.block 506 memScheduler.io.loadFinalIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx 507 memScheduler.io.loadFinalIssueResp(i)(j).bits.uopIdx.foreach(_ := toMem(i)(j).bits.vpu.get.vuopIdx) 508 } 509 510 NewPipelineConnect( 511 bypassNetwork.io.toExus.mem(i)(j), toMem(i)(j), toMem(i)(j).fire, 512 Mux( 513 bypassNetwork.io.toExus.mem(i)(j).fire, 514 bypassNetwork.io.toExus.mem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 515 toMem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || issueTimeout 516 ), 517 Option("bypassNetwork2toMemExus") 518 ) 519 520 if (memScheduler.io.memAddrIssueResp(i).nonEmpty && memExuBlocksHasLDU(i)(j)) { 521 memScheduler.io.memAddrIssueResp(i)(j).valid := toMem(i)(j).fire && FuType.isLoad(toMem(i)(j).bits.fuType) 522 memScheduler.io.memAddrIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType 523 memScheduler.io.memAddrIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx 524 memScheduler.io.memAddrIssueResp(i)(j).bits.resp := RespType.success // for load inst, firing at toMem means issuing successfully 525 } 526 } 527 } 528 529 io.mem.redirect := ctrlBlock.io.redirect 530 io.mem.issueUops.zip(toMem.flatten).foreach { case (sink, source) => 531 val enableMdp = Constantin.createRecord("EnableMdp", true) 532 sink.valid := source.valid 533 source.ready := sink.ready 534 sink.bits.iqIdx := source.bits.iqIdx 535 sink.bits.isFirstIssue := source.bits.isFirstIssue 536 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 537 sink.bits.src := 0.U.asTypeOf(sink.bits.src) 538 sink.bits.src.zip(source.bits.src).foreach { case (l, r) => l := r} 539 sink.bits.uop.fuType := source.bits.fuType 540 sink.bits.uop.fuOpType := source.bits.fuOpType 541 sink.bits.uop.imm := source.bits.imm 542 sink.bits.uop.robIdx := source.bits.robIdx 543 sink.bits.uop.pdest := source.bits.pdest 544 sink.bits.uop.rfWen := source.bits.rfWen.getOrElse(false.B) 545 sink.bits.uop.fpWen := source.bits.fpWen.getOrElse(false.B) 546 sink.bits.uop.vecWen := source.bits.vecWen.getOrElse(false.B) 547 sink.bits.uop.flushPipe := source.bits.flushPipe.getOrElse(false.B) 548 sink.bits.uop.pc := source.bits.pc.getOrElse(0.U) 549 sink.bits.uop.loadWaitBit := Mux(enableMdp, source.bits.loadWaitBit.getOrElse(false.B), false.B) 550 sink.bits.uop.waitForRobIdx := Mux(enableMdp, source.bits.waitForRobIdx.getOrElse(0.U.asTypeOf(new RobPtr)), 0.U.asTypeOf(new RobPtr)) 551 sink.bits.uop.storeSetHit := Mux(enableMdp, source.bits.storeSetHit.getOrElse(false.B), false.B) 552 sink.bits.uop.loadWaitStrict := Mux(enableMdp, source.bits.loadWaitStrict.getOrElse(false.B), false.B) 553 sink.bits.uop.ssid := Mux(enableMdp, source.bits.ssid.getOrElse(0.U(SSIDWidth.W)), 0.U(SSIDWidth.W)) 554 sink.bits.uop.lqIdx := source.bits.lqIdx.getOrElse(0.U.asTypeOf(new LqPtr)) 555 sink.bits.uop.sqIdx := source.bits.sqIdx.getOrElse(0.U.asTypeOf(new SqPtr)) 556 sink.bits.uop.ftqPtr := source.bits.ftqIdx.getOrElse(0.U.asTypeOf(new FtqPtr)) 557 sink.bits.uop.ftqOffset := source.bits.ftqOffset.getOrElse(0.U) 558 sink.bits.uop.debugInfo := source.bits.perfDebugInfo 559 sink.bits.uop.vpu := source.bits.vpu.getOrElse(0.U.asTypeOf(new VPUCtrlSignals)) 560 sink.bits.uop.preDecodeInfo := source.bits.preDecode.getOrElse(0.U.asTypeOf(new PreDecodeInfo)) 561 } 562 io.mem.loadFastMatch := memScheduler.io.toMem.get.loadFastMatch.map(_.fastMatch) 563 io.mem.loadFastImm := memScheduler.io.toMem.get.loadFastMatch.map(_.fastImm) 564 io.mem.tlbCsr := csrio.tlb 565 io.mem.csrCtrl := csrio.customCtrl 566 io.mem.sfence := fenceio.sfence 567 io.mem.isStoreException := CommitType.lsInstIsStore(ctrlBlock.io.robio.exception.bits.commitType) 568 io.mem.isVlsException := ctrlBlock.io.robio.exception.bits.vls 569 require(io.mem.loadPcRead.size == params.LduCnt) 570 io.mem.loadPcRead.zipWithIndex.foreach { case (loadPcRead, i) => 571 loadPcRead := ctrlBlock.io.memLdPcRead(i).data 572 ctrlBlock.io.memLdPcRead(i).vld := io.mem.issueLda(i).valid 573 ctrlBlock.io.memLdPcRead(i).ptr := io.mem.issueLda(i).bits.uop.ftqPtr 574 ctrlBlock.io.memLdPcRead(i).offset := io.mem.issueLda(i).bits.uop.ftqOffset 575 } 576 577 io.mem.storePcRead.zipWithIndex.foreach { case (storePcRead, i) => 578 storePcRead := ctrlBlock.io.memStPcRead(i).data 579 ctrlBlock.io.memStPcRead(i).vld := io.mem.issueSta(i).valid 580 ctrlBlock.io.memStPcRead(i).ptr := io.mem.issueSta(i).bits.uop.ftqPtr 581 ctrlBlock.io.memStPcRead(i).offset := io.mem.issueSta(i).bits.uop.ftqOffset 582 } 583 584 io.mem.hyuPcRead.zipWithIndex.foreach( { case (hyuPcRead, i) => 585 hyuPcRead := ctrlBlock.io.memHyPcRead(i).data 586 ctrlBlock.io.memHyPcRead(i).vld := io.mem.issueHylda(i).valid 587 ctrlBlock.io.memHyPcRead(i).ptr := io.mem.issueHylda(i).bits.uop.ftqPtr 588 ctrlBlock.io.memHyPcRead(i).offset := io.mem.issueHylda(i).bits.uop.ftqOffset 589 }) 590 591 ctrlBlock.io.robio.robHeadLsIssue := io.mem.issueUops.map(deq => deq.fire && deq.bits.uop.robIdx === ctrlBlock.io.robio.robDeqPtr).reduce(_ || _) 592 593 // mem io 594 io.mem.lsqEnqIO <> memScheduler.io.memIO.get.lsqEnqIO 595 io.mem.robLsqIO <> ctrlBlock.io.robio.lsq 596 597 io.frontendSfence := fenceio.sfence 598 io.frontendTlbCsr := csrio.tlb 599 io.frontendCsrCtrl := csrio.customCtrl 600 601 io.tlb <> csrio.tlb 602 603 io.csrCustomCtrl := csrio.customCtrl 604 605 io.toTop.cpuHalted := false.B // TODO: implement cpu halt 606 607 io.debugTopDown.fromRob := ctrlBlock.io.debugTopDown.fromRob 608 ctrlBlock.io.debugTopDown.fromCore := io.debugTopDown.fromCore 609 610 io.debugRolling := ctrlBlock.io.debugRolling 611 612 if(backendParams.debugEn) { 613 dontTouch(memScheduler.io) 614 dontTouch(dataPath.io.toMemExu) 615 dontTouch(wbDataPath.io.fromMemExu) 616 } 617} 618 619class BackendMemIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 620 // Since fast load replay always use load unit 0, Backend flips two load port to avoid conflicts 621 val flippedLda = true 622 // params alias 623 private val LoadQueueSize = VirtualLoadQueueSize 624 // In/Out // Todo: split it into one-direction bundle 625 val lsqEnqIO = Flipped(new LsqEnqIO) 626 val robLsqIO = new RobLsqIO 627 val ldaIqFeedback = Vec(params.LduCnt, Flipped(new MemRSFeedbackIO)) 628 val staIqFeedback = Vec(params.StaCnt, Flipped(new MemRSFeedbackIO)) 629 val hyuIqFeedback = Vec(params.HyuCnt, Flipped(new MemRSFeedbackIO)) 630 val ldCancel = Vec(params.LdExuCnt, Flipped(new LoadCancelIO)) 631 val wakeup = Vec(params.LdExuCnt, Flipped(Valid(new DynInst))) 632 val loadPcRead = Vec(params.LduCnt, Output(UInt(VAddrBits.W))) 633 val storePcRead = Vec(params.StaCnt, Output(UInt(VAddrBits.W))) 634 val hyuPcRead = Vec(params.HyuCnt, Output(UInt(VAddrBits.W))) 635 // Input 636 val writebackLda = Vec(params.LduCnt, Flipped(DecoupledIO(new MemExuOutput))) 637 val writebackSta = Vec(params.StaCnt, Flipped(DecoupledIO(new MemExuOutput))) 638 val writebackStd = Vec(params.StdCnt, Flipped(DecoupledIO(new MemExuOutput))) 639 val writebackHyuLda = Vec(params.HyuCnt, Flipped(DecoupledIO(new MemExuOutput))) 640 val writebackHyuSta = Vec(params.HyuCnt, Flipped(DecoupledIO(new MemExuOutput))) 641 val writebackVldu = Vec(params.VlduCnt, Flipped(DecoupledIO(new MemExuOutput(true)))) 642 643 val s3_delayed_load_error = Input(Vec(LoadPipelineWidth, Bool())) 644 val stIn = Input(Vec(params.StaExuCnt, ValidIO(new DynInst()))) 645 val memoryViolation = Flipped(ValidIO(new Redirect)) 646 val exceptionAddr = Input(new Bundle { 647 val vaddr = UInt(VAddrBits.W) 648 val gpaddr = UInt(GPAddrBits.W) 649 }) 650 val sqDeq = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) 651 val lqDeq = Input(UInt(log2Up(CommitWidth + 1).W)) 652 val sqDeqPtr = Input(new SqPtr) 653 val lqDeqPtr = Input(new LqPtr) 654 655 val lqCancelCnt = Input(UInt(log2Up(VirtualLoadQueueSize + 1).W)) 656 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 657 658 val lqCanAccept = Input(Bool()) 659 val sqCanAccept = Input(Bool()) 660 661 val otherFastWakeup = Flipped(Vec(params.LduCnt + params.HyuCnt, ValidIO(new DynInst))) 662 val stIssuePtr = Input(new SqPtr()) 663 664 val csrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 665 666 val debugLS = Flipped(Output(new DebugLSIO)) 667 668 val lsTopdownInfo = Vec(params.LduCnt + params.HyuCnt, Flipped(Output(new LsTopdownInfo))) 669 // Output 670 val redirect = ValidIO(new Redirect) // rob flush MemBlock 671 val issueLda = MixedVec(Seq.fill(params.LduCnt)(DecoupledIO(new MemExuInput()))) 672 val issueSta = MixedVec(Seq.fill(params.StaCnt)(DecoupledIO(new MemExuInput()))) 673 val issueStd = MixedVec(Seq.fill(params.StdCnt)(DecoupledIO(new MemExuInput()))) 674 val issueHylda = MixedVec(Seq.fill(params.HyuCnt)(DecoupledIO(new MemExuInput()))) 675 val issueHysta = MixedVec(Seq.fill(params.HyuCnt)(DecoupledIO(new MemExuInput()))) 676 val issueVldu = MixedVec(Seq.fill(params.VlduCnt)(DecoupledIO(new MemExuInput(true)))) 677 678 val loadFastMatch = Vec(params.LduCnt, Output(UInt(params.LduCnt.W))) 679 val loadFastImm = Vec(params.LduCnt, Output(UInt(12.W))) // Imm_I 680 681 val tlbCsr = Output(new TlbCsrBundle) 682 val csrCtrl = Output(new CustomCSRCtrlIO) 683 val sfence = Output(new SfenceBundle) 684 val isStoreException = Output(Bool()) 685 val isVlsException = Output(Bool()) 686 687 // ATTENTION: The issue ports' sequence order should be the same as IQs' deq config 688 private [backend] def issueUops: Seq[DecoupledIO[MemExuInput]] = { 689 issueSta ++ 690 issueHylda ++ issueHysta ++ 691 issueLda ++ 692 issueVldu ++ 693 issueStd 694 }.toSeq 695 696 // ATTENTION: The writeback ports' sequence order should be the same as IQs' deq config 697 private [backend] def writeBack: Seq[DecoupledIO[MemExuOutput]] = { 698 writebackSta ++ 699 writebackHyuLda ++ writebackHyuSta ++ 700 writebackLda ++ 701 writebackVldu ++ 702 writebackStd 703 } 704} 705 706class BackendIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 707 val fromTop = new Bundle { 708 val hartId = Input(UInt(hartIdLen.W)) 709 val externalInterrupt = new ExternalInterruptIO 710 } 711 712 val toTop = new Bundle { 713 val cpuHalted = Output(Bool()) 714 } 715 716 val fenceio = new FenceIO 717 // Todo: merge these bundles into BackendFrontendIO 718 val frontend = Flipped(new FrontendToCtrlIO) 719 val frontendSfence = Output(new SfenceBundle) 720 val frontendCsrCtrl = Output(new CustomCSRCtrlIO) 721 val frontendTlbCsr = Output(new TlbCsrBundle) 722 // distributed csr write 723 val frontendCsrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 724 725 val mem = new BackendMemIO 726 727 val perf = Input(new PerfCounterIO) 728 729 val tlb = Output(new TlbCsrBundle) 730 731 val csrCustomCtrl = Output(new CustomCSRCtrlIO) 732 733 val debugTopDown = new Bundle { 734 val fromRob = new RobCoreTopDownIO 735 val fromCore = new CoreDispatchTopDownIO 736 } 737 val debugRolling = new RobDebugRollingIO 738} 739