1package xiangshan.backend 2 3import bus.simplebus.SimpleBusUC 4import chisel3._ 5import chisel3.util._ 6import chisel3.util.experimental.BoringUtils 7import noop.MemMMUIO 8import xiangshan._ 9import xiangshan.backend.decode.{DecodeBuffer, DecodeStage} 10import xiangshan.backend.rename.Rename 11import xiangshan.backend.brq.Brq 12import xiangshan.backend.dispatch.Dispatch 13import xiangshan.backend.exu._ 14import xiangshan.backend.fu.FunctionUnit 15import xiangshan.backend.issue.{IssueQueue, ReservationStation} 16import xiangshan.backend.regfile.{Regfile, RfWritePort} 17import xiangshan.backend.roq.Roq 18import xiangshan.mem._ 19import utils.ParallelOR 20 21/** Backend Pipeline: 22 * Decode -> Rename -> Dispatch-1 -> Dispatch-2 -> Issue -> Exe 23 */ 24class Backend extends XSModule 25 with NeedImpl { 26 val io = IO(new Bundle { 27 val frontend = Flipped(new FrontendToBackendIO) 28 val mem = Flipped(new MemToBackendIO) 29 }) 30 31 32 val aluExeUnits =Array.tabulate(exuParameters.AluCnt)(_ => Module(new AluExeUnit)) 33 val jmpExeUnit = Module(new JmpExeUnit) 34 val mulExeUnits = Array.tabulate(exuParameters.MulCnt)(_ => Module(new MulExeUnit)) 35 val mduFenceExeUnit = Array.tabulate(1)(_ => Module(new MulDivFenceExeUnit)) // MulDivExeFenceUnit 36 val mduExeUnits = Array.tabulate(exuParameters.MduCnt-1)(_ => Module(new MulDivExeUnit)) 37 // val fmacExeUnits = Array.tabulate(exuParameters.FmacCnt)(_ => Module(new Fmac)) 38 // val fmiscExeUnits = Array.tabulate(exuParameters.FmiscCnt)(_ => Module(new Fmisc)) 39 // val fmiscDivSqrtExeUnits = Array.tabulate(exuParameters.FmiscDivSqrtCnt)(_ => Module(new FmiscDivSqrt)) 40 val exeUnits = jmpExeUnit +: (aluExeUnits ++ mulExeUnits ++ mduFenceExeUnit ++ mduExeUnits) 41 exeUnits.foreach(_.io.exception := DontCare) 42 exeUnits.foreach(_.io.dmem := DontCare) 43 exeUnits.foreach(_.io.mcommit := DontCare) 44 45 val decode = Module(new DecodeStage) 46 val brq = Module(new Brq) 47 val decBuf = Module(new DecodeBuffer) 48 val rename = Module(new Rename) 49 val dispatch = Module(new Dispatch) 50 val roq = Module(new Roq) 51 val intRf = Module(new Regfile( 52 numReadPorts = NRIntReadPorts, 53 numWirtePorts = NRIntWritePorts, 54 hasZero = true 55 )) 56 val fpRf = Module(new Regfile( 57 numReadPorts = NRFpReadPorts, 58 numWirtePorts = NRFpWritePorts, 59 hasZero = false 60 )) 61 val memRf = Module(new Regfile( 62 numReadPorts = 2*exuParameters.StuCnt + exuParameters.LduCnt, 63 numWirtePorts = NRIntWritePorts, 64 hasZero = true, 65 isMemRf = true 66 )) 67 68 // backend redirect, flush pipeline 69 val redirect = Mux( 70 roq.io.redirect.valid, 71 roq.io.redirect, 72 Mux( 73 brq.io.redirect.valid, 74 brq.io.redirect, 75 io.mem.replayAll 76 ) 77 ) 78 79 io.frontend.redirect := redirect 80 io.frontend.redirect.valid := redirect.valid && !redirect.bits.isReplay 81 82 val memConfigs = 83 Seq.fill(exuParameters.LduCnt)(Exu.ldExeUnitCfg) ++ 84 Seq.fill(exuParameters.StuCnt)(Exu.stExeUnitCfg) 85 86 val exuConfigs = exeUnits.map(_.config) ++ memConfigs 87 88 val exeWbReqs = exeUnits.map(_.io.out) ++ io.mem.ldout ++ io.mem.stout 89 90 def needWakeup(cfg: ExuConfig): Boolean = 91 (cfg.readIntRf && cfg.writeIntRf) || (cfg.readFpRf && cfg.writeFpRf) 92 93 def needData(a: ExuConfig, b: ExuConfig): Boolean = 94 (a.readIntRf && b.writeIntRf) || (a.readFpRf && b.writeFpRf) 95 96 val reservedStations = exeUnits. 97 zipWithIndex. 98 map({ case (exu, i) => 99 100 val cfg = exu.config 101 102 val wakeUpDateVec = exuConfigs.zip(exeWbReqs).filter(x => needData(cfg, x._1)).map(_._2) 103 val bypassCnt = exuConfigs.count(c => c.enableBypass && needData(cfg, c)) 104 105 println(s"exu:${cfg.name} wakeupCnt:${wakeUpDateVec.length} bypassCnt:$bypassCnt") 106 107 val rs = Module(new ReservationStation( 108 cfg, wakeUpDateVec.length, bypassCnt, cfg.enableBypass, false 109 )) 110 rs.io.redirect <> redirect 111 rs.io.numExist <> dispatch.io.numExist(i) 112 rs.io.enqCtrl <> dispatch.io.enqIQCtrl(i) 113 rs.io.enqData <> dispatch.io.enqIQData(i) 114 for( 115 (wakeUpPort, exuOut) <- 116 rs.io.wakeUpPorts.zip(wakeUpDateVec) 117 ){ 118 wakeUpPort.bits := exuOut.bits 119 wakeUpPort.valid := exuOut.valid 120 } 121 122 exu.io.in <> rs.io.deq 123 exu.io.redirect <> redirect 124 rs 125 }) 126 127 for( rs <- reservedStations){ 128 rs.io.bypassUops <> reservedStations. 129 filter(x => x.enableBypass && needData(rs.exuCfg, x.exuCfg)). 130 map(_.io.selectedUop) 131 132 val bypassDataVec = exuConfigs.zip(exeWbReqs). 133 filter(x => x._1.enableBypass && needData(rs.exuCfg, x._1)).map(_._2) 134 135 for(i <- bypassDataVec.indices){ 136 rs.io.bypassData(i).valid := bypassDataVec(i).valid 137 rs.io.bypassData(i).bits := bypassDataVec(i).bits 138 } 139 } 140 141 val issueQueues = exuConfigs. 142 zipWithIndex. 143 takeRight(exuParameters.LduCnt + exuParameters.StuCnt). 144 map({case (cfg, i) => 145 val wakeUpDateVec = exuConfigs.zip(exeWbReqs).filter(x => needData(cfg, x._1)).map(_._2) 146 val bypassUopVec = reservedStations. 147 filter(r => r.exuCfg.enableBypass && needData(cfg, r.exuCfg)).map(_.io.selectedUop) 148 val bypassDataVec = exuConfigs.zip(exeWbReqs). 149 filter(x => x._1.enableBypass && needData(cfg, x._1)).map(_._2) 150 151 val iq = Module(new IssueQueue( 152 cfg, wakeUpDateVec.length, bypassUopVec.length 153 )) 154 println(s"exu:${cfg.name} wakeupCnt:${wakeUpDateVec.length} bypassCnt:${bypassUopVec.length}") 155 iq.io.redirect <> redirect 156 iq.io.tlbFeedback := io.mem.tlbFeedback(i - exuParameters.ExuCnt + exuParameters.LduCnt + exuParameters.StuCnt) 157 iq.io.enq <> dispatch.io.enqIQCtrl(i) 158 dispatch.io.numExist(i) := iq.io.numExist 159 for( 160 (wakeUpPort, exuOut) <- 161 iq.io.wakeUpPorts.zip(wakeUpDateVec) 162 ){ 163 wakeUpPort.bits := exuOut.bits 164 wakeUpPort.valid := exuOut.fire() // data after arbit 165 } 166 iq.io.bypassUops <> bypassUopVec 167 for(i <- bypassDataVec.indices){ 168 iq.io.bypassData(i).valid := bypassDataVec(i).valid 169 iq.io.bypassData(i).bits := bypassDataVec(i).bits 170 } 171 iq 172 }) 173 174 io.mem.commits <> roq.io.commits 175 io.mem.ldin <> issueQueues.filter(_.exuCfg == Exu.ldExeUnitCfg).map(_.io.deq) 176 io.mem.stin <> issueQueues.filter(_.exuCfg == Exu.stExeUnitCfg).map(_.io.deq) 177 jmpExeUnit.io.exception.valid := roq.io.redirect.valid && roq.io.redirect.bits.isException 178 jmpExeUnit.io.exception.bits := roq.io.exception 179 180 io.frontend.outOfOrderBrInfo <> brq.io.outOfOrderBrInfo 181 io.frontend.inOrderBrInfo <> brq.io.inOrderBrInfo 182 183 decode.io.in <> io.frontend.cfVec 184 brq.io.roqRedirect <> roq.io.redirect 185 brq.io.memRedirect <> io.mem.replayAll 186 brq.io.bcommit := roq.io.bcommit 187 brq.io.enqReqs <> decode.io.toBrq 188 for ((x, y) <- brq.io.exuRedirect.zip(exeUnits.filter(_.config.hasRedirect))) { 189 x.bits := y.io.out.bits 190 x.valid := y.io.out.fire() && y.io.out.bits.redirectValid 191 } 192 decode.io.brTags <> brq.io.brTags 193 decBuf.io.isWalking := ParallelOR(roq.io.commits.map(c => c.valid && c.bits.isWalk)) // TODO: opt this 194 decBuf.io.redirect <> redirect 195 decBuf.io.in <> decode.io.out 196 197 rename.io.redirect <> redirect 198 rename.io.roqCommits <> roq.io.commits 199 rename.io.in <> decBuf.io.out 200 rename.io.intRfReadAddr <> dispatch.io.readIntRf.map(_.addr) ++ dispatch.io.intMemRegAddr 201 rename.io.intPregRdy <> dispatch.io.intPregRdy ++ dispatch.io.intMemRegRdy 202 rename.io.fpRfReadAddr <> dispatch.io.readFpRf.map(_.addr) ++ dispatch.io.fpMemRegAddr 203 rename.io.fpPregRdy <> dispatch.io.fpPregRdy ++ dispatch.io.fpMemRegRdy 204 rename.io.replayPregReq <> dispatch.io.replayPregReq 205 dispatch.io.redirect <> redirect 206 dispatch.io.fromRename <> rename.io.out 207 208 roq.io.memRedirect <> io.mem.replayAll 209 roq.io.brqRedirect <> brq.io.redirect 210 roq.io.dp1Req <> dispatch.io.toRoq 211 dispatch.io.roqIdxs <> roq.io.roqIdxs 212 io.mem.dp1Req <> dispatch.io.toLsroq 213 dispatch.io.lsroqIdxs <> io.mem.lsroqIdxs 214 dispatch.io.commits <> roq.io.commits 215 216 intRf.io.readPorts <> dispatch.io.readIntRf 217 fpRf.io.readPorts <> dispatch.io.readFpRf ++ issueQueues.flatMap(_.io.readFpRf) 218 memRf.io.readPorts <> issueQueues.flatMap(_.io.readIntRf) 219 220 io.mem.redirect <> redirect 221 222 val wbu = Module(new Wbu(exuConfigs)) 223 wbu.io.in <> exeWbReqs 224 225 val wbIntResults = wbu.io.toIntRf 226 val wbFpResults = wbu.io.toFpRf 227 228 def exuOutToRfWrite(x: Valid[ExuOutput]): RfWritePort = { 229 val rfWrite = Wire(new RfWritePort) 230 rfWrite.wen := x.valid 231 rfWrite.addr := x.bits.uop.pdest 232 rfWrite.data := x.bits.data 233 rfWrite 234 } 235 val intRfWrite = wbIntResults.map(exuOutToRfWrite) 236 intRf.io.writePorts <> intRfWrite 237 memRf.io.writePorts <> intRfWrite 238 fpRf.io.writePorts <> wbFpResults.map(exuOutToRfWrite) 239 240 rename.io.wbIntResults <> wbIntResults 241 rename.io.wbFpResults <> wbFpResults 242 243 roq.io.exeWbResults.take(exeWbReqs.length).zip(wbu.io.toRoq).foreach(x => x._1 := x._2) 244 roq.io.exeWbResults.last := brq.io.out 245 246 247 // TODO: Remove sink and source 248 val tmp = WireInit(0.U) 249 val sinks = Array[String]( 250 "DTLBFINISH", 251 "DTLBPF", 252 "DTLBENABLE", 253 "perfCntCondMdcacheLoss", 254 "perfCntCondMl2cacheLoss", 255 "perfCntCondMdcacheHit", 256 "lsuMMIO", 257 "perfCntCondMl2cacheHit", 258 "perfCntCondMl2cacheReq", 259 "mtip", 260 "perfCntCondMdcacheReq", 261 "meip" 262 ) 263 for (s <- sinks) { 264 BoringUtils.addSink(tmp, s) 265 } 266 267 val debugIntReg, debugFpReg = WireInit(VecInit(Seq.fill(32)(0.U(XLEN.W)))) 268 BoringUtils.addSink(debugIntReg, "DEBUG_INT_ARCH_REG") 269 BoringUtils.addSink(debugFpReg, "DEBUG_FP_ARCH_REG") 270 val debugArchReg = WireInit(VecInit(debugIntReg ++ debugFpReg)) 271 if (!env.FPGAPlatform) { 272 BoringUtils.addSource(debugArchReg, "difftestRegs") 273 } 274 275} 276