1package xiangshan.backend 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import utility.{PipelineConnect, ZeroExt} 8import xiangshan._ 9import xiangshan.backend.Bundles.{DynInst, MemExuInput, MemExuOutput} 10import xiangshan.backend.ctrlblock.CtrlBlock 11import xiangshan.backend.datapath.WbConfig._ 12import xiangshan.backend.datapath.{DataPath, NewPipelineConnect, WbDataPath} 13import xiangshan.backend.exu.ExuBlock 14import xiangshan.backend.fu.vector.Bundles.{VConfig, VType} 15import xiangshan.backend.fu.{FenceIO, FenceToSbuffer, PerfCounterIO, FuConfig} 16import xiangshan.backend.issue.{Scheduler, IntScheduler, MemScheduler, VfScheduler} 17import xiangshan.backend.rob.RobLsqIO 18import xiangshan.frontend.{FtqPtr, FtqRead} 19import xiangshan.mem.{LqPtr, LsqEnqIO, SqPtr} 20 21class Backend(val params: BackendParams)(implicit p: Parameters) extends LazyModule 22 with HasXSParameter { 23 24 for (exuCfg <- params.allExuParams) { 25 val fuConfigs = exuCfg.fuConfigs 26 val wbPortConfigs = exuCfg.wbPortConfigs 27 val immType = exuCfg.immType 28 println(s"exu: ${fuConfigs.map(_.name)}, wb: ${wbPortConfigs}, imm: ${immType}") 29 require(wbPortConfigs.collectFirst { case x: IntWB => x }.nonEmpty == 30 fuConfigs.map(_.writeIntRf).reduce(_ || _), 31 "int wb port has no priority" ) 32 require(wbPortConfigs.collectFirst { case x: VfWB => x }.nonEmpty == 33 fuConfigs.map(x => x.writeFpRf || x.writeVecRf).reduce(_ || _), 34 "vec wb port has no priority" ) 35 } 36 37 println(s"Function Unit: Alu(${params.AluCnt}), Brh(${params.BrhCnt}), Jmp(${params.JmpCnt}), " + 38 s"Ldu(${params.LduCnt}), Sta(${params.StaCnt}), Std(${params.StdCnt})") 39 40 for (cfg <- FuConfig.allConfigs) { 41 println(s"[Backend] $cfg") 42 } 43 44 val ctrlBlock = LazyModule(new CtrlBlock(params)) 45 val intScheduler = params.intSchdParams.map(x => LazyModule(new Scheduler(x))) 46 val vfScheduler = params.vfSchdParams.map(x => LazyModule(new Scheduler(x))) 47 val memScheduler = params.memSchdParams.map(x => LazyModule(new Scheduler(x))) 48 val dataPath = LazyModule(new DataPath(params)) 49 val intExuBlock = params.intSchdParams.map(x => LazyModule(new ExuBlock(x))) 50 val vfExuBlock = params.vfSchdParams.map(x => LazyModule(new ExuBlock(x))) 51 52 lazy val module = new BackendImp(this) 53} 54 55class BackendImp(override val wrapper: Backend)(implicit p: Parameters) extends LazyModuleImp(wrapper) 56 with HasXSParameter{ 57 implicit private val params = wrapper.params 58 val io = IO(new BackendIO()(p, wrapper.params)) 59 60 private val ctrlBlock = wrapper.ctrlBlock.module 61 private val intScheduler = wrapper.intScheduler.get.module 62 private val vfScheduler = wrapper.vfScheduler.get.module 63 private val memScheduler = wrapper.memScheduler.get.module 64 private val dataPath = wrapper.dataPath.module 65 private val intExuBlock = wrapper.intExuBlock.get.module 66 private val vfExuBlock = wrapper.vfExuBlock.get.module 67 private val wbDataPath = Module(new WbDataPath(params)) 68 69 private val (intRespWrite, vfRespWrite, memRespWrite) = (intScheduler.io.toWbFuBusyTable.intFuBusyTableWrite, 70 vfScheduler.io.toWbFuBusyTable.intFuBusyTableWrite, 71 memScheduler.io.toWbFuBusyTable.intFuBusyTableWrite) 72 private val (intRespRead, vfRespRead, memRespRead) = (intScheduler.io.fromWbFuBusyTable.fuBusyTableRead, 73 vfScheduler.io.fromWbFuBusyTable.fuBusyTableRead, 74 memScheduler.io.fromWbFuBusyTable.fuBusyTableRead) 75 private val intAllRespWrite = (intRespWrite ++ vfRespWrite ++ memRespWrite).flatten 76 private val intAllRespRead = (intRespRead ++ vfRespRead ++ memRespRead).flatten.map(_.intWbBusyTable) 77 private val intAllWbConflictFlag = dataPath.io.wbConfictRead.flatten.flatten.map(_.intConflict) 78 79 private val (vfIntRespWrite, vfVfRespWrite, vfMemRespWrite) = (intScheduler.io.toWbFuBusyTable.vfFuBusyTableWrite, 80 vfScheduler.io.toWbFuBusyTable.vfFuBusyTableWrite, 81 memScheduler.io.toWbFuBusyTable.vfFuBusyTableWrite) 82 83 private val vfAllRespWrite = (vfIntRespWrite ++ vfVfRespWrite ++ vfMemRespWrite).flatten 84 private val vfAllRespRead = (intRespRead ++ vfRespRead ++ memRespRead).flatten.map(_.vfWbBusyTable) 85 private val vfAllWbConflictFlag = dataPath.io.wbConfictRead.flatten.flatten.map(_.vfConflict) 86 87 wbDataPath.io.fromIntExu.flatten.filter(x => x.bits.params.writeIntRf) 88 private val allExuParams = params.allExuParams 89 private val intRespWriteWithParams = intAllRespWrite.zip(allExuParams) 90 println(s"[intRespWriteWithParams] is ${intRespWriteWithParams}") 91 intRespWriteWithParams.foreach{ case(l,r) => 92 println(s"FuBusyTableWriteBundle is ${l}, ExeUnitParams is ${r}") 93 } 94 private val vfRespWriteWithParams = vfAllRespWrite.zip(allExuParams) 95 96 private val intWBAllFuGroup = params.getIntWBExeGroup.map{ case(groupId, exeUnit) => (groupId, exeUnit.flatMap(_.fuConfigs)) } 97 private val intWBFuGroup = params.getIntWBExeGroup.map{ case(groupId, exeUnit) => (groupId, exeUnit.flatMap(_.fuConfigs).filter(_.writeIntRf)) } 98 private val intLatencyCertains = intWBAllFuGroup.map{case (k,v) => (k, v.map(_.latency.latencyVal.nonEmpty).reduce(_ && _))} 99 private val intWBFuLatencyMap = intLatencyCertains.map{case (k, latencyCertain) => 100 if (latencyCertain) Some(intWBFuGroup(k).map(y => (y.fuType, y.latency.latencyVal.get))) 101 else None 102 }.toSeq 103 private val intWBFuLatencyValMax = intWBFuLatencyMap.map(latencyMap=> latencyMap.map(x => x.map(_._2).max)) 104 105 private val vfWBAllFuGroup = params.getVfWBExeGroup.map{ case(groupId, exeUnit) => (groupId, exeUnit.flatMap(_.fuConfigs)) } 106 private val vfWBFuGroup = params.getVfWBExeGroup.map{ case(groupId, exeUnit) => (groupId, exeUnit.flatMap(_.fuConfigs).filter(x => x.writeFpRf || x.writeVecRf)) } 107 private val vfLatencyCertains = vfWBAllFuGroup.map{case (k,v) => (k, v.map(_.latency.latencyVal.nonEmpty).reduce(_ && _))} 108 val vfWBFuLatencyMap = vfLatencyCertains.map { case (k, latencyCertain) => 109 if (latencyCertain) Some(vfWBFuGroup(k).map(y => (y.fuType, y.latency.latencyVal.get))) 110 else None 111 }.toSeq 112 private val vfWBFuLatencyValMax = vfWBFuLatencyMap.map(latencyMap => latencyMap.map(x => x.map(_._2).max)) 113 114 private val intWBFuBusyTable = intWBFuLatencyValMax.map { case y => if (y.getOrElse(0)>0) Some(Reg(UInt(y.getOrElse(1).W))) else None } 115 println(s"[intWBFuBusyTable] is ${intWBFuBusyTable.map(x => x) }") 116 private val vfWBFuBusyTable = vfWBFuLatencyValMax.map { case y => if (y.getOrElse(0)>0) Some(Reg(UInt(y.getOrElse(1).W))) else None } 117 println(s"[vfWBFuBusyTable] is ${vfWBFuBusyTable.map(x => x) }") 118 119 private val intWBPortConflictFlag = intWBFuLatencyValMax.map { case y => if (y.getOrElse(0) > 0) Some(Reg(Bool())) else None } 120 private val vfWBPortConflictFlag = vfWBFuLatencyValMax.map { case y => if (y.getOrElse(0) > 0) Some(Reg(Bool())) else None } 121 122 intWBPortConflictFlag.foreach(x => if(x.isDefined) dontTouch((x.get))) 123 vfWBPortConflictFlag.foreach(x => if(x.isDefined) dontTouch((x.get))) 124 125 126 intWBFuBusyTable.map(x => x.map(dontTouch(_))) 127 vfWBFuBusyTable.map(x => x.map(dontTouch(_))) 128 129 130 private val intWBFuBusyTableWithPort = intWBFuBusyTable.zip(intWBFuGroup.map(_._1)) 131 private val intWBPortConflictFlagWithPort = intWBPortConflictFlag.zip(intWBFuGroup.map(_._1)) 132 // intWBFuBusyTable write 133 intWBFuBusyTableWithPort.zip(intWBPortConflictFlag).zip(intWBFuLatencyValMax).foreach { 134 case (((busyTable, wbPort), wbPortConflictFlag), maxLatency) => 135 if (busyTable.nonEmpty) { 136 val maskWidth = maxLatency.getOrElse(0) 137 val defaultMask = ((1 << maskWidth) - 1).U 138 val deqWbFuBusyTableValue = intRespWriteWithParams.zipWithIndex.filter { case ((r, p), idx) => 139 (p.wbPortConfigs.collectFirst{ case x: IntWB => x.port }.getOrElse(-1)) == wbPort 140 }.map{case ((r, p), idx) => 141 val resps = Seq(r.deqResp, r.og0Resp, r.og1Resp) 142 Mux(resps(0).valid && resps(0).bits.respType === RSFeedbackType.issueSuccess, 143 VecInit((0 until maxLatency.getOrElse(0) + 1).map { case latency => 144 val latencyNumFuType = p.writeIntFuConfigs.filter(_.latency.latencyVal.getOrElse(-1) == latency).map(_.fuType) 145 val isLatencyNum = Cat(latencyNumFuType.map(futype => resps(0).bits.fuType === futype.U)).asUInt().orR() // The latency of the deqResp inst is Num 146 isLatencyNum 147 }).asUInt, 148 0.U) 149 } 150// deqWbFuBusyTableValue.foreach(x => dontTouch(x)) 151 val deqIsLatencyNumMask = (deqWbFuBusyTableValue.reduce(_ | _) >> 1).asUInt 152 wbPortConflictFlag.get := deqWbFuBusyTableValue.reduce(_ & _).orR 153 154 val og0IsLatencyNumMask = WireInit(defaultMask) 155 og0IsLatencyNumMask := intRespWriteWithParams.zipWithIndex.map { case ((r, p), idx) => 156 val resps = Seq(r.deqResp, r.og0Resp, r.og1Resp) 157 val matchI = (p.wbPortConfigs.collectFirst { case x: IntWB => x.port }.getOrElse(-1)) == wbPort 158 if (matchI) { 159 Mux(resps(1).valid && resps(1).bits.respType === RSFeedbackType.rfArbitFail, 160 (~(Cat(VecInit((0 until maxLatency.getOrElse(0)).map { case num => 161 val latencyNumFuType = p.writeIntFuConfigs.filter(_.latency.latencyVal.getOrElse(-1) == num + 1).map(_.fuType) 162 val isLatencyNum = Cat(latencyNumFuType.map(futype => resps(1).bits.fuType === futype.U)).asUInt().orR() // The latency of the deqResp inst is Num 163 isLatencyNum 164 }).asUInt, 0.U(1.W)))).asUInt, 165 defaultMask) 166 } else defaultMask 167 }.reduce(_&_) 168 val og1IsLatencyNumMask = WireInit(defaultMask) 169 og1IsLatencyNumMask := intRespWriteWithParams.zipWithIndex.map { case ((r, p), idx) => 170 val resps = Seq(r.deqResp, r.og0Resp, r.og1Resp) 171 val matchI = (p.wbPortConfigs.collectFirst { case x: IntWB => x.port }.getOrElse(-1)) == wbPort 172 if (matchI && resps.length==3) { 173 Mux(resps(2).valid && resps(2).bits.respType === RSFeedbackType.fuBusy, 174 (~(Cat(VecInit((0 until maxLatency.getOrElse(0)).map { case num => 175 val latencyNumFuType = p.writeIntFuConfigs.filter(_.latency.latencyVal.getOrElse(-1) == num + 1).map(_.fuType) 176 val isLatencyNum = Cat(latencyNumFuType.map(futype => resps(2).bits.fuType === futype.U)).asUInt().orR() // The latency of the deqResp inst is Num 177 isLatencyNum 178 }).asUInt, 0.U(2.W)))).asUInt, 179 defaultMask) 180 } else defaultMask 181 }.reduce(_ & _) 182 dontTouch(deqIsLatencyNumMask) 183 dontTouch(og0IsLatencyNumMask) 184 dontTouch(og1IsLatencyNumMask) 185 busyTable.get := ((busyTable.get >> 1.U).asUInt() | deqIsLatencyNumMask) & og0IsLatencyNumMask.asUInt() & og1IsLatencyNumMask.asUInt() 186 } 187 } 188 // intWBFuBusyTable read 189 for(i <- 0 until intAllRespRead.size){ 190 if(intAllRespRead(i).isDefined){ 191 intAllRespRead(i).get := intWBFuBusyTableWithPort.map { case (busyTable, wbPort) => 192 val matchI = (allExuParams(i).wbPortConfigs.collectFirst { case x: IntWB => x.port }.getOrElse(-1)) == wbPort 193 if (busyTable.nonEmpty && matchI) { 194 busyTable.get.asTypeOf(intAllRespRead(i).get) 195 } else { 196 0.U.asTypeOf(intAllRespRead(i).get) 197 } 198 }.reduce(_ | _) 199 } 200 201 if (intAllWbConflictFlag(i).isDefined) { 202 intAllWbConflictFlag(i).get := intWBPortConflictFlagWithPort.map { case (conflictFlag, wbPort) => 203 val matchI = (allExuParams(i).wbPortConfigs.collectFirst { case x: IntWB => x.port }.getOrElse(-1)) == wbPort 204 if (conflictFlag.nonEmpty && matchI) { 205 conflictFlag.get 206 } else false.B 207 }.reduce(_ | _) 208 } 209 } 210 211 private val vfWBFuBusyTableWithPort = vfWBFuBusyTable.zip(vfWBFuGroup.map(_._1)) 212 private val vfWBPortConflictFlagWithPort = vfWBPortConflictFlag.zip(vfWBFuGroup.map(_._1)) 213 // vfWBFuBusyTable write 214 vfWBFuBusyTableWithPort.zip(vfWBPortConflictFlag).zip(vfWBFuLatencyValMax).foreach{ 215 case(((busyTable, wbPort), wbPortConflictFlag), maxLatency) => 216 if(busyTable.nonEmpty){ 217 val maskWidth = maxLatency.getOrElse(0) 218 val defaultMask = ((1 << maskWidth) - 1).U 219 val deqWbFuBusyTableValue = vfRespWriteWithParams.zipWithIndex.filter { case ((_, p), _) => 220 (p.wbPortConfigs.collectFirst { case x: VfWB => x.port }.getOrElse(-1)) == wbPort 221 }.map { case ((r, p), _) => 222 val resps = Seq(r.deqResp, r.og0Resp, r.og1Resp) 223 Mux(resps(0).valid && resps(0).bits.respType === RSFeedbackType.issueSuccess, 224 VecInit((0 until maxLatency.getOrElse(0) + 1).map { case latency => 225 val latencyNumFuType = p.writeVfFuConfigs.filter(_.latency.latencyVal.getOrElse(-1) == latency).map(_.fuType) 226 val isLatencyNum = Cat(latencyNumFuType.map(futype => resps(0).bits.fuType === futype.U)).asUInt.orR // The latency of the deqResp inst is Num 227 isLatencyNum 228 }).asUInt, 229 0.U) 230 } 231 val deqIsLatencyNumMask = (deqWbFuBusyTableValue.reduce(_ | _) >> 1).asUInt 232 wbPortConflictFlag.get := deqWbFuBusyTableValue.reduce(_ & _).orR 233 234 val og0IsLatencyNumMask = WireInit(defaultMask) 235 og0IsLatencyNumMask := vfRespWriteWithParams.zipWithIndex.map { case ((r, p), idx) => 236 val resps = Seq(r.deqResp, r.og0Resp, r.og1Resp) 237 val matchI = (p.wbPortConfigs.collectFirst { case x: VfWB => x.port }.getOrElse(-1)) == wbPort 238 if (matchI) { 239 Mux(resps(1).valid && resps(1).bits.respType === RSFeedbackType.rfArbitFail, 240 (~(Cat(VecInit((0 until maxLatency.getOrElse(0)).map { case num => 241 val latencyNumFuType = p.writeVfFuConfigs.filter(_.latency.latencyVal.getOrElse(-1) == num + 1).map(_.fuType) 242 val isLatencyNum = Cat(latencyNumFuType.map(futype => resps(1).bits.fuType === futype.U)).asUInt.orR // The latency of the deqResp inst is Num 243 isLatencyNum 244 }).asUInt, 0.U(1.W)))).asUInt, 245 defaultMask) 246 } else defaultMask 247 }.reduce(_ & _) 248 val og1IsLatencyNumMask = WireInit(defaultMask) 249 og1IsLatencyNumMask := vfRespWriteWithParams.zipWithIndex.map { case ((r, p), idx) => 250 val resps = Seq(r.deqResp, r.og0Resp, r.og1Resp) 251 252 val matchI = (p.wbPortConfigs.collectFirst { case x: VfWB => x.port }.getOrElse(-1)) == wbPort 253 if (matchI && resps.length == 3) { 254 Mux(resps(2).valid && resps(2).bits.respType === RSFeedbackType.fuBusy, 255 (~(Cat(VecInit((0 until maxLatency.getOrElse(0)).map { case num => 256 val latencyNumFuType = p.writeVfFuConfigs.filter(_.latency.latencyVal.getOrElse(-1) == num + 1).map(_.fuType) 257 val isLatencyNum = Cat(latencyNumFuType.map(futype => resps(2).bits.fuType === futype.U)).asUInt.orR // The latency of the deqResp inst is Num 258 isLatencyNum 259 }).asUInt, 0.U(2.W)))).asUInt, 260 defaultMask) 261 } else defaultMask 262 }.reduce(_ & _) 263 dontTouch(deqIsLatencyNumMask) 264 dontTouch(og0IsLatencyNumMask) 265 dontTouch(og1IsLatencyNumMask) 266 busyTable.get := ((busyTable.get >> 1.U).asUInt | deqIsLatencyNumMask) & og0IsLatencyNumMask.asUInt & og1IsLatencyNumMask.asUInt 267 } 268 } 269 270 // vfWBFuBusyTable read 271 for (i <- 0 until vfAllRespRead.size) { 272 if(vfAllRespRead(i).isDefined){ 273 vfAllRespRead(i).get := vfWBFuBusyTableWithPort.map { case (busyTable, wbPort) => 274 val matchI = (allExuParams(i).wbPortConfigs.collectFirst { case x: VfWB => x.port }.getOrElse(-1)) == wbPort 275 if (busyTable.nonEmpty && matchI) { 276 busyTable.get.asTypeOf(vfAllRespRead(i).get) 277 } else { 278 0.U.asTypeOf(vfAllRespRead(i).get) 279 } 280 }.reduce(_ | _) 281 } 282 283 if(vfAllWbConflictFlag(i).isDefined){ 284 vfAllWbConflictFlag(i).get := vfWBPortConflictFlagWithPort.map { case (conflictFlag, wbPort) => 285 val matchI = (allExuParams(i).wbPortConfigs.collectFirst { case x: VfWB => x.port }.getOrElse(-1)) == wbPort 286 if (conflictFlag.nonEmpty && matchI) { 287 conflictFlag.get 288 } else false.B 289 }.reduce(_ | _) 290 } 291 } 292 293 ctrlBlock.io.fromTop.hartId := io.fromTop.hartId 294 ctrlBlock.io.frontend <> io.frontend 295 ctrlBlock.io.fromWB.wbData <> wbDataPath.io.toCtrlBlock.writeback 296 ctrlBlock.io.fromMem.stIn <> io.mem.stIn 297 ctrlBlock.io.fromMem.violation <> io.mem.memoryViolation 298 ctrlBlock.io.csrCtrl <> intExuBlock.io.csrio.get.customCtrl 299 ctrlBlock.io.robio.csr.intrBitSet := intExuBlock.io.csrio.get.interrupt 300 ctrlBlock.io.robio.csr.trapTarget := intExuBlock.io.csrio.get.trapTarget 301 ctrlBlock.io.robio.csr.isXRet := intExuBlock.io.csrio.get.isXRet 302 ctrlBlock.io.robio.csr.wfiEvent := intExuBlock.io.csrio.get.wfi_event 303 ctrlBlock.io.robio.lsq <> io.mem.robLsqIO 304 305 intScheduler.io.fromTop.hartId := io.fromTop.hartId 306 intScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 307 intScheduler.io.fromCtrlBlock.pcVec := ctrlBlock.io.toIssueBlock.pcVec 308 intScheduler.io.fromCtrlBlock.targetVec := ctrlBlock.io.toIssueBlock.targetVec 309 intScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 310 intScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.intUops 311 intScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 312 intScheduler.io.vfWriteBack := 0.U.asTypeOf(intScheduler.io.vfWriteBack) 313 314 memScheduler.io.fromTop.hartId := io.fromTop.hartId 315 memScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 316 memScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 317 memScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.memUops 318 memScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 319 memScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 320 memScheduler.io.fromMem.get.scommit := io.mem.sqDeq 321 memScheduler.io.fromMem.get.lcommit := io.mem.lqDeq 322 memScheduler.io.fromMem.get.sqCancelCnt := io.mem.sqCancelCnt 323 memScheduler.io.fromMem.get.lqCancelCnt := io.mem.lqCancelCnt 324 memScheduler.io.fromMem.get.stIssuePtr := io.mem.stIssuePtr 325 memScheduler.io.fromMem.get.memWaitUpdateReq.staIssue.zip(io.mem.stIn).foreach { case (sink, source) => 326 sink.valid := source.valid 327 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 328 sink.bits.uop.robIdx := source.bits.robIdx 329 } 330 io.mem.ldaIqFeedback <> memScheduler.io.fromMem.get.ldaFeedback 331 io.mem.staIqFeedback <> memScheduler.io.fromMem.get.staFeedback 332 333 vfScheduler.io.fromTop.hartId := io.fromTop.hartId 334 vfScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 335 vfScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 336 vfScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.vfUops 337 vfScheduler.io.intWriteBack := 0.U.asTypeOf(vfScheduler.io.intWriteBack) 338 vfScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 339 340 dataPath.io.flush := ctrlBlock.io.toDataPath.flush 341 dataPath.io.vconfigReadPort.addr := ctrlBlock.io.toDataPath.vtypeAddr 342 val vconfig = dataPath.io.vconfigReadPort.data 343 ctrlBlock.io.fromDataPath.vtype := vconfig(7, 0).asTypeOf(new VType) 344 for (i <- 0 until dataPath.io.fromIntIQ.length) { 345 for (j <- 0 until dataPath.io.fromIntIQ(i).length) { 346 NewPipelineConnect(intScheduler.io.toDataPath(i)(j), dataPath.io.fromIntIQ(i)(j), dataPath.io.fromIntIQ(i)(j).valid, 347 intScheduler.io.toDataPath(i)(j).bits.common.robIdx.needFlush(ctrlBlock.io.toDataPath.flush), Option("intScheduler2DataPathPipe")) 348 intScheduler.io.fromDataPath(i)(j) := dataPath.io.toIntIQ(i)(j) 349 } 350 } 351 352 for (i <- 0 until dataPath.io.fromVfIQ.length) { 353 for (j <- 0 until dataPath.io.fromVfIQ(i).length) { 354 NewPipelineConnect(vfScheduler.io.toDataPath(i)(j), dataPath.io.fromVfIQ(i)(j), dataPath.io.fromVfIQ(i)(j).valid, 355 vfScheduler.io.toDataPath(i)(j).bits.common.robIdx.needFlush(ctrlBlock.io.toDataPath.flush), Option("vfScheduler2DataPathPipe")) 356 vfScheduler.io.fromDataPath(i)(j) := dataPath.io.toVfIQ(i)(j) 357 } 358 } 359 360 for (i <- 0 until dataPath.io.fromMemIQ.length) { 361 for (j <- 0 until dataPath.io.fromMemIQ(i).length) { 362 NewPipelineConnect(memScheduler.io.toDataPath(i)(j), dataPath.io.fromMemIQ(i)(j), dataPath.io.fromMemIQ(i)(j).valid, 363 memScheduler.io.toDataPath(i)(j).bits.common.robIdx.needFlush(ctrlBlock.io.toDataPath.flush), Option("memScheduler2DataPathPipe")) 364 memScheduler.io.fromDataPath(i)(j) := dataPath.io.toMemIQ(i)(j) 365 } 366 } 367 368 println(s"[Backend] wbDataPath.io.toIntPreg: ${wbDataPath.io.toIntPreg.size}, dataPath.io.fromIntWb: ${dataPath.io.fromIntWb.size}") 369 println(s"[Backend] wbDataPath.io.toVfPreg: ${wbDataPath.io.toVfPreg.size}, dataPath.io.fromFpWb: ${dataPath.io.fromVfWb.size}") 370 dataPath.io.fromIntWb := wbDataPath.io.toIntPreg 371 dataPath.io.fromVfWb := wbDataPath.io.toVfPreg 372 dataPath.io.debugIntRat := ctrlBlock.io.debug_int_rat 373 dataPath.io.debugFpRat := ctrlBlock.io.debug_fp_rat 374 dataPath.io.debugVecRat := ctrlBlock.io.debug_vec_rat 375 dataPath.io.debugVconfigRat := ctrlBlock.io.debug_vconfig_rat 376 377 intExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 378 for (i <- 0 until intExuBlock.io.in.length) { 379 for (j <- 0 until intExuBlock.io.in(i).length) { 380 NewPipelineConnect(dataPath.io.toIntExu(i)(j), intExuBlock.io.in(i)(j), intExuBlock.io.in(i)(j).fire, 381 Mux(dataPath.io.toIntExu(i)(j).fire, 382 dataPath.io.toIntExu(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush), 383 intExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush))) 384 } 385 } 386 387 private val csrio = intExuBlock.io.csrio.get 388 csrio.hartId := io.fromTop.hartId 389 csrio.perf.retiredInstr <> ctrlBlock.io.robio.csr.perfinfo.retiredInstr 390 csrio.perf.ctrlInfo <> ctrlBlock.io.perfInfo.ctrlInfo 391 csrio.perf.perfEventsCtrl <> ctrlBlock.getPerf 392 csrio.fpu.fflags := ctrlBlock.io.robio.csr.fflags 393 csrio.fpu.isIllegal := false.B // Todo: remove it 394 csrio.fpu.dirty_fs := ctrlBlock.io.robio.csr.dirty_fs 395 csrio.vpu <> 0.U.asTypeOf(csrio.vpu) // Todo 396 397 val debugVconfig = dataPath.io.debugVconfig.asTypeOf(new VConfig) 398 val debugVtype = VType.toVtypeStruct(debugVconfig.vtype).asUInt 399 val debugVl = debugVconfig.vl 400 csrio.vpu.set_vxsat := ctrlBlock.io.robio.csr.vxsat 401 csrio.vpu.set_vstart.valid := ctrlBlock.io.robio.csr.vcsrFlag 402 csrio.vpu.set_vstart.bits := 0.U 403 csrio.vpu.set_vtype.valid := ctrlBlock.io.robio.csr.vcsrFlag 404 csrio.vpu.set_vtype.bits := ZeroExt(debugVtype, XLEN) 405 csrio.vpu.set_vl.valid := ctrlBlock.io.robio.csr.vcsrFlag 406 csrio.vpu.set_vl.bits := ZeroExt(debugVl, XLEN) 407 csrio.exception := ctrlBlock.io.robio.exception 408 csrio.memExceptionVAddr := io.mem.exceptionVAddr 409 csrio.externalInterrupt := io.fromTop.externalInterrupt 410 csrio.distributedUpdate(0) := io.mem.csrDistributedUpdate 411 csrio.distributedUpdate(1) := io.frontendCsrDistributedUpdate 412 csrio.perf <> io.perf 413 private val fenceio = intExuBlock.io.fenceio.get 414 fenceio.disableSfence := csrio.disableSfence 415 io.fenceio <> fenceio 416 417 vfExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 418 for (i <- 0 until vfExuBlock.io.in.size) { 419 for (j <- 0 until vfExuBlock.io.in(i).size) { 420 NewPipelineConnect(dataPath.io.toFpExu(i)(j), vfExuBlock.io.in(i)(j), vfExuBlock.io.in(i)(j).fire, 421 Mux(dataPath.io.toFpExu(i)(j).fire, 422 dataPath.io.toFpExu(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush), 423 vfExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush))) 424 } 425 } 426 vfExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 427 428 wbDataPath.io.flush := ctrlBlock.io.redirect 429 wbDataPath.io.fromTop.hartId := io.fromTop.hartId 430 wbDataPath.io.fromIntExu <> intExuBlock.io.out 431 wbDataPath.io.fromVfExu <> vfExuBlock.io.out 432 wbDataPath.io.fromMemExu.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 433 sink.valid := source.valid 434 source.ready := sink.ready 435 sink.bits.data := source.bits.data 436 sink.bits.pdest := source.bits.uop.pdest 437 sink.bits.robIdx := source.bits.uop.robIdx 438 sink.bits.intWen.foreach(_ := source.bits.uop.rfWen) 439 sink.bits.fpWen.foreach(_ := source.bits.uop.fpWen) 440 sink.bits.vecWen.foreach(_ := source.bits.uop.vecWen) 441 sink.bits.exceptionVec.foreach(_ := source.bits.uop.exceptionVec) 442 sink.bits.flushPipe.foreach(_ := source.bits.uop.flushPipe) 443 sink.bits.replay.foreach(_ := source.bits.uop.replayInst) 444 sink.bits.debug := source.bits.debug 445 sink.bits.debugInfo := 0.U.asTypeOf(sink.bits.debugInfo) 446 sink.bits.lqIdx.foreach(_ := source.bits.uop.lqIdx) 447 sink.bits.sqIdx.foreach(_ := source.bits.uop.sqIdx) 448 sink.bits.ftqIdx.foreach(_ := source.bits.uop.ftqPtr) 449 sink.bits.ftqOffset.foreach(_ := source.bits.uop.ftqOffset) 450 } 451 452 // to mem 453 io.mem.redirect := ctrlBlock.io.redirect 454 io.mem.issueUops.zip(dataPath.io.toMemExu.flatten).foreach { case (sink, source) => 455 sink.valid := source.valid 456 source.ready := sink.ready 457 sink.bits.iqIdx := source.bits.iqIdx 458 sink.bits.isFirstIssue := source.bits.isFirstIssue 459 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 460 sink.bits.src := 0.U.asTypeOf(sink.bits.src) 461 sink.bits.src.zip(source.bits.src).foreach { case (l, r) => l := r} 462 sink.bits.uop.fuType := source.bits.fuType 463 sink.bits.uop.fuOpType := source.bits.fuOpType 464 sink.bits.uop.imm := source.bits.imm 465 sink.bits.uop.robIdx := source.bits.robIdx 466 sink.bits.uop.pdest := source.bits.pdest 467 sink.bits.uop.rfWen := source.bits.rfWen.getOrElse(false.B) 468 sink.bits.uop.fpWen := source.bits.fpWen.getOrElse(false.B) 469 sink.bits.uop.vecWen := source.bits.vecWen.getOrElse(false.B) 470 sink.bits.uop.flushPipe := source.bits.flushPipe.getOrElse(false.B) 471 sink.bits.uop.pc := source.bits.pc.getOrElse(0.U) 472 sink.bits.uop.lqIdx := source.bits.lqIdx.getOrElse(0.U.asTypeOf(new LqPtr)) 473 sink.bits.uop.sqIdx := source.bits.sqIdx.getOrElse(0.U.asTypeOf(new SqPtr)) 474 sink.bits.uop.ftqPtr := source.bits.ftqIdx.getOrElse(0.U.asTypeOf(new FtqPtr)) 475 sink.bits.uop.ftqOffset := source.bits.ftqOffset.getOrElse(0.U) 476 } 477 io.mem.loadFastMatch := memScheduler.io.toMem.get.loadFastMatch.map(_.fastMatch) 478 io.mem.loadFastImm := memScheduler.io.toMem.get.loadFastMatch.map(_.fastImm) 479 io.mem.tlbCsr := csrio.tlb 480 io.mem.csrCtrl := csrio.customCtrl 481 io.mem.sfence := fenceio.sfence 482 io.mem.isStoreException := CommitType.lsInstIsStore(ctrlBlock.io.robio.exception.bits.commitType) 483 require(io.mem.loadPcRead.size == params.LduCnt) 484 io.mem.loadPcRead.zipWithIndex.foreach { case (loadPcRead, i) => 485 loadPcRead.data := ctrlBlock.io.memLdPcRead(i).data 486 ctrlBlock.io.memLdPcRead(i).ptr := loadPcRead.ptr 487 ctrlBlock.io.memLdPcRead(i).offset := loadPcRead.offset 488 } 489 // mem io 490 io.mem.lsqEnqIO <> memScheduler.io.memIO.get.lsqEnqIO 491 io.mem.robLsqIO <> ctrlBlock.io.robio.lsq 492 io.mem.toSbuffer <> fenceio.sbuffer 493 494 io.frontendSfence := fenceio.sfence 495 io.frontendTlbCsr := csrio.tlb 496 io.frontendCsrCtrl := csrio.customCtrl 497 498 io.tlb <> csrio.tlb 499 500 io.csrCustomCtrl := csrio.customCtrl 501 502 dontTouch(memScheduler.io) 503 dontTouch(io.mem) 504 dontTouch(dataPath.io.toMemExu) 505 dontTouch(wbDataPath.io.fromMemExu) 506} 507 508class BackendMemIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 509 // params alias 510 private val LoadQueueSize = VirtualLoadQueueSize 511 // In/Out // Todo: split it into one-direction bundle 512 val lsqEnqIO = Flipped(new LsqEnqIO) 513 val robLsqIO = new RobLsqIO 514 val toSbuffer = new FenceToSbuffer 515 val ldaIqFeedback = Vec(params.LduCnt, Flipped(new MemRSFeedbackIO)) 516 val staIqFeedback = Vec(params.StaCnt, Flipped(new MemRSFeedbackIO)) 517 val loadPcRead = Vec(params.LduCnt, Flipped(new FtqRead(UInt(VAddrBits.W)))) 518 519 // Input 520 val writeBack = MixedVec(Seq.fill(params.LduCnt + params.StaCnt * 2)(Flipped(DecoupledIO(new MemExuOutput()))) ++ Seq.fill(params.VlduCnt)(Flipped(DecoupledIO(new MemExuOutput(true))))) 521 522 val s3_delayed_load_error = Input(Vec(LoadPipelineWidth, Bool())) 523 val stIn = Input(Vec(params.StaCnt, ValidIO(new DynInst()))) 524 val memoryViolation = Flipped(ValidIO(new Redirect)) 525 val exceptionVAddr = Input(UInt(VAddrBits.W)) 526 val sqDeq = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) 527 val lqDeq = Input(UInt(log2Up(CommitWidth + 1).W)) 528 529 val lqCancelCnt = Input(UInt(log2Up(VirtualLoadQueueSize + 1).W)) 530 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 531 532 val otherFastWakeup = Flipped(Vec(params.LduCnt + 2 * params.StaCnt, ValidIO(new DynInst))) 533 val stIssuePtr = Input(new SqPtr()) 534 535 val csrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 536 537 // Output 538 val redirect = ValidIO(new Redirect) // rob flush MemBlock 539 val issueUops = MixedVec(Seq.fill(params.LduCnt + params.StaCnt * 2)(DecoupledIO(new MemExuInput())) ++ Seq.fill(params.VlduCnt)(DecoupledIO(new MemExuInput(true)))) 540 val loadFastMatch = Vec(params.LduCnt, Output(UInt(params.LduCnt.W))) 541 val loadFastImm = Vec(params.LduCnt, Output(UInt(12.W))) // Imm_I 542 543 val tlbCsr = Output(new TlbCsrBundle) 544 val csrCtrl = Output(new CustomCSRCtrlIO) 545 val sfence = Output(new SfenceBundle) 546 val isStoreException = Output(Bool()) 547} 548 549class BackendIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 550 val fromTop = new Bundle { 551 val hartId = Input(UInt(8.W)) 552 val externalInterrupt = new ExternalInterruptIO 553 } 554 555 val toTop = new Bundle { 556 val cpuHalted = Output(Bool()) 557 } 558 559 val fenceio = new FenceIO 560 // Todo: merge these bundles into BackendFrontendIO 561 val frontend = Flipped(new FrontendToCtrlIO) 562 val frontendSfence = Output(new SfenceBundle) 563 val frontendCsrCtrl = Output(new CustomCSRCtrlIO) 564 val frontendTlbCsr = Output(new TlbCsrBundle) 565 // distributed csr write 566 val frontendCsrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 567 568 val mem = new BackendMemIO 569 570 val perf = Input(new PerfCounterIO) 571 572 val tlb = Output(new TlbCsrBundle) 573 574 val csrCustomCtrl = Output(new CustomCSRCtrlIO) 575} 576