1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 23import system.HasSoCParameter 24import utility.{Constantin, ZeroExt} 25import xiangshan._ 26import xiangshan.backend.Bundles.{DynInst, IssueQueueIQWakeUpBundle, LoadShouldCancel, MemExuInput, MemExuOutput, VPUCtrlSignals} 27import xiangshan.backend.ctrlblock.{DebugLSIO, LsTopdownInfo} 28import xiangshan.backend.datapath.DataConfig.{IntData, VecData, FpData} 29import xiangshan.backend.datapath.RdConfig.{IntRD, VfRD} 30import xiangshan.backend.datapath.WbConfig._ 31import xiangshan.backend.datapath.DataConfig._ 32import xiangshan.backend.datapath._ 33import xiangshan.backend.dispatch.CoreDispatchTopDownIO 34import xiangshan.backend.exu.ExuBlock 35import xiangshan.backend.fu.vector.Bundles.{VConfig, VType} 36import xiangshan.backend.fu.{FenceIO, FenceToSbuffer, FuConfig, FuType, PerfCounterIO} 37import xiangshan.backend.issue.EntryBundles._ 38import xiangshan.backend.issue.{CancelNetwork, Scheduler, SchedulerImpBase} 39import xiangshan.backend.rob.{RobCoreTopDownIO, RobDebugRollingIO, RobLsqIO, RobPtr} 40import xiangshan.frontend.{FtqPtr, FtqRead, PreDecodeInfo} 41import xiangshan.mem.{LqPtr, LsqEnqIO, SqPtr} 42import scala.collection.mutable 43 44class Backend(val params: BackendParams)(implicit p: Parameters) extends LazyModule 45 with HasXSParameter { 46 47 override def shouldBeInlined: Boolean = false 48 49 // check read & write port config 50 params.configChecks 51 52 /* Only update the idx in mem-scheduler here 53 * Idx in other schedulers can be updated the same way if needed 54 * 55 * Also note that we filter out the 'stData issue-queues' when counting 56 */ 57 for ((ibp, idx) <- params.memSchdParams.get.issueBlockParams.filter(iq => iq.StdCnt == 0).zipWithIndex) { 58 ibp.updateIdx(idx) 59 } 60 61 println(params.iqWakeUpParams) 62 63 for ((schdCfg, i) <- params.allSchdParams.zipWithIndex) { 64 schdCfg.bindBackendParam(params) 65 } 66 67 for ((iqCfg, i) <- params.allIssueParams.zipWithIndex) { 68 iqCfg.bindBackendParam(params) 69 } 70 71 for ((exuCfg, i) <- params.allExuParams.zipWithIndex) { 72 exuCfg.bindBackendParam(params) 73 exuCfg.updateIQWakeUpConfigs(params.iqWakeUpParams) 74 exuCfg.updateExuIdx(i) 75 } 76 77 println("[Backend] ExuConfigs:") 78 for (exuCfg <- params.allExuParams) { 79 val fuConfigs = exuCfg.fuConfigs 80 val wbPortConfigs = exuCfg.wbPortConfigs 81 val immType = exuCfg.immType 82 83 println("[Backend] " + 84 s"${exuCfg.name}: " + 85 (if (exuCfg.fakeUnit) "fake, " else "") + 86 (if (exuCfg.hasLoadFu || exuCfg.hasHyldaFu) s"LdExuIdx(${backendParams.getLdExuIdx(exuCfg)})" else "") + 87 s"${fuConfigs.map(_.name).mkString("fu(s): {", ",", "}")}, " + 88 s"${wbPortConfigs.mkString("wb: {", ",", "}")}, " + 89 s"${immType.map(SelImm.mkString(_)).mkString("imm: {", ",", "}")}, " + 90 s"latMax(${exuCfg.latencyValMax}), ${exuCfg.fuLatancySet.mkString("lat: {", ",", "}")}, " + 91 s"srcReg(${exuCfg.numRegSrc})" 92 ) 93 require( 94 wbPortConfigs.collectFirst { case x: IntWB => x }.nonEmpty == 95 fuConfigs.map(_.writeIntRf).reduce(_ || _), 96 s"${exuCfg.name} int wb port has no priority" 97 ) 98 require( 99 wbPortConfigs.collectFirst { case x: FpWB => x }.nonEmpty == 100 fuConfigs.map(x => x.writeFpRf).reduce(_ || _), 101 s"${exuCfg.name} fp wb port has no priority" 102 ) 103 require( 104 wbPortConfigs.collectFirst { case x: VfWB => x }.nonEmpty == 105 fuConfigs.map(x => x.writeVecRf).reduce(_ || _), 106 s"${exuCfg.name} vec wb port has no priority" 107 ) 108 } 109 110 println(s"[Backend] all fu configs") 111 for (cfg <- FuConfig.allConfigs) { 112 println(s"[Backend] $cfg") 113 } 114 115 println(s"[Backend] Int RdConfigs: ExuName(Priority)") 116 for ((port, seq) <- params.getRdPortParams(IntData())) { 117 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 118 } 119 120 println(s"[Backend] Int WbConfigs: ExuName(Priority)") 121 for ((port, seq) <- params.getWbPortParams(IntData())) { 122 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 123 } 124 125 println(s"[Backend] Fp RdConfigs: ExuName(Priority)") 126 for ((port, seq) <- params.getRdPortParams(FpData())) { 127 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 128 } 129 130 println(s"[Backend] Fp WbConfigs: ExuName(Priority)") 131 for ((port, seq) <- params.getWbPortParams(FpData())) { 132 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 133 } 134 135 println(s"[Backend] Vf RdConfigs: ExuName(Priority)") 136 for ((port, seq) <- params.getRdPortParams(VecData())) { 137 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 138 } 139 140 println(s"[Backend] Vf WbConfigs: ExuName(Priority)") 141 for ((port, seq) <- params.getWbPortParams(VecData())) { 142 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 143 } 144 145 println(s"[Backend] Dispatch Configs:") 146 println(s"[Backend] Load IQ enq width(${params.numLoadDp}), Store IQ enq width(${params.numStoreDp})") 147 println(s"[Backend] Load DP width(${LSQLdEnqWidth}), Store DP width(${LSQStEnqWidth})") 148 149 params.updateCopyPdestInfo 150 println(s"[Backend] copyPdestInfo ${params.copyPdestInfo}") 151 params.allExuParams.map(_.copyNum) 152 val ctrlBlock = LazyModule(new CtrlBlock(params)) 153 val pcTargetMem = LazyModule(new PcTargetMem(params)) 154 val intScheduler = params.intSchdParams.map(x => LazyModule(new Scheduler(x))) 155 val fpScheduler = params.fpSchdParams.map(x => LazyModule(new Scheduler(x))) 156 val vfScheduler = params.vfSchdParams.map(x => LazyModule(new Scheduler(x))) 157 val memScheduler = params.memSchdParams.map(x => LazyModule(new Scheduler(x))) 158 val dataPath = LazyModule(new DataPath(params)) 159 val intExuBlock = params.intSchdParams.map(x => LazyModule(new ExuBlock(x))) 160 val fpExuBlock = params.fpSchdParams.map(x => LazyModule(new ExuBlock(x))) 161 val vfExuBlock = params.vfSchdParams.map(x => LazyModule(new ExuBlock(x))) 162 val wbFuBusyTable = LazyModule(new WbFuBusyTable(params)) 163 164 lazy val module = new BackendImp(this) 165} 166 167class BackendImp(override val wrapper: Backend)(implicit p: Parameters) extends LazyModuleImp(wrapper) 168 with HasXSParameter { 169 implicit private val params: BackendParams = wrapper.params 170 171 val io = IO(new BackendIO()(p, wrapper.params)) 172 173 private val ctrlBlock = wrapper.ctrlBlock.module 174 private val pcTargetMem = wrapper.pcTargetMem.module 175 private val intScheduler: SchedulerImpBase = wrapper.intScheduler.get.module 176 private val fpScheduler = wrapper.fpScheduler.get.module 177 private val vfScheduler = wrapper.vfScheduler.get.module 178 private val memScheduler = wrapper.memScheduler.get.module 179 private val dataPath = wrapper.dataPath.module 180 private val intExuBlock = wrapper.intExuBlock.get.module 181 private val fpExuBlock = wrapper.fpExuBlock.get.module 182 private val vfExuBlock = wrapper.vfExuBlock.get.module 183 private val og2ForVector = Module(new Og2ForVector(params)) 184 private val bypassNetwork = Module(new BypassNetwork) 185 private val wbDataPath = Module(new WbDataPath(params)) 186 private val wbFuBusyTable = wrapper.wbFuBusyTable.module 187 188 private val iqWakeUpMappedBundle: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = ( 189 intScheduler.io.toSchedulers.wakeupVec ++ 190 fpScheduler.io.toSchedulers.wakeupVec ++ 191 vfScheduler.io.toSchedulers.wakeupVec ++ 192 memScheduler.io.toSchedulers.wakeupVec 193 ).map(x => (x.bits.exuIdx, x)).toMap 194 195 println(s"[Backend] iq wake up keys: ${iqWakeUpMappedBundle.keys}") 196 197 wbFuBusyTable.io.in.intSchdBusyTable := intScheduler.io.wbFuBusyTable 198 wbFuBusyTable.io.in.fpSchdBusyTable := fpScheduler.io.wbFuBusyTable 199 wbFuBusyTable.io.in.vfSchdBusyTable := vfScheduler.io.wbFuBusyTable 200 wbFuBusyTable.io.in.memSchdBusyTable := memScheduler.io.wbFuBusyTable 201 intScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.intRespRead 202 fpScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.fpRespRead 203 vfScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.vfRespRead 204 memScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.memRespRead 205 dataPath.io.wbConfictRead := wbFuBusyTable.io.out.wbConflictRead 206 207 private val og1CancelOH: UInt = dataPath.io.og1CancelOH 208 private val og0CancelOH: UInt = dataPath.io.og0CancelOH 209 private val cancelToBusyTable = dataPath.io.cancelToBusyTable 210 private val vlIsZero = intExuBlock.io.vlIsZero.get 211 private val vlIsVlmax = intExuBlock.io.vlIsVlmax.get 212 213 ctrlBlock.io.intIQValidNumVec := intScheduler.io.intIQValidNumVec 214 ctrlBlock.io.fpIQValidNumVec := fpScheduler.io.fpIQValidNumVec 215 ctrlBlock.io.fromTop.hartId := io.fromTop.hartId 216 ctrlBlock.io.frontend <> io.frontend 217 ctrlBlock.io.fromWB.wbData <> wbDataPath.io.toCtrlBlock.writeback 218 ctrlBlock.io.fromMem.stIn <> io.mem.stIn 219 ctrlBlock.io.fromMem.violation <> io.mem.memoryViolation 220 ctrlBlock.io.lqCanAccept := io.mem.lqCanAccept 221 ctrlBlock.io.sqCanAccept := io.mem.sqCanAccept 222 ctrlBlock.io.csrCtrl <> intExuBlock.io.csrio.get.customCtrl 223 ctrlBlock.io.robio.csr.intrBitSet := intExuBlock.io.csrio.get.interrupt 224 ctrlBlock.io.robio.csr.trapTarget := intExuBlock.io.csrio.get.trapTarget 225 ctrlBlock.io.robio.csr.isXRet := intExuBlock.io.csrio.get.isXRet 226 ctrlBlock.io.robio.csr.wfiEvent := intExuBlock.io.csrio.get.wfi_event 227 ctrlBlock.io.robio.lsq <> io.mem.robLsqIO 228 ctrlBlock.io.robio.lsTopdownInfo <> io.mem.lsTopdownInfo 229 ctrlBlock.io.robio.debug_ls <> io.mem.debugLS 230 ctrlBlock.perfinfo := DontCare // TODO: Implement backend hpm 231 ctrlBlock.io.debugEnqLsq.canAccept := io.mem.lsqEnqIO.canAccept 232 ctrlBlock.io.debugEnqLsq.resp := io.mem.lsqEnqIO.resp 233 ctrlBlock.io.debugEnqLsq.req := memScheduler.io.memIO.get.lsqEnqIO.req 234 ctrlBlock.io.debugEnqLsq.needAlloc := memScheduler.io.memIO.get.lsqEnqIO.needAlloc 235 236 intScheduler.io.fromTop.hartId := io.fromTop.hartId 237 intScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 238 intScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 239 intScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.intUops 240 intScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 241 intScheduler.io.fpWriteBack := 0.U.asTypeOf(intScheduler.io.fpWriteBack) 242 intScheduler.io.vfWriteBack := 0.U.asTypeOf(intScheduler.io.vfWriteBack) 243 intScheduler.io.v0WriteBack := 0.U.asTypeOf(intScheduler.io.v0WriteBack) 244 intScheduler.io.vlWriteBack := 0.U.asTypeOf(intScheduler.io.vlWriteBack) 245 intScheduler.io.fromDataPath.resp := dataPath.io.toIntIQ 246 intScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 247 intScheduler.io.fromDataPath.og0Cancel := og0CancelOH 248 intScheduler.io.fromDataPath.og1Cancel := og1CancelOH 249 intScheduler.io.ldCancel := io.mem.ldCancel 250 intScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 251 intScheduler.io.vlWriteBackInfo.vlIsZero := false.B 252 intScheduler.io.vlWriteBackInfo.vlIsVlmax := false.B 253 254 fpScheduler.io.fromTop.hartId := io.fromTop.hartId 255 fpScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 256 fpScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 257 fpScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.fpUops 258 fpScheduler.io.intWriteBack := 0.U.asTypeOf(fpScheduler.io.intWriteBack) 259 fpScheduler.io.fpWriteBack := wbDataPath.io.toFpPreg 260 fpScheduler.io.vfWriteBack := 0.U.asTypeOf(fpScheduler.io.vfWriteBack) 261 fpScheduler.io.v0WriteBack := 0.U.asTypeOf(fpScheduler.io.v0WriteBack) 262 fpScheduler.io.vlWriteBack := 0.U.asTypeOf(fpScheduler.io.vlWriteBack) 263 fpScheduler.io.fromDataPath.resp := dataPath.io.toFpIQ 264 fpScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 265 fpScheduler.io.fromDataPath.og0Cancel := og0CancelOH 266 fpScheduler.io.fromDataPath.og1Cancel := og1CancelOH 267 fpScheduler.io.ldCancel := io.mem.ldCancel 268 fpScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 269 fpScheduler.io.vlWriteBackInfo.vlIsZero := false.B 270 fpScheduler.io.vlWriteBackInfo.vlIsVlmax := false.B 271 272 memScheduler.io.fromTop.hartId := io.fromTop.hartId 273 memScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 274 memScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 275 memScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.memUops 276 memScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 277 memScheduler.io.fpWriteBack := wbDataPath.io.toFpPreg 278 memScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 279 memScheduler.io.v0WriteBack := wbDataPath.io.toV0Preg 280 memScheduler.io.vlWriteBack := wbDataPath.io.toVlPreg 281 memScheduler.io.fromMem.get.scommit := io.mem.sqDeq 282 memScheduler.io.fromMem.get.lcommit := io.mem.lqDeq 283 memScheduler.io.fromMem.get.wakeup := io.mem.wakeup 284 memScheduler.io.fromMem.get.sqDeqPtr := io.mem.sqDeqPtr 285 memScheduler.io.fromMem.get.lqDeqPtr := io.mem.lqDeqPtr 286 memScheduler.io.fromMem.get.sqCancelCnt := io.mem.sqCancelCnt 287 memScheduler.io.fromMem.get.lqCancelCnt := io.mem.lqCancelCnt 288 memScheduler.io.fromMem.get.stIssuePtr := io.mem.stIssuePtr 289 require(memScheduler.io.fromMem.get.memWaitUpdateReq.robIdx.length == io.mem.stIn.length) 290 memScheduler.io.fromMem.get.memWaitUpdateReq.robIdx.zip(io.mem.stIn).foreach { case (sink, source) => 291 sink.valid := source.valid 292 sink.bits := source.bits.robIdx 293 } 294 memScheduler.io.fromMem.get.memWaitUpdateReq.sqIdx := DontCare // TODO 295 memScheduler.io.fromDataPath.resp := dataPath.io.toMemIQ 296 memScheduler.io.fromMem.get.ldaFeedback := io.mem.ldaIqFeedback 297 memScheduler.io.fromMem.get.staFeedback := io.mem.staIqFeedback 298 memScheduler.io.fromMem.get.hyuFeedback := io.mem.hyuIqFeedback 299 memScheduler.io.fromMem.get.vstuFeedback := io.mem.vstuIqFeedback 300 memScheduler.io.fromMem.get.vlduFeedback := io.mem.vlduIqFeedback 301 memScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 302 memScheduler.io.fromDataPath.og0Cancel := og0CancelOH 303 memScheduler.io.fromDataPath.og1Cancel := og1CancelOH 304 memScheduler.io.ldCancel := io.mem.ldCancel 305 memScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 306 memScheduler.io.vlWriteBackInfo.vlIsZero := vlIsZero 307 memScheduler.io.vlWriteBackInfo.vlIsVlmax := vlIsVlmax 308 309 vfScheduler.io.fromTop.hartId := io.fromTop.hartId 310 vfScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 311 vfScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 312 vfScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.vfUops 313 vfScheduler.io.intWriteBack := 0.U.asTypeOf(vfScheduler.io.intWriteBack) 314 vfScheduler.io.fpWriteBack := 0.U.asTypeOf(vfScheduler.io.fpWriteBack) 315 vfScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 316 vfScheduler.io.v0WriteBack := wbDataPath.io.toV0Preg 317 vfScheduler.io.vlWriteBack := wbDataPath.io.toVlPreg 318 vfScheduler.io.fromDataPath.resp := dataPath.io.toVfIQ 319 vfScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 320 vfScheduler.io.fromDataPath.og0Cancel := og0CancelOH 321 vfScheduler.io.fromDataPath.og1Cancel := og1CancelOH 322 vfScheduler.io.ldCancel := io.mem.ldCancel 323 vfScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 324 vfScheduler.io.vlWriteBackInfo.vlIsZero := vlIsZero 325 vfScheduler.io.vlWriteBackInfo.vlIsVlmax := vlIsVlmax 326 vfScheduler.io.fromOg2.get := og2ForVector.io.toVfIQ 327 328 dataPath.io.hartId := io.fromTop.hartId 329 dataPath.io.flush := ctrlBlock.io.toDataPath.flush 330 331 dataPath.io.fromIntIQ <> intScheduler.io.toDataPathAfterDelay 332 dataPath.io.fromFpIQ <> fpScheduler.io.toDataPathAfterDelay 333 dataPath.io.fromVfIQ <> vfScheduler.io.toDataPathAfterDelay 334 dataPath.io.fromMemIQ <> memScheduler.io.toDataPathAfterDelay 335 336 dataPath.io.ldCancel := io.mem.ldCancel 337 338 println(s"[Backend] wbDataPath.io.toIntPreg: ${wbDataPath.io.toIntPreg.size}, dataPath.io.fromIntWb: ${dataPath.io.fromIntWb.size}") 339 println(s"[Backend] wbDataPath.io.toVfPreg: ${wbDataPath.io.toVfPreg.size}, dataPath.io.fromFpWb: ${dataPath.io.fromVfWb.size}") 340 dataPath.io.fromIntWb := wbDataPath.io.toIntPreg 341 dataPath.io.fromFpWb := wbDataPath.io.toFpPreg 342 dataPath.io.fromVfWb := wbDataPath.io.toVfPreg 343 dataPath.io.fromV0Wb := wbDataPath.io.toV0Preg 344 dataPath.io.fromVlWb := wbDataPath.io.toVlPreg 345 dataPath.io.debugIntRat .foreach(_ := ctrlBlock.io.debug_int_rat.get) 346 dataPath.io.debugFpRat .foreach(_ := ctrlBlock.io.debug_fp_rat.get) 347 dataPath.io.debugVecRat .foreach(_ := ctrlBlock.io.debug_vec_rat.get) 348 dataPath.io.debugV0Rat .foreach(_ := ctrlBlock.io.debug_v0_rat.get) 349 dataPath.io.debugVlRat .foreach(_ := ctrlBlock.io.debug_vl_rat.get) 350 351 og2ForVector.io.flush := ctrlBlock.io.toDataPath.flush 352 og2ForVector.io.ldCancel := io.mem.ldCancel 353 og2ForVector.io.fromOg1NoReg <> dataPath.io.toVecExu 354 og2ForVector.io.fromOg1ImmInfo := dataPath.io.og1ImmInfo.zip(params.allExuParams).filter(_._2.isVfExeUnit).map(_._1) 355 356 bypassNetwork.io.fromDataPath.int <> dataPath.io.toIntExu 357 bypassNetwork.io.fromDataPath.fp <> dataPath.io.toFpExu 358 bypassNetwork.io.fromDataPath.vf <> og2ForVector.io.toVfExu 359 bypassNetwork.io.fromDataPath.mem <> dataPath.io.toMemExu 360 bypassNetwork.io.fromDataPath.immInfo := dataPath.io.og1ImmInfo 361 bypassNetwork.io.fromDataPath.immInfo.zip(params.allExuParams).filter(_._2.isVfExeUnit).map(_._1).zip(og2ForVector.io.toVfImmInfo).map{ 362 case (vfImmInfo, og2ImmInfo) => vfImmInfo := og2ImmInfo 363 } 364 bypassNetwork.io.fromExus.connectExuOutput(_.int)(intExuBlock.io.out) 365 bypassNetwork.io.fromExus.connectExuOutput(_.fp)(fpExuBlock.io.out) 366 bypassNetwork.io.fromExus.connectExuOutput(_.vf)(vfExuBlock.io.out) 367 368 require(bypassNetwork.io.fromExus.mem.flatten.size == io.mem.writeBack.size, 369 s"bypassNetwork.io.fromExus.mem.flatten.size(${bypassNetwork.io.fromExus.mem.flatten.size}: ${bypassNetwork.io.fromExus.mem.map(_.size)}, " + 370 s"io.mem.writeback(${io.mem.writeBack.size})" 371 ) 372 bypassNetwork.io.fromExus.mem.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 373 sink.valid := source.valid 374 sink.bits.pdest := source.bits.uop.pdest 375 sink.bits.data := source.bits.data 376 } 377 378 379 intExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 380 for (i <- 0 until intExuBlock.io.in.length) { 381 for (j <- 0 until intExuBlock.io.in(i).length) { 382 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.int(i)(j).bits.loadDependency, io.mem.ldCancel) 383 NewPipelineConnect( 384 bypassNetwork.io.toExus.int(i)(j), intExuBlock.io.in(i)(j), intExuBlock.io.in(i)(j).fire, 385 Mux( 386 bypassNetwork.io.toExus.int(i)(j).fire, 387 bypassNetwork.io.toExus.int(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 388 intExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 389 ), 390 Option("bypassNetwork2intExuBlock") 391 ) 392 } 393 } 394 395 pcTargetMem.io.fromFrontendFtq := io.frontend.fromFtq 396 pcTargetMem.io.toDataPath <> dataPath.io.fromPcTargetMem 397 398 private val csrin = intExuBlock.io.csrin.get 399 csrin.hartId := io.fromTop.hartId 400 csrin.setIpNumValidVec2 := io.fromTop.setIpNumValidVec2 401 csrin.setIpNum := io.fromTop.setIpNum 402 403 private val csrio = intExuBlock.io.csrio.get 404 csrio.hartId := io.fromTop.hartId 405 csrio.fpu.fflags := ctrlBlock.io.robio.csr.fflags 406 csrio.fpu.isIllegal := false.B // Todo: remove it 407 csrio.fpu.dirty_fs := ctrlBlock.io.robio.csr.dirty_fs 408 csrio.vpu <> WireDefault(0.U.asTypeOf(csrio.vpu)) // Todo 409 410 val fromIntExuVsetVType = intExuBlock.io.vtype.getOrElse(0.U.asTypeOf((Valid(new VType)))) 411 val fromVfExuVsetVType = vfExuBlock.io.vtype.getOrElse(0.U.asTypeOf((Valid(new VType)))) 412 val fromVsetVType = Mux(fromIntExuVsetVType.valid, fromIntExuVsetVType.bits, fromVfExuVsetVType.bits) 413 val vsetvlVType = RegEnable(fromVsetVType, 0.U.asTypeOf(new VType), fromIntExuVsetVType.valid || fromVfExuVsetVType.valid) 414 ctrlBlock.io.toDecode.vsetvlVType := vsetvlVType 415 416 val commitVType = ctrlBlock.io.robio.commitVType.vtype 417 val hasVsetvl = ctrlBlock.io.robio.commitVType.hasVsetvl 418 val vtype = VType.toVtypeStruct(Mux(hasVsetvl, vsetvlVType, commitVType.bits)).asUInt 419 420 // csr not store the value of vl, so when using difftest we assign the value of vl to debugVl 421 val debugVl_s0 = WireInit(UInt(VlData().dataWidth.W), 0.U) 422 val debugVl_s1 = WireInit(UInt(VlData().dataWidth.W), 0.U) 423 debugVl_s0 := dataPath.io.debugVl.getOrElse(0.U.asTypeOf(UInt(VlData().dataWidth.W))) 424 debugVl_s1 := RegNext(debugVl_s0) 425 csrio.vpu.set_vxsat := ctrlBlock.io.robio.csr.vxsat 426 csrio.vpu.set_vstart.valid := ctrlBlock.io.robio.csr.vstart.valid 427 csrio.vpu.set_vstart.bits := ctrlBlock.io.robio.csr.vstart.bits 428 ctrlBlock.io.toDecode.vstart := csrio.vpu.vstart 429 //Todo here need change design 430 csrio.vpu.set_vtype.valid := commitVType.valid 431 csrio.vpu.set_vtype.bits := ZeroExt(vtype, XLEN) 432 csrio.vpu.vl := ZeroExt(debugVl_s1, XLEN) 433 csrio.vpu.dirty_vs := ctrlBlock.io.robio.csr.dirty_vs 434 csrio.exception := ctrlBlock.io.robio.exception 435 csrio.memExceptionVAddr := io.mem.exceptionAddr.vaddr 436 csrio.memExceptionGPAddr := io.mem.exceptionAddr.gpaddr 437 csrio.externalInterrupt := io.fromTop.externalInterrupt 438 csrio.distributedUpdate(0) := io.mem.csrDistributedUpdate 439 csrio.distributedUpdate(1) := io.frontendCsrDistributedUpdate 440 csrio.perf <> io.perf 441 csrio.perf.retiredInstr <> ctrlBlock.io.robio.csr.perfinfo.retiredInstr 442 csrio.perf.ctrlInfo <> ctrlBlock.io.perfInfo.ctrlInfo 443 csrio.perf.perfEventsCtrl <> ctrlBlock.getPerf 444 private val fenceio = intExuBlock.io.fenceio.get 445 io.fenceio <> fenceio 446 fenceio.disableSfence := csrio.disableSfence 447 fenceio.disableHfenceg := csrio.disableHfenceg 448 fenceio.disableHfencev := csrio.disableHfencev 449 fenceio.virtMode := csrio.customCtrl.virtMode 450 451 // to fpExuBlock 452 fpExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 453 for (i <- 0 until fpExuBlock.io.in.length) { 454 for (j <- 0 until fpExuBlock.io.in(i).length) { 455 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.fp(i)(j).bits.loadDependency, io.mem.ldCancel) 456 NewPipelineConnect( 457 bypassNetwork.io.toExus.fp(i)(j), fpExuBlock.io.in(i)(j), fpExuBlock.io.in(i)(j).fire, 458 Mux( 459 bypassNetwork.io.toExus.fp(i)(j).fire, 460 bypassNetwork.io.toExus.fp(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 461 fpExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 462 ), 463 Option("bypassNetwork2fpExuBlock") 464 ) 465 } 466 } 467 468 vfExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 469 for (i <- 0 until vfExuBlock.io.in.size) { 470 for (j <- 0 until vfExuBlock.io.in(i).size) { 471 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.vf(i)(j).bits.loadDependency, io.mem.ldCancel) 472 NewPipelineConnect( 473 bypassNetwork.io.toExus.vf(i)(j), vfExuBlock.io.in(i)(j), vfExuBlock.io.in(i)(j).fire, 474 Mux( 475 bypassNetwork.io.toExus.vf(i)(j).fire, 476 bypassNetwork.io.toExus.vf(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 477 vfExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 478 ), 479 Option("bypassNetwork2vfExuBlock") 480 ) 481 482 } 483 } 484 485 intExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 486 fpExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 487 fpExuBlock.io.vxrm.foreach(_ := csrio.vpu.vxrm) 488 vfExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 489 vfExuBlock.io.vxrm.foreach(_ := csrio.vpu.vxrm) 490 491 wbDataPath.io.flush := ctrlBlock.io.redirect 492 wbDataPath.io.fromTop.hartId := io.fromTop.hartId 493 wbDataPath.io.fromIntExu <> intExuBlock.io.out 494 wbDataPath.io.fromFpExu <> fpExuBlock.io.out 495 wbDataPath.io.fromVfExu <> vfExuBlock.io.out 496 wbDataPath.io.fromMemExu.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 497 sink.valid := source.valid 498 source.ready := sink.ready 499 sink.bits.data := VecInit(Seq.fill(sink.bits.params.wbPathNum)(source.bits.data)) 500 sink.bits.pdest := source.bits.uop.pdest 501 sink.bits.robIdx := source.bits.uop.robIdx 502 sink.bits.intWen.foreach(_ := source.bits.uop.rfWen) 503 sink.bits.fpWen.foreach(_ := source.bits.uop.fpWen) 504 sink.bits.vecWen.foreach(_ := source.bits.uop.vecWen) 505 sink.bits.v0Wen.foreach(_ := source.bits.uop.v0Wen) 506 sink.bits.vlWen.foreach(_ := source.bits.uop.vlWen) 507 sink.bits.exceptionVec.foreach(_ := source.bits.uop.exceptionVec) 508 sink.bits.flushPipe.foreach(_ := source.bits.uop.flushPipe) 509 sink.bits.replay.foreach(_ := source.bits.uop.replayInst) 510 sink.bits.debug := source.bits.debug 511 sink.bits.debugInfo := source.bits.uop.debugInfo 512 sink.bits.lqIdx.foreach(_ := source.bits.uop.lqIdx) 513 sink.bits.sqIdx.foreach(_ := source.bits.uop.sqIdx) 514 sink.bits.predecodeInfo.foreach(_ := source.bits.uop.preDecodeInfo) 515 sink.bits.vls.foreach(x => { 516 x.vdIdx := source.bits.vdIdx.get 517 x.vdIdxInField := source.bits.vdIdxInField.get 518 x.vpu := source.bits.uop.vpu 519 x.oldVdPsrc := source.bits.uop.psrc(2) 520 x.isIndexed := VlduType.isIndexed(source.bits.uop.fuOpType) 521 x.isMasked := VlduType.isMasked(source.bits.uop.fuOpType) 522 }) 523 sink.bits.trigger.foreach(_ := source.bits.uop.trigger) 524 } 525 526 // to mem 527 private val memIssueParams = params.memSchdParams.get.issueBlockParams 528 private val memExuBlocksHasLDU = memIssueParams.map(_.exuBlockParams.map(x => x.hasLoadFu || x.hasHyldaFu)) 529 private val memExuBlocksHasVecLoad = memIssueParams.map(_.exuBlockParams.map(x => x.hasVLoadFu)) 530 println(s"[Backend] memExuBlocksHasLDU: $memExuBlocksHasLDU") 531 println(s"[Backend] memExuBlocksHasVecLoad: $memExuBlocksHasVecLoad") 532 533 private val toMem = Wire(bypassNetwork.io.toExus.mem.cloneType) 534 for (i <- toMem.indices) { 535 for (j <- toMem(i).indices) { 536 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.mem(i)(j).bits.loadDependency, io.mem.ldCancel) 537 val issueTimeout = 538 if (memExuBlocksHasLDU(i)(j)) 539 Counter(0 until 16, toMem(i)(j).valid && !toMem(i)(j).fire, bypassNetwork.io.toExus.mem(i)(j).fire)._2 540 else 541 false.B 542 543 if (memScheduler.io.loadFinalIssueResp(i).nonEmpty && memExuBlocksHasLDU(i)(j)) { 544 memScheduler.io.loadFinalIssueResp(i)(j).valid := issueTimeout 545 memScheduler.io.loadFinalIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType 546 memScheduler.io.loadFinalIssueResp(i)(j).bits.resp := RespType.block 547 memScheduler.io.loadFinalIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx 548 memScheduler.io.loadFinalIssueResp(i)(j).bits.uopIdx.foreach(_ := toMem(i)(j).bits.vpu.get.vuopIdx) 549 memScheduler.io.loadFinalIssueResp(i)(j).bits.sqIdx.foreach(_ := toMem(i)(j).bits.sqIdx.get) 550 memScheduler.io.loadFinalIssueResp(i)(j).bits.lqIdx.foreach(_ := toMem(i)(j).bits.lqIdx.get) 551 } 552 553 NewPipelineConnect( 554 bypassNetwork.io.toExus.mem(i)(j), toMem(i)(j), toMem(i)(j).fire, 555 Mux( 556 bypassNetwork.io.toExus.mem(i)(j).fire, 557 bypassNetwork.io.toExus.mem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 558 toMem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || issueTimeout 559 ), 560 Option("bypassNetwork2toMemExus") 561 ) 562 563 if (memScheduler.io.memAddrIssueResp(i).nonEmpty && memExuBlocksHasLDU(i)(j)) { 564 memScheduler.io.memAddrIssueResp(i)(j).valid := toMem(i)(j).fire && FuType.isLoad(toMem(i)(j).bits.fuType) 565 memScheduler.io.memAddrIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType 566 memScheduler.io.memAddrIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx 567 memScheduler.io.memAddrIssueResp(i)(j).bits.sqIdx.foreach(_ := toMem(i)(j).bits.sqIdx.get) 568 memScheduler.io.memAddrIssueResp(i)(j).bits.lqIdx.foreach(_ := toMem(i)(j).bits.lqIdx.get) 569 memScheduler.io.memAddrIssueResp(i)(j).bits.resp := RespType.success // for load inst, firing at toMem means issuing successfully 570 } 571 572 if (memScheduler.io.vecLoadIssueResp(i).nonEmpty && memExuBlocksHasVecLoad(i)(j)) { 573 memScheduler.io.vecLoadIssueResp(i)(j) match { 574 case resp => 575 resp.valid := toMem(i)(j).fire && VlduType.isVecLd(toMem(i)(j).bits.fuOpType) 576 resp.bits.fuType := toMem(i)(j).bits.fuType 577 resp.bits.robIdx := toMem(i)(j).bits.robIdx 578 resp.bits.uopIdx.get := toMem(i)(j).bits.vpu.get.vuopIdx 579 resp.bits.sqIdx.get := toMem(i)(j).bits.sqIdx.get 580 resp.bits.lqIdx.get := toMem(i)(j).bits.lqIdx.get 581 resp.bits.resp := RespType.success 582 } 583 if (backendParams.debugEn){ 584 dontTouch(memScheduler.io.vecLoadIssueResp(i)(j)) 585 } 586 } 587 } 588 } 589 590 io.mem.redirect := ctrlBlock.io.redirect 591 io.mem.issueUops.zip(toMem.flatten).foreach { case (sink, source) => 592 val enableMdp = Constantin.createRecord("EnableMdp", true) 593 sink.valid := source.valid 594 source.ready := sink.ready 595 sink.bits.iqIdx := source.bits.iqIdx 596 sink.bits.isFirstIssue := source.bits.isFirstIssue 597 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 598 sink.bits.src := 0.U.asTypeOf(sink.bits.src) 599 sink.bits.src.zip(source.bits.src).foreach { case (l, r) => l := r} 600 sink.bits.uop.fuType := source.bits.fuType 601 sink.bits.uop.fuOpType := source.bits.fuOpType 602 sink.bits.uop.imm := source.bits.imm 603 sink.bits.uop.robIdx := source.bits.robIdx 604 sink.bits.uop.pdest := source.bits.pdest 605 sink.bits.uop.rfWen := source.bits.rfWen.getOrElse(false.B) 606 sink.bits.uop.fpWen := source.bits.fpWen.getOrElse(false.B) 607 sink.bits.uop.vecWen := source.bits.vecWen.getOrElse(false.B) 608 sink.bits.uop.v0Wen := source.bits.v0Wen.getOrElse(false.B) 609 sink.bits.uop.vlWen := source.bits.vlWen.getOrElse(false.B) 610 sink.bits.uop.flushPipe := source.bits.flushPipe.getOrElse(false.B) 611 sink.bits.uop.pc := source.bits.pc.getOrElse(0.U) 612 sink.bits.uop.loadWaitBit := Mux(enableMdp, source.bits.loadWaitBit.getOrElse(false.B), false.B) 613 sink.bits.uop.waitForRobIdx := Mux(enableMdp, source.bits.waitForRobIdx.getOrElse(0.U.asTypeOf(new RobPtr)), 0.U.asTypeOf(new RobPtr)) 614 sink.bits.uop.storeSetHit := Mux(enableMdp, source.bits.storeSetHit.getOrElse(false.B), false.B) 615 sink.bits.uop.loadWaitStrict := Mux(enableMdp, source.bits.loadWaitStrict.getOrElse(false.B), false.B) 616 sink.bits.uop.ssid := Mux(enableMdp, source.bits.ssid.getOrElse(0.U(SSIDWidth.W)), 0.U(SSIDWidth.W)) 617 sink.bits.uop.lqIdx := source.bits.lqIdx.getOrElse(0.U.asTypeOf(new LqPtr)) 618 sink.bits.uop.sqIdx := source.bits.sqIdx.getOrElse(0.U.asTypeOf(new SqPtr)) 619 sink.bits.uop.ftqPtr := source.bits.ftqIdx.getOrElse(0.U.asTypeOf(new FtqPtr)) 620 sink.bits.uop.ftqOffset := source.bits.ftqOffset.getOrElse(0.U) 621 sink.bits.uop.debugInfo := source.bits.perfDebugInfo 622 sink.bits.uop.vpu := source.bits.vpu.getOrElse(0.U.asTypeOf(new VPUCtrlSignals)) 623 sink.bits.uop.preDecodeInfo := source.bits.preDecode.getOrElse(0.U.asTypeOf(new PreDecodeInfo)) 624 sink.bits.uop.numLsElem := source.bits.numLsElem.getOrElse(0.U) // Todo: remove this bundle, keep only the one below 625 sink.bits.flowNum.foreach(_ := source.bits.numLsElem.get) 626 } 627 io.mem.loadFastMatch := memScheduler.io.toMem.get.loadFastMatch.map(_.fastMatch) 628 io.mem.loadFastImm := memScheduler.io.toMem.get.loadFastMatch.map(_.fastImm) 629 io.mem.tlbCsr := csrio.tlb 630 io.mem.csrCtrl := csrio.customCtrl 631 io.mem.sfence := fenceio.sfence 632 io.mem.isStoreException := CommitType.lsInstIsStore(ctrlBlock.io.robio.exception.bits.commitType) 633 io.mem.isVlsException := ctrlBlock.io.robio.exception.bits.vls 634 require(io.mem.loadPcRead.size == params.LduCnt) 635 io.mem.loadPcRead.zipWithIndex.foreach { case (loadPcRead, i) => 636 loadPcRead := ctrlBlock.io.memLdPcRead(i).data 637 ctrlBlock.io.memLdPcRead(i).vld := io.mem.issueLda(i).valid 638 ctrlBlock.io.memLdPcRead(i).ptr := io.mem.issueLda(i).bits.uop.ftqPtr 639 ctrlBlock.io.memLdPcRead(i).offset := io.mem.issueLda(i).bits.uop.ftqOffset 640 } 641 642 io.mem.storePcRead.zipWithIndex.foreach { case (storePcRead, i) => 643 storePcRead := ctrlBlock.io.memStPcRead(i).data 644 ctrlBlock.io.memStPcRead(i).vld := io.mem.issueSta(i).valid 645 ctrlBlock.io.memStPcRead(i).ptr := io.mem.issueSta(i).bits.uop.ftqPtr 646 ctrlBlock.io.memStPcRead(i).offset := io.mem.issueSta(i).bits.uop.ftqOffset 647 } 648 649 io.mem.hyuPcRead.zipWithIndex.foreach( { case (hyuPcRead, i) => 650 hyuPcRead := ctrlBlock.io.memHyPcRead(i).data 651 ctrlBlock.io.memHyPcRead(i).vld := io.mem.issueHylda(i).valid 652 ctrlBlock.io.memHyPcRead(i).ptr := io.mem.issueHylda(i).bits.uop.ftqPtr 653 ctrlBlock.io.memHyPcRead(i).offset := io.mem.issueHylda(i).bits.uop.ftqOffset 654 }) 655 656 ctrlBlock.io.robio.robHeadLsIssue := io.mem.issueUops.map(deq => deq.fire && deq.bits.uop.robIdx === ctrlBlock.io.robio.robDeqPtr).reduce(_ || _) 657 658 // mem io 659 io.mem.lsqEnqIO <> memScheduler.io.memIO.get.lsqEnqIO 660 io.mem.robLsqIO <> ctrlBlock.io.robio.lsq 661 662 io.frontendSfence := fenceio.sfence 663 io.frontendTlbCsr := csrio.tlb 664 io.frontendCsrCtrl := csrio.customCtrl 665 666 io.tlb <> csrio.tlb 667 668 io.csrCustomCtrl := csrio.customCtrl 669 670 io.toTop.cpuHalted := false.B // TODO: implement cpu halt 671 672 io.debugTopDown.fromRob := ctrlBlock.io.debugTopDown.fromRob 673 ctrlBlock.io.debugTopDown.fromCore := io.debugTopDown.fromCore 674 675 io.debugRolling := ctrlBlock.io.debugRolling 676 677 if(backendParams.debugEn) { 678 dontTouch(memScheduler.io) 679 dontTouch(dataPath.io.toMemExu) 680 dontTouch(wbDataPath.io.fromMemExu) 681 } 682} 683 684class BackendMemIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 685 // Since fast load replay always use load unit 0, Backend flips two load port to avoid conflicts 686 val flippedLda = true 687 // params alias 688 private val LoadQueueSize = VirtualLoadQueueSize 689 // In/Out // Todo: split it into one-direction bundle 690 val lsqEnqIO = Flipped(new LsqEnqIO) 691 val robLsqIO = new RobLsqIO 692 val ldaIqFeedback = Vec(params.LduCnt, Flipped(new MemRSFeedbackIO)) 693 val staIqFeedback = Vec(params.StaCnt, Flipped(new MemRSFeedbackIO)) 694 val hyuIqFeedback = Vec(params.HyuCnt, Flipped(new MemRSFeedbackIO)) 695 val vstuIqFeedback = Flipped(Vec(params.VstuCnt, new MemRSFeedbackIO(isVector = true))) 696 val vlduIqFeedback = Flipped(Vec(params.VlduCnt, new MemRSFeedbackIO(isVector = true))) 697 val ldCancel = Vec(params.LdExuCnt, Flipped(new LoadCancelIO)) 698 val wakeup = Vec(params.LdExuCnt, Flipped(Valid(new DynInst))) 699 val loadPcRead = Vec(params.LduCnt, Output(UInt(VAddrBits.W))) 700 val storePcRead = Vec(params.StaCnt, Output(UInt(VAddrBits.W))) 701 val hyuPcRead = Vec(params.HyuCnt, Output(UInt(VAddrBits.W))) 702 // Input 703 val writebackLda = Vec(params.LduCnt, Flipped(DecoupledIO(new MemExuOutput))) 704 val writebackSta = Vec(params.StaCnt, Flipped(DecoupledIO(new MemExuOutput))) 705 val writebackStd = Vec(params.StdCnt, Flipped(DecoupledIO(new MemExuOutput))) 706 val writebackHyuLda = Vec(params.HyuCnt, Flipped(DecoupledIO(new MemExuOutput))) 707 val writebackHyuSta = Vec(params.HyuCnt, Flipped(DecoupledIO(new MemExuOutput))) 708 val writebackVldu = Vec(params.VlduCnt, Flipped(DecoupledIO(new MemExuOutput(true)))) 709 710 val s3_delayed_load_error = Input(Vec(LoadPipelineWidth, Bool())) 711 val stIn = Input(Vec(params.StaExuCnt, ValidIO(new DynInst()))) 712 val memoryViolation = Flipped(ValidIO(new Redirect)) 713 val exceptionAddr = Input(new Bundle { 714 val vaddr = UInt(VAddrBits.W) 715 val gpaddr = UInt(GPAddrBits.W) 716 }) 717 val sqDeq = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) 718 val lqDeq = Input(UInt(log2Up(CommitWidth + 1).W)) 719 val sqDeqPtr = Input(new SqPtr) 720 val lqDeqPtr = Input(new LqPtr) 721 722 val lqCancelCnt = Input(UInt(log2Up(VirtualLoadQueueSize + 1).W)) 723 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 724 725 val lqCanAccept = Input(Bool()) 726 val sqCanAccept = Input(Bool()) 727 728 val otherFastWakeup = Flipped(Vec(params.LduCnt + params.HyuCnt, ValidIO(new DynInst))) 729 val stIssuePtr = Input(new SqPtr()) 730 731 val csrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 732 733 val debugLS = Flipped(Output(new DebugLSIO)) 734 735 val lsTopdownInfo = Vec(params.LduCnt + params.HyuCnt, Flipped(Output(new LsTopdownInfo))) 736 // Output 737 val redirect = ValidIO(new Redirect) // rob flush MemBlock 738 val issueLda = MixedVec(Seq.fill(params.LduCnt)(DecoupledIO(new MemExuInput()))) 739 val issueSta = MixedVec(Seq.fill(params.StaCnt)(DecoupledIO(new MemExuInput()))) 740 val issueStd = MixedVec(Seq.fill(params.StdCnt)(DecoupledIO(new MemExuInput()))) 741 val issueHylda = MixedVec(Seq.fill(params.HyuCnt)(DecoupledIO(new MemExuInput()))) 742 val issueHysta = MixedVec(Seq.fill(params.HyuCnt)(DecoupledIO(new MemExuInput()))) 743 val issueVldu = MixedVec(Seq.fill(params.VlduCnt)(DecoupledIO(new MemExuInput(true)))) 744 745 val loadFastMatch = Vec(params.LduCnt, Output(UInt(params.LduCnt.W))) 746 val loadFastImm = Vec(params.LduCnt, Output(UInt(12.W))) // Imm_I 747 748 val tlbCsr = Output(new TlbCsrBundle) 749 val csrCtrl = Output(new CustomCSRCtrlIO) 750 val sfence = Output(new SfenceBundle) 751 val isStoreException = Output(Bool()) 752 val isVlsException = Output(Bool()) 753 754 // ATTENTION: The issue ports' sequence order should be the same as IQs' deq config 755 private [backend] def issueUops: Seq[DecoupledIO[MemExuInput]] = { 756 issueSta ++ 757 issueHylda ++ issueHysta ++ 758 issueLda ++ 759 issueVldu ++ 760 issueStd 761 }.toSeq 762 763 // ATTENTION: The writeback ports' sequence order should be the same as IQs' deq config 764 private [backend] def writeBack: Seq[DecoupledIO[MemExuOutput]] = { 765 writebackSta ++ 766 writebackHyuLda ++ writebackHyuSta ++ 767 writebackLda ++ 768 writebackVldu ++ 769 writebackStd 770 } 771} 772 773class BackendIO(implicit p: Parameters, params: BackendParams) extends XSBundle with HasSoCParameter { 774 val fromTop = new Bundle { 775 val hartId = Input(UInt(hartIdLen.W)) 776 val externalInterrupt = new ExternalInterruptIO 777 val setIpNumValidVec2 = Input(UInt(SetIpNumValidSize.W)) 778 val setIpNum = Input(UInt(log2Up(NumIRSrc).W)) 779 } 780 781 val toTop = new Bundle { 782 val cpuHalted = Output(Bool()) 783 } 784 785 val fenceio = new FenceIO 786 // Todo: merge these bundles into BackendFrontendIO 787 val frontend = Flipped(new FrontendToCtrlIO) 788 val frontendSfence = Output(new SfenceBundle) 789 val frontendCsrCtrl = Output(new CustomCSRCtrlIO) 790 val frontendTlbCsr = Output(new TlbCsrBundle) 791 // distributed csr write 792 val frontendCsrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 793 794 val mem = new BackendMemIO 795 796 val perf = Input(new PerfCounterIO) 797 798 val tlb = Output(new TlbCsrBundle) 799 800 val csrCustomCtrl = Output(new CustomCSRCtrlIO) 801 802 val debugTopDown = new Bundle { 803 val fromRob = new RobCoreTopDownIO 804 val fromCore = new CoreDispatchTopDownIO 805 } 806 val debugRolling = new RobDebugRollingIO 807} 808