1package xiangshan.backend 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import utility.ZeroExt 8import xiangshan._ 9import xiangshan.backend.Bundles.{DynInst, IssueQueueIQWakeUpBundle, MemExuInput, MemExuOutput} 10import xiangshan.backend.datapath.DataConfig.{IntData, VecData} 11import xiangshan.backend.datapath.RdConfig.{IntRD, VfRD} 12import xiangshan.backend.datapath.WbConfig._ 13import xiangshan.backend.datapath._ 14import xiangshan.backend.exu.ExuBlock 15import xiangshan.backend.fu.vector.Bundles.{VConfig, VType} 16import xiangshan.backend.fu.{FenceIO, FenceToSbuffer, FuConfig, PerfCounterIO} 17import xiangshan.backend.issue.{CancelNetwork, Scheduler} 18import xiangshan.backend.rob.RobLsqIO 19import xiangshan.frontend.{FtqPtr, FtqRead} 20import xiangshan.mem.{LqPtr, LsqEnqIO, SqPtr} 21 22class Backend(val params: BackendParams)(implicit p: Parameters) extends LazyModule 23 with HasXSParameter { 24 25 /* Only update the idx in mem-scheduler here 26 * Idx in other schedulers can be updated the same way if needed 27 * 28 * Also note that we filter out the 'stData issue-queues' when counting 29 */ 30 for ((ibp, idx) <- params.memSchdParams.get.issueBlockParams.filter(iq => iq.StdCnt == 0).zipWithIndex) { 31 ibp.updateIdx(idx) 32 } 33 34 println(params.iqWakeUpParams) 35 36 for ((schdCfg, i) <- params.allSchdParams.zipWithIndex) { 37 schdCfg.bindBackendParam(params) 38 } 39 40 for ((iqCfg, i) <- params.allIssueParams.zipWithIndex) { 41 iqCfg.bindBackendParam(params) 42 } 43 44 for ((exuCfg, i) <- params.allExuParams.zipWithIndex) { 45 exuCfg.updateIQWakeUpConfigs(params.iqWakeUpParams) 46 exuCfg.updateExuIdx(i) 47 exuCfg.bindBackendParam(params) 48 } 49 50 println("[Backend] ExuConfigs:") 51 for (exuCfg <- params.allExuParams) { 52 val fuConfigs = exuCfg.fuConfigs 53 val wbPortConfigs = exuCfg.wbPortConfigs 54 val immType = exuCfg.immType 55 56 println("[Backend] " + 57 s"${exuCfg.name}: " + 58 s"${fuConfigs.map(_.name).mkString("fu(s): {", ",", "}")}, " + 59 s"${wbPortConfigs.mkString("wb: {", ",", "}")}, " + 60 s"${immType.map(SelImm.mkString(_)).mkString("imm: {", ",", "}")}, " + 61 s"latMax(${exuCfg.latencyValMax}), ${exuCfg.fuLatancySet.mkString("lat: {", ",", "}")}, " 62 ) 63 require( 64 wbPortConfigs.collectFirst { case x: IntWB => x }.nonEmpty == 65 fuConfigs.map(_.writeIntRf).reduce(_ || _), 66 "int wb port has no priority" 67 ) 68 require( 69 wbPortConfigs.collectFirst { case x: VfWB => x }.nonEmpty == 70 fuConfigs.map(x => x.writeFpRf || x.writeVecRf).reduce(_ || _), 71 "vec wb port has no priority" 72 ) 73 } 74 75 println(s"[Backend] all fu configs") 76 for (cfg <- FuConfig.allConfigs) { 77 println(s"[Backend] $cfg") 78 } 79 80 println(s"[Backend] Int RdConfigs: ExuName(Priority)") 81 for ((port, seq) <- params.getRdPortParams(IntData())) { 82 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 83 } 84 85 println(s"[Backend] Int WbConfigs: ExuName(Priority)") 86 for ((port, seq) <- params.getWbPortParams(IntData())) { 87 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 88 } 89 90 println(s"[Backend] Vf RdConfigs: ExuName(Priority)") 91 for ((port, seq) <- params.getRdPortParams(VecData())) { 92 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 93 } 94 95 println(s"[Backend] Vf WbConfigs: ExuName(Priority)") 96 for ((port, seq) <- params.getWbPortParams(VecData())) { 97 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 98 } 99 100 val ctrlBlock = LazyModule(new CtrlBlock(params)) 101 val intScheduler = params.intSchdParams.map(x => LazyModule(new Scheduler(x))) 102 val vfScheduler = params.vfSchdParams.map(x => LazyModule(new Scheduler(x))) 103 val memScheduler = params.memSchdParams.map(x => LazyModule(new Scheduler(x))) 104 val cancelNetwork = LazyModule(new CancelNetwork(params)) 105 val dataPath = LazyModule(new DataPath(params)) 106 val intExuBlock = params.intSchdParams.map(x => LazyModule(new ExuBlock(x))) 107 val vfExuBlock = params.vfSchdParams.map(x => LazyModule(new ExuBlock(x))) 108 val wbFuBusyTable = LazyModule(new WbFuBusyTable(params)) 109 110 lazy val module = new BackendImp(this) 111} 112 113class BackendImp(override val wrapper: Backend)(implicit p: Parameters) extends LazyModuleImp(wrapper) 114 with HasXSParameter { 115 implicit private val params = wrapper.params 116 val io = IO(new BackendIO()(p, wrapper.params)) 117 118 private val ctrlBlock = wrapper.ctrlBlock.module 119 private val intScheduler = wrapper.intScheduler.get.module 120 private val vfScheduler = wrapper.vfScheduler.get.module 121 private val memScheduler = wrapper.memScheduler.get.module 122 private val cancelNetwork = wrapper.cancelNetwork.module 123 private val dataPath = wrapper.dataPath.module 124 private val intExuBlock = wrapper.intExuBlock.get.module 125 private val vfExuBlock = wrapper.vfExuBlock.get.module 126 private val bypassNetwork = Module(new BypassNetwork) 127 private val wbDataPath = Module(new WbDataPath(params)) 128 private val wbFuBusyTable = wrapper.wbFuBusyTable.module 129 130 private val iqWakeUpMappedBundle: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = ( 131 intScheduler.io.toSchedulers.wakeupVec ++ 132 vfScheduler.io.toSchedulers.wakeupVec ++ 133 memScheduler.io.toSchedulers.wakeupVec 134 ).map(x => (x.bits.exuIdx, x)).toMap 135 136 println(s"[Backend] iq wake up keys: ${iqWakeUpMappedBundle.keys}") 137 138 wbFuBusyTable.io.in.intSchdBusyTable := intScheduler.io.wbFuBusyTable 139 wbFuBusyTable.io.in.vfSchdBusyTable := vfScheduler.io.wbFuBusyTable 140 wbFuBusyTable.io.in.memSchdBusyTable := memScheduler.io.wbFuBusyTable 141 intScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.intRespRead 142 vfScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.vfRespRead 143 memScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.memRespRead 144 dataPath.io.wbConfictRead := wbFuBusyTable.io.out.wbConflictRead 145 146 wbDataPath.io.fromIntExu.flatten.filter(x => x.bits.params.writeIntRf) 147 148 private val vconfig = dataPath.io.vconfigReadPort.data 149 private val og1CancelVec: Vec[Bool] = dataPath.io.og1CancelVec 150 private val og0CancelVecFromDataPath: Vec[Bool] = dataPath.io.og0CancelVec 151 private val og0CancelVecFromCancelNet: Vec[Bool] = cancelNetwork.io.out.og0CancelVec 152 private val og0CancelVec: Vec[Bool] = VecInit(og0CancelVecFromDataPath.zip(og0CancelVecFromCancelNet).map(x => x._1 | x._2)) 153 154 ctrlBlock.io.fromTop.hartId := io.fromTop.hartId 155 ctrlBlock.io.frontend <> io.frontend 156 ctrlBlock.io.fromWB.wbData <> wbDataPath.io.toCtrlBlock.writeback 157 ctrlBlock.io.fromMem.stIn <> io.mem.stIn 158 ctrlBlock.io.fromMem.violation <> io.mem.memoryViolation 159 ctrlBlock.io.csrCtrl <> intExuBlock.io.csrio.get.customCtrl 160 ctrlBlock.io.robio.csr.intrBitSet := intExuBlock.io.csrio.get.interrupt 161 ctrlBlock.io.robio.csr.trapTarget := intExuBlock.io.csrio.get.trapTarget 162 ctrlBlock.io.robio.csr.isXRet := intExuBlock.io.csrio.get.isXRet 163 ctrlBlock.io.robio.csr.wfiEvent := intExuBlock.io.csrio.get.wfi_event 164 ctrlBlock.io.robio.lsq <> io.mem.robLsqIO 165 ctrlBlock.io.fromDataPath.vtype := vconfig(7, 0).asTypeOf(new VType) 166 167 intScheduler.io.fromTop.hartId := io.fromTop.hartId 168 intScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 169 intScheduler.io.fromCtrlBlock.pcVec := ctrlBlock.io.toIssueBlock.pcVec 170 intScheduler.io.fromCtrlBlock.targetVec := ctrlBlock.io.toIssueBlock.targetVec 171 intScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 172 intScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.intUops 173 intScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 174 intScheduler.io.vfWriteBack := 0.U.asTypeOf(intScheduler.io.vfWriteBack) 175 intScheduler.io.fromDataPath.resp := dataPath.io.toIntIQ 176 intScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 177 intScheduler.io.fromDataPath.og0Cancel := og0CancelVec 178 intScheduler.io.fromDataPath.og1Cancel := og1CancelVec 179 180 memScheduler.io.fromTop.hartId := io.fromTop.hartId 181 memScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 182 memScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 183 memScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.memUops 184 memScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 185 memScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 186 memScheduler.io.fromMem.get.scommit := io.mem.sqDeq 187 memScheduler.io.fromMem.get.lcommit := io.mem.lqDeq 188 memScheduler.io.fromMem.get.sqCancelCnt := io.mem.sqCancelCnt 189 memScheduler.io.fromMem.get.lqCancelCnt := io.mem.lqCancelCnt 190 memScheduler.io.fromMem.get.stIssuePtr := io.mem.stIssuePtr 191 memScheduler.io.fromMem.get.memWaitUpdateReq.staIssue.zip(io.mem.stIn).foreach { case (sink, source) => 192 sink.valid := source.valid 193 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 194 sink.bits.uop.robIdx := source.bits.robIdx 195 } 196 memScheduler.io.fromDataPath.resp := dataPath.io.toMemIQ 197 memScheduler.io.fromMem.get.ldaFeedback := io.mem.ldaIqFeedback 198 memScheduler.io.fromMem.get.staFeedback := io.mem.staIqFeedback 199 memScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 200 memScheduler.io.fromDataPath.og0Cancel := og0CancelVec 201 memScheduler.io.fromDataPath.og1Cancel := og1CancelVec 202 203 vfScheduler.io.fromTop.hartId := io.fromTop.hartId 204 vfScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 205 vfScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 206 vfScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.vfUops 207 vfScheduler.io.intWriteBack := 0.U.asTypeOf(vfScheduler.io.intWriteBack) 208 vfScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 209 vfScheduler.io.fromDataPath.resp := dataPath.io.toVfIQ 210 vfScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 211 vfScheduler.io.fromDataPath.og0Cancel := og0CancelVec 212 vfScheduler.io.fromDataPath.og1Cancel := og1CancelVec 213 214 cancelNetwork.io.in.int <> intScheduler.io.toDataPath 215 cancelNetwork.io.in.vf <> vfScheduler.io.toDataPath 216 cancelNetwork.io.in.mem <> memScheduler.io.toDataPath 217 cancelNetwork.io.in.og0CancelVec := og0CancelVecFromDataPath 218 cancelNetwork.io.in.og1CancelVec := og1CancelVec 219 intScheduler.io.fromCancelNetwork <> cancelNetwork.io.out.int 220 vfScheduler.io.fromCancelNetwork <> cancelNetwork.io.out.vf 221 memScheduler.io.fromCancelNetwork <> cancelNetwork.io.out.mem 222 223 dataPath.io.flush := ctrlBlock.io.toDataPath.flush 224 dataPath.io.vconfigReadPort.addr := ctrlBlock.io.toDataPath.vtypeAddr 225 226 dataPath.io.fromIntIQ <> intScheduler.io.toDataPathAfterDelay 227 dataPath.io.fromVfIQ <> vfScheduler.io.toDataPathAfterDelay 228 dataPath.io.fromMemIQ <> memScheduler.io.toDataPathAfterDelay 229 230 println(s"[Backend] wbDataPath.io.toIntPreg: ${wbDataPath.io.toIntPreg.size}, dataPath.io.fromIntWb: ${dataPath.io.fromIntWb.size}") 231 println(s"[Backend] wbDataPath.io.toVfPreg: ${wbDataPath.io.toVfPreg.size}, dataPath.io.fromFpWb: ${dataPath.io.fromVfWb.size}") 232 dataPath.io.fromIntWb := wbDataPath.io.toIntPreg 233 dataPath.io.fromVfWb := wbDataPath.io.toVfPreg 234 dataPath.io.debugIntRat := ctrlBlock.io.debug_int_rat 235 dataPath.io.debugFpRat := ctrlBlock.io.debug_fp_rat 236 dataPath.io.debugVecRat := ctrlBlock.io.debug_vec_rat 237 dataPath.io.debugVconfigRat := ctrlBlock.io.debug_vconfig_rat 238 239 bypassNetwork.io.fromDataPath.int <> dataPath.io.toIntExu 240 bypassNetwork.io.fromDataPath.vf <> dataPath.io.toFpExu 241 bypassNetwork.io.fromDataPath.mem <> dataPath.io.toMemExu 242 bypassNetwork.io.fromExus.connectExuOutput(_.int)(intExuBlock.io.out) 243 bypassNetwork.io.fromExus.connectExuOutput(_.vf)(vfExuBlock.io.out) 244 bypassNetwork.io.fromExus.mem.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 245 sink.valid := source.valid 246 sink.bits.pdest := source.bits.uop.pdest 247 sink.bits.data := source.bits.data 248 } 249 250 intExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 251 for (i <- 0 until intExuBlock.io.in.length) { 252 for (j <- 0 until intExuBlock.io.in(i).length) { 253 NewPipelineConnect( 254 bypassNetwork.io.toExus.int(i)(j), intExuBlock.io.in(i)(j), intExuBlock.io.in(i)(j).fire, 255 Mux( 256 bypassNetwork.io.toExus.int(i)(j).fire, 257 bypassNetwork.io.toExus.int(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush), 258 intExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 259 ) 260 ) 261 } 262 } 263 264 private val csrio = intExuBlock.io.csrio.get 265 csrio.hartId := io.fromTop.hartId 266 csrio.perf.retiredInstr <> ctrlBlock.io.robio.csr.perfinfo.retiredInstr 267 csrio.perf.ctrlInfo <> ctrlBlock.io.perfInfo.ctrlInfo 268 csrio.perf.perfEventsCtrl <> ctrlBlock.getPerf 269 csrio.fpu.fflags := ctrlBlock.io.robio.csr.fflags 270 csrio.fpu.isIllegal := false.B // Todo: remove it 271 csrio.fpu.dirty_fs := ctrlBlock.io.robio.csr.dirty_fs 272 csrio.vpu <> 0.U.asTypeOf(csrio.vpu) // Todo 273 274 val debugVconfig = dataPath.io.debugVconfig.asTypeOf(new VConfig) 275 val debugVtype = VType.toVtypeStruct(debugVconfig.vtype).asUInt 276 val debugVl = debugVconfig.vl 277 csrio.vpu.set_vxsat := ctrlBlock.io.robio.csr.vxsat 278 csrio.vpu.set_vstart.valid := ctrlBlock.io.robio.csr.vcsrFlag 279 csrio.vpu.set_vstart.bits := 0.U 280 csrio.vpu.set_vtype.valid := ctrlBlock.io.robio.csr.vcsrFlag 281 csrio.vpu.set_vtype.bits := ZeroExt(debugVtype, XLEN) 282 csrio.vpu.set_vl.valid := ctrlBlock.io.robio.csr.vcsrFlag 283 csrio.vpu.set_vl.bits := ZeroExt(debugVl, XLEN) 284 csrio.exception := ctrlBlock.io.robio.exception 285 csrio.memExceptionVAddr := io.mem.exceptionVAddr 286 csrio.externalInterrupt := io.fromTop.externalInterrupt 287 csrio.distributedUpdate(0) := io.mem.csrDistributedUpdate 288 csrio.distributedUpdate(1) := io.frontendCsrDistributedUpdate 289 csrio.perf <> io.perf 290 private val fenceio = intExuBlock.io.fenceio.get 291 fenceio.disableSfence := csrio.disableSfence 292 io.fenceio <> fenceio 293 294 vfExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 295 for (i <- 0 until vfExuBlock.io.in.size) { 296 for (j <- 0 until vfExuBlock.io.in(i).size) { 297 NewPipelineConnect( 298 bypassNetwork.io.toExus.vf(i)(j), vfExuBlock.io.in(i)(j), vfExuBlock.io.in(i)(j).fire, 299 Mux( 300 bypassNetwork.io.toExus.vf(i)(j).fire, 301 bypassNetwork.io.toExus.vf(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush), 302 vfExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 303 ) 304 ) 305 } 306 } 307 vfExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 308 309 wbDataPath.io.flush := ctrlBlock.io.redirect 310 wbDataPath.io.fromTop.hartId := io.fromTop.hartId 311 wbDataPath.io.fromIntExu <> intExuBlock.io.out 312 wbDataPath.io.fromVfExu <> vfExuBlock.io.out 313 wbDataPath.io.fromMemExu.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 314 sink.valid := source.valid 315 source.ready := sink.ready 316 sink.bits.data := source.bits.data 317 sink.bits.pdest := source.bits.uop.pdest 318 sink.bits.robIdx := source.bits.uop.robIdx 319 sink.bits.intWen.foreach(_ := source.bits.uop.rfWen) 320 sink.bits.fpWen.foreach(_ := source.bits.uop.fpWen) 321 sink.bits.vecWen.foreach(_ := source.bits.uop.vecWen) 322 sink.bits.exceptionVec.foreach(_ := source.bits.uop.exceptionVec) 323 sink.bits.flushPipe.foreach(_ := source.bits.uop.flushPipe) 324 sink.bits.replay.foreach(_ := source.bits.uop.replayInst) 325 sink.bits.debug := source.bits.debug 326 sink.bits.debugInfo := 0.U.asTypeOf(sink.bits.debugInfo) 327 sink.bits.lqIdx.foreach(_ := source.bits.uop.lqIdx) 328 sink.bits.sqIdx.foreach(_ := source.bits.uop.sqIdx) 329 sink.bits.ftqIdx.foreach(_ := source.bits.uop.ftqPtr) 330 sink.bits.ftqOffset.foreach(_ := source.bits.uop.ftqOffset) 331 } 332 333 // to mem 334 private val toMem = Wire(bypassNetwork.io.toExus.mem.cloneType) 335 for (i <- toMem.indices) { 336 for (j <- toMem(i).indices) { 337 NewPipelineConnect( 338 bypassNetwork.io.toExus.mem(i)(j), toMem(i)(j), toMem(i)(j).fire, 339 Mux( 340 bypassNetwork.io.toExus.mem(i)(j).fire, 341 bypassNetwork.io.toExus.mem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush), 342 toMem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 343 ) 344 ) 345 } 346 } 347 348 io.mem.redirect := ctrlBlock.io.redirect 349 io.mem.issueUops.zip(toMem.flatten).foreach { case (sink, source) => 350 sink.valid := source.valid 351 source.ready := sink.ready 352 sink.bits.iqIdx := source.bits.iqIdx 353 sink.bits.isFirstIssue := source.bits.isFirstIssue 354 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 355 sink.bits.src := 0.U.asTypeOf(sink.bits.src) 356 sink.bits.src.zip(source.bits.src).foreach { case (l, r) => l := r} 357 sink.bits.uop.fuType := source.bits.fuType 358 sink.bits.uop.fuOpType := source.bits.fuOpType 359 sink.bits.uop.imm := source.bits.imm 360 sink.bits.uop.robIdx := source.bits.robIdx 361 sink.bits.uop.pdest := source.bits.pdest 362 sink.bits.uop.rfWen := source.bits.rfWen.getOrElse(false.B) 363 sink.bits.uop.fpWen := source.bits.fpWen.getOrElse(false.B) 364 sink.bits.uop.vecWen := source.bits.vecWen.getOrElse(false.B) 365 sink.bits.uop.flushPipe := source.bits.flushPipe.getOrElse(false.B) 366 sink.bits.uop.pc := source.bits.pc.getOrElse(0.U) 367 sink.bits.uop.lqIdx := source.bits.lqIdx.getOrElse(0.U.asTypeOf(new LqPtr)) 368 sink.bits.uop.sqIdx := source.bits.sqIdx.getOrElse(0.U.asTypeOf(new SqPtr)) 369 sink.bits.uop.ftqPtr := source.bits.ftqIdx.getOrElse(0.U.asTypeOf(new FtqPtr)) 370 sink.bits.uop.ftqOffset := source.bits.ftqOffset.getOrElse(0.U) 371 } 372 io.mem.loadFastMatch := memScheduler.io.toMem.get.loadFastMatch.map(_.fastMatch) 373 io.mem.loadFastImm := memScheduler.io.toMem.get.loadFastMatch.map(_.fastImm) 374 io.mem.tlbCsr := csrio.tlb 375 io.mem.csrCtrl := csrio.customCtrl 376 io.mem.sfence := fenceio.sfence 377 io.mem.isStoreException := CommitType.lsInstIsStore(ctrlBlock.io.robio.exception.bits.commitType) 378 require(io.mem.loadPcRead.size == params.LduCnt) 379 io.mem.loadPcRead.zipWithIndex.foreach { case (loadPcRead, i) => 380 loadPcRead.data := ctrlBlock.io.memLdPcRead(i).data 381 ctrlBlock.io.memLdPcRead(i).ptr := loadPcRead.ptr 382 ctrlBlock.io.memLdPcRead(i).offset := loadPcRead.offset 383 } 384 // mem io 385 io.mem.lsqEnqIO <> memScheduler.io.memIO.get.lsqEnqIO 386 io.mem.robLsqIO <> ctrlBlock.io.robio.lsq 387 io.mem.toSbuffer <> fenceio.sbuffer 388 389 io.frontendSfence := fenceio.sfence 390 io.frontendTlbCsr := csrio.tlb 391 io.frontendCsrCtrl := csrio.customCtrl 392 393 io.tlb <> csrio.tlb 394 395 io.csrCustomCtrl := csrio.customCtrl 396 397 dontTouch(memScheduler.io) 398 dontTouch(io.mem) 399 dontTouch(dataPath.io.toMemExu) 400 dontTouch(wbDataPath.io.fromMemExu) 401} 402 403class BackendMemIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 404 // params alias 405 private val LoadQueueSize = VirtualLoadQueueSize 406 // In/Out // Todo: split it into one-direction bundle 407 val lsqEnqIO = Flipped(new LsqEnqIO) 408 val robLsqIO = new RobLsqIO 409 val toSbuffer = new FenceToSbuffer 410 val ldaIqFeedback = Vec(params.LduCnt, Flipped(new MemRSFeedbackIO)) 411 val staIqFeedback = Vec(params.StaCnt, Flipped(new MemRSFeedbackIO)) 412 val loadPcRead = Vec(params.LduCnt, Flipped(new FtqRead(UInt(VAddrBits.W)))) 413 414 // Input 415 val writeBack = MixedVec(Seq.fill(params.LduCnt + params.StaCnt * 2)(Flipped(DecoupledIO(new MemExuOutput()))) ++ Seq.fill(params.VlduCnt)(Flipped(DecoupledIO(new MemExuOutput(true))))) 416 417 val s3_delayed_load_error = Input(Vec(LoadPipelineWidth, Bool())) 418 val stIn = Input(Vec(params.StaCnt, ValidIO(new DynInst()))) 419 val memoryViolation = Flipped(ValidIO(new Redirect)) 420 val exceptionVAddr = Input(UInt(VAddrBits.W)) 421 val sqDeq = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) 422 val lqDeq = Input(UInt(log2Up(CommitWidth + 1).W)) 423 424 val lqCancelCnt = Input(UInt(log2Up(VirtualLoadQueueSize + 1).W)) 425 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 426 427 val otherFastWakeup = Flipped(Vec(params.LduCnt + 2 * params.StaCnt, ValidIO(new DynInst))) 428 val stIssuePtr = Input(new SqPtr()) 429 430 val csrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 431 432 // Output 433 val redirect = ValidIO(new Redirect) // rob flush MemBlock 434 val issueUops = MixedVec(Seq.fill(params.LduCnt + params.StaCnt * 2)(DecoupledIO(new MemExuInput())) ++ Seq.fill(params.VlduCnt)(DecoupledIO(new MemExuInput(true)))) 435 val loadFastMatch = Vec(params.LduCnt, Output(UInt(params.LduCnt.W))) 436 val loadFastImm = Vec(params.LduCnt, Output(UInt(12.W))) // Imm_I 437 438 val tlbCsr = Output(new TlbCsrBundle) 439 val csrCtrl = Output(new CustomCSRCtrlIO) 440 val sfence = Output(new SfenceBundle) 441 val isStoreException = Output(Bool()) 442} 443 444class BackendIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 445 val fromTop = new Bundle { 446 val hartId = Input(UInt(8.W)) 447 val externalInterrupt = new ExternalInterruptIO 448 } 449 450 val toTop = new Bundle { 451 val cpuHalted = Output(Bool()) 452 } 453 454 val fenceio = new FenceIO 455 // Todo: merge these bundles into BackendFrontendIO 456 val frontend = Flipped(new FrontendToCtrlIO) 457 val frontendSfence = Output(new SfenceBundle) 458 val frontendCsrCtrl = Output(new CustomCSRCtrlIO) 459 val frontendTlbCsr = Output(new TlbCsrBundle) 460 // distributed csr write 461 val frontendCsrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 462 463 val mem = new BackendMemIO 464 465 val perf = Input(new PerfCounterIO) 466 467 val tlb = Output(new TlbCsrBundle) 468 469 val csrCustomCtrl = Output(new CustomCSRCtrlIO) 470} 471