xref: /XiangShan/src/main/scala/xiangshan/backend/Backend.scala (revision 211d620b07edb797ba35b635d24fef4e7294bae2)
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package xiangshan.backend
18
19import org.chipsalliance.cde.config.Parameters
20import chisel3._
21import chisel3.util._
22import device.MsiInfoBundle
23import difftest._
24import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
25import system.HasSoCParameter
26import utility._
27import xiangshan._
28import xiangshan.backend.Bundles.{DynInst, IssueQueueIQWakeUpBundle, LoadShouldCancel, MemExuInput, MemExuOutput, VPUCtrlSignals}
29import xiangshan.backend.ctrlblock.{DebugLSIO, LsTopdownInfo}
30import xiangshan.backend.datapath.DataConfig.{IntData, VecData, FpData}
31import xiangshan.backend.datapath.RdConfig.{IntRD, VfRD}
32import xiangshan.backend.datapath.WbConfig._
33import xiangshan.backend.datapath.DataConfig._
34import xiangshan.backend.datapath._
35import xiangshan.backend.dispatch.CoreDispatchTopDownIO
36import xiangshan.backend.exu.ExuBlock
37import xiangshan.backend.fu.vector.Bundles.{VConfig, VType}
38import xiangshan.backend.fu.{FenceIO, FenceToSbuffer, FuConfig, FuType, PFEvent, PerfCounterIO}
39import xiangshan.backend.issue.EntryBundles._
40import xiangshan.backend.issue.{CancelNetwork, Scheduler, SchedulerArithImp, SchedulerImpBase, SchedulerMemImp}
41import xiangshan.backend.rob.{RobCoreTopDownIO, RobDebugRollingIO, RobLsqIO, RobPtr}
42import xiangshan.frontend.{FtqPtr, FtqRead, PreDecodeInfo}
43import xiangshan.mem.{LqPtr, LsqEnqIO, SqPtr}
44
45import scala.collection.mutable
46
47class Backend(val params: BackendParams)(implicit p: Parameters) extends LazyModule
48  with HasXSParameter {
49  override def shouldBeInlined: Boolean = false
50  val inner = LazyModule(new BackendInlined(params))
51  lazy val module = new BackendImp(this)
52}
53
54class BackendImp(wrapper: Backend)(implicit p: Parameters) extends LazyModuleImp(wrapper) {
55  val io = IO(new BackendIO()(p, wrapper.params))
56  io <> wrapper.inner.module.io
57  if (p(DebugOptionsKey).ResetGen) {
58    ResetGen(ResetGenNode(Seq(ModuleNode(wrapper.inner.module))), reset, sim = false)
59  }
60}
61
62class BackendInlined(val params: BackendParams)(implicit p: Parameters) extends LazyModule
63  with HasXSParameter {
64
65  override def shouldBeInlined: Boolean = true
66
67  // check read & write port config
68  params.configChecks
69
70  /* Only update the idx in mem-scheduler here
71   * Idx in other schedulers can be updated the same way if needed
72   *
73   * Also note that we filter out the 'stData issue-queues' when counting
74   */
75  for ((ibp, idx) <- params.memSchdParams.get.issueBlockParams.filter(iq => iq.StdCnt == 0).zipWithIndex) {
76    ibp.updateIdx(idx)
77  }
78
79  println(params.iqWakeUpParams)
80
81  for ((schdCfg, i) <- params.allSchdParams.zipWithIndex) {
82    schdCfg.bindBackendParam(params)
83  }
84
85  for ((iqCfg, i) <- params.allIssueParams.zipWithIndex) {
86    iqCfg.bindBackendParam(params)
87  }
88
89  for ((exuCfg, i) <- params.allExuParams.zipWithIndex) {
90    exuCfg.bindBackendParam(params)
91    exuCfg.updateIQWakeUpConfigs(params.iqWakeUpParams)
92    exuCfg.updateExuIdx(i)
93  }
94
95  println("[Backend] ExuConfigs:")
96  for (exuCfg <- params.allExuParams) {
97    val fuConfigs = exuCfg.fuConfigs
98    val wbPortConfigs = exuCfg.wbPortConfigs
99    val immType = exuCfg.immType
100
101    println("[Backend]   " +
102      s"${exuCfg.name}: " +
103      (if (exuCfg.fakeUnit) "fake, " else "") +
104      (if (exuCfg.hasLoadFu || exuCfg.hasHyldaFu) s"LdExuIdx(${backendParams.getLdExuIdx(exuCfg)})" else "") +
105      s"${fuConfigs.map(_.name).mkString("fu(s): {", ",", "}")}, " +
106      s"${wbPortConfigs.mkString("wb: {", ",", "}")}, " +
107      s"${immType.map(SelImm.mkString(_)).mkString("imm: {", ",", "}")}, " +
108      s"latMax(${exuCfg.latencyValMax}), ${exuCfg.fuLatancySet.mkString("lat: {", ",", "}")}, " +
109      s"srcReg(${exuCfg.numRegSrc})"
110    )
111    require(
112      wbPortConfigs.collectFirst { case x: IntWB => x }.nonEmpty ==
113        fuConfigs.map(_.writeIntRf).reduce(_ || _),
114      s"${exuCfg.name} int wb port has no priority"
115    )
116    require(
117      wbPortConfigs.collectFirst { case x: FpWB => x }.nonEmpty ==
118        fuConfigs.map(x => x.writeFpRf).reduce(_ || _),
119      s"${exuCfg.name} fp wb port has no priority"
120    )
121    require(
122      wbPortConfigs.collectFirst { case x: VfWB => x }.nonEmpty ==
123        fuConfigs.map(x => x.writeVecRf).reduce(_ || _),
124      s"${exuCfg.name} vec wb port has no priority"
125    )
126  }
127
128  println(s"[Backend] all fu configs")
129  for (cfg <- FuConfig.allConfigs) {
130    println(s"[Backend]   $cfg")
131  }
132
133  println(s"[Backend] Int RdConfigs: ExuName(Priority)")
134  for ((port, seq) <- params.getRdPortParams(IntData())) {
135    println(s"[Backend]   port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}")
136  }
137
138  println(s"[Backend] Int WbConfigs: ExuName(Priority)")
139  for ((port, seq) <- params.getWbPortParams(IntData())) {
140    println(s"[Backend]   port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}")
141  }
142
143  println(s"[Backend] Fp RdConfigs: ExuName(Priority)")
144  for ((port, seq) <- params.getRdPortParams(FpData())) {
145    println(s"[Backend]   port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}")
146  }
147
148  println(s"[Backend] Fp WbConfigs: ExuName(Priority)")
149  for ((port, seq) <- params.getWbPortParams(FpData())) {
150    println(s"[Backend]   port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}")
151  }
152
153  println(s"[Backend] Vf RdConfigs: ExuName(Priority)")
154  for ((port, seq) <- params.getRdPortParams(VecData())) {
155    println(s"[Backend]   port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}")
156  }
157
158  println(s"[Backend] Vf WbConfigs: ExuName(Priority)")
159  for ((port, seq) <- params.getWbPortParams(VecData())) {
160    println(s"[Backend]   port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}")
161  }
162
163  println(s"[Backend] Dispatch Configs:")
164  println(s"[Backend] Load IQ enq width(${params.numLoadDp}), Store IQ enq width(${params.numStoreDp})")
165  println(s"[Backend] Load DP width(${LSQLdEnqWidth}), Store DP width(${LSQStEnqWidth})")
166
167  params.updateCopyPdestInfo
168  println(s"[Backend] copyPdestInfo ${params.copyPdestInfo}")
169  params.allExuParams.map(_.copyNum)
170  val ctrlBlock = LazyModule(new CtrlBlock(params))
171  val pcTargetMem = LazyModule(new PcTargetMem(params))
172  val intScheduler = params.intSchdParams.map(x => LazyModule(new Scheduler(x)))
173  val fpScheduler = params.fpSchdParams.map(x => LazyModule(new Scheduler(x)))
174  val vfScheduler = params.vfSchdParams.map(x => LazyModule(new Scheduler(x)))
175  val memScheduler = params.memSchdParams.map(x => LazyModule(new Scheduler(x)))
176  val dataPath = LazyModule(new DataPath(params))
177  val intExuBlock = params.intSchdParams.map(x => LazyModule(new ExuBlock(x)))
178  val fpExuBlock = params.fpSchdParams.map(x => LazyModule(new ExuBlock(x)))
179  val vfExuBlock = params.vfSchdParams.map(x => LazyModule(new ExuBlock(x)))
180  val wbFuBusyTable = LazyModule(new WbFuBusyTable(params))
181
182  lazy val module = new BackendInlinedImp(this)
183}
184
185class BackendInlinedImp(override val wrapper: BackendInlined)(implicit p: Parameters) extends LazyModuleImp(wrapper)
186  with HasXSParameter
187  with HasPerfEvents
188  with HasCriticalErrors {
189  implicit private val params: BackendParams = wrapper.params
190
191  val io = IO(new BackendIO()(p, wrapper.params))
192
193  private val ctrlBlock = wrapper.ctrlBlock.module
194  private val pcTargetMem = wrapper.pcTargetMem.module
195  private val intScheduler: SchedulerImpBase = wrapper.intScheduler.get.module
196  private val fpScheduler = wrapper.fpScheduler.get.module
197  private val vfScheduler = wrapper.vfScheduler.get.module
198  private val memScheduler = wrapper.memScheduler.get.module
199  private val dataPath = wrapper.dataPath.module
200  private val intExuBlock = wrapper.intExuBlock.get.module
201  private val fpExuBlock = wrapper.fpExuBlock.get.module
202  private val vfExuBlock = wrapper.vfExuBlock.get.module
203  private val og2ForVector = Module(new Og2ForVector(params))
204  private val bypassNetwork = Module(new BypassNetwork)
205  private val wbDataPath = Module(new WbDataPath(params))
206  private val wbFuBusyTable = wrapper.wbFuBusyTable.module
207  private val vecExcpMod = Module(new VecExcpDataMergeModule)
208
209  private val iqWakeUpMappedBundle: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = (
210    intScheduler.io.toSchedulers.wakeupVec ++
211      fpScheduler.io.toSchedulers.wakeupVec ++
212      vfScheduler.io.toSchedulers.wakeupVec ++
213      memScheduler.io.toSchedulers.wakeupVec
214    ).map(x => (x.bits.exuIdx, x)).toMap
215
216  println(s"[Backend] iq wake up keys: ${iqWakeUpMappedBundle.keys}")
217
218  wbFuBusyTable.io.in.intSchdBusyTable := intScheduler.io.wbFuBusyTable
219  wbFuBusyTable.io.in.fpSchdBusyTable := fpScheduler.io.wbFuBusyTable
220  wbFuBusyTable.io.in.vfSchdBusyTable := vfScheduler.io.wbFuBusyTable
221  wbFuBusyTable.io.in.memSchdBusyTable := memScheduler.io.wbFuBusyTable
222  intScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.intRespRead
223  fpScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.fpRespRead
224  vfScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.vfRespRead
225  memScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.memRespRead
226  dataPath.io.wbConfictRead := wbFuBusyTable.io.out.wbConflictRead
227
228  private val og1Cancel = dataPath.io.og1Cancel
229  private val og0Cancel = dataPath.io.og0Cancel
230  private val vlFromIntIsZero = intExuBlock.io.vlIsZero.get
231  private val vlFromIntIsVlmax = intExuBlock.io.vlIsVlmax.get
232  private val vlFromVfIsZero = vfExuBlock.io.vlIsZero.get
233  private val vlFromVfIsVlmax = vfExuBlock.io.vlIsVlmax.get
234
235  ctrlBlock.io.intIQValidNumVec := intScheduler.io.intIQValidNumVec
236  ctrlBlock.io.fpIQValidNumVec := fpScheduler.io.fpIQValidNumVec
237  ctrlBlock.io.fromTop.hartId := io.fromTop.hartId
238  ctrlBlock.io.frontend <> io.frontend
239  ctrlBlock.io.fromCSR.toDecode := intExuBlock.io.csrToDecode.get
240  ctrlBlock.io.fromWB.wbData <> wbDataPath.io.toCtrlBlock.writeback
241  ctrlBlock.io.fromMem.stIn <> io.mem.stIn
242  ctrlBlock.io.fromMem.violation <> io.mem.memoryViolation
243  ctrlBlock.io.lqCanAccept := io.mem.lqCanAccept
244  ctrlBlock.io.sqCanAccept := io.mem.sqCanAccept
245  ctrlBlock.io.csrCtrl <> intExuBlock.io.csrio.get.customCtrl
246  ctrlBlock.io.robio.csr.intrBitSet := intExuBlock.io.csrio.get.interrupt
247  ctrlBlock.io.robio.csr.trapTarget := intExuBlock.io.csrio.get.trapTarget
248  ctrlBlock.io.robio.csr.isXRet := intExuBlock.io.csrio.get.isXRet
249  ctrlBlock.io.robio.csr.wfiEvent := intExuBlock.io.csrio.get.wfi_event
250  ctrlBlock.io.robio.lsq <> io.mem.robLsqIO
251  ctrlBlock.io.robio.lsTopdownInfo <> io.mem.lsTopdownInfo
252  ctrlBlock.io.robio.debug_ls <> io.mem.debugLS
253  ctrlBlock.io.debugEnqLsq.canAccept := io.mem.lsqEnqIO.canAccept
254  ctrlBlock.io.debugEnqLsq.resp := io.mem.lsqEnqIO.resp
255  ctrlBlock.io.debugEnqLsq.req := memScheduler.io.memIO.get.lsqEnqIO.req
256  ctrlBlock.io.debugEnqLsq.needAlloc := memScheduler.io.memIO.get.lsqEnqIO.needAlloc
257  ctrlBlock.io.debugEnqLsq.iqAccept := memScheduler.io.memIO.get.lsqEnqIO.iqAccept
258  ctrlBlock.io.fromVecExcpMod.busy := vecExcpMod.o.status.busy
259
260  intScheduler.io.fromTop.hartId := io.fromTop.hartId
261  intScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush
262  intScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs
263  intScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.intUops
264  intScheduler.io.intWriteBack := wbDataPath.io.toIntPreg
265  intScheduler.io.fpWriteBack := 0.U.asTypeOf(intScheduler.io.fpWriteBack)
266  intScheduler.io.vfWriteBack := 0.U.asTypeOf(intScheduler.io.vfWriteBack)
267  intScheduler.io.v0WriteBack := 0.U.asTypeOf(intScheduler.io.v0WriteBack)
268  intScheduler.io.vlWriteBack := 0.U.asTypeOf(intScheduler.io.vlWriteBack)
269  intScheduler.io.fromDataPath.resp := dataPath.io.toIntIQ
270  intScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) }
271  intScheduler.io.fromDataPath.og0Cancel := og0Cancel
272  intScheduler.io.fromDataPath.og1Cancel := og1Cancel
273  intScheduler.io.ldCancel := io.mem.ldCancel
274  intScheduler.io.fromDataPath.replaceRCIdx.get := dataPath.io.toWakeupQueueRCIdx.take(params.getIntExuRCWriteSize)
275  intScheduler.io.vlWriteBackInfo.vlFromIntIsZero := false.B
276  intScheduler.io.vlWriteBackInfo.vlFromIntIsVlmax := false.B
277  intScheduler.io.vlWriteBackInfo.vlFromVfIsZero := false.B
278  intScheduler.io.vlWriteBackInfo.vlFromVfIsVlmax := false.B
279
280  fpScheduler.io.fromTop.hartId := io.fromTop.hartId
281  fpScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush
282  fpScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs
283  fpScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.fpUops
284  fpScheduler.io.intWriteBack := 0.U.asTypeOf(fpScheduler.io.intWriteBack)
285  fpScheduler.io.fpWriteBack := wbDataPath.io.toFpPreg
286  fpScheduler.io.vfWriteBack := 0.U.asTypeOf(fpScheduler.io.vfWriteBack)
287  fpScheduler.io.v0WriteBack := 0.U.asTypeOf(fpScheduler.io.v0WriteBack)
288  fpScheduler.io.vlWriteBack := 0.U.asTypeOf(fpScheduler.io.vlWriteBack)
289  fpScheduler.io.fromDataPath.resp := dataPath.io.toFpIQ
290  fpScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) }
291  fpScheduler.io.fromDataPath.og0Cancel := og0Cancel
292  fpScheduler.io.fromDataPath.og1Cancel := og1Cancel
293  fpScheduler.io.ldCancel := io.mem.ldCancel
294  fpScheduler.io.vlWriteBackInfo.vlFromIntIsZero := false.B
295  fpScheduler.io.vlWriteBackInfo.vlFromIntIsVlmax := false.B
296  fpScheduler.io.vlWriteBackInfo.vlFromVfIsZero := false.B
297  fpScheduler.io.vlWriteBackInfo.vlFromVfIsVlmax := false.B
298
299  memScheduler.io.fromTop.hartId := io.fromTop.hartId
300  memScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush
301  memScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs
302  memScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.memUops
303  memScheduler.io.intWriteBack := wbDataPath.io.toIntPreg
304  memScheduler.io.fpWriteBack := wbDataPath.io.toFpPreg
305  memScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg
306  memScheduler.io.v0WriteBack := wbDataPath.io.toV0Preg
307  memScheduler.io.vlWriteBack := wbDataPath.io.toVlPreg
308  memScheduler.io.fromMem.get.scommit := io.mem.sqDeq
309  memScheduler.io.fromMem.get.lcommit := io.mem.lqDeq
310  memScheduler.io.fromMem.get.wakeup := io.mem.wakeup
311  memScheduler.io.fromMem.get.sqDeqPtr := io.mem.sqDeqPtr
312  memScheduler.io.fromMem.get.lqDeqPtr := io.mem.lqDeqPtr
313  memScheduler.io.fromMem.get.sqCancelCnt := io.mem.sqCancelCnt
314  memScheduler.io.fromMem.get.lqCancelCnt := io.mem.lqCancelCnt
315  memScheduler.io.fromMem.get.stIssuePtr := io.mem.stIssuePtr
316  require(memScheduler.io.fromMem.get.memWaitUpdateReq.robIdx.length == io.mem.stIn.length)
317  memScheduler.io.fromMem.get.memWaitUpdateReq.robIdx.zip(io.mem.stIn).foreach { case (sink, source) =>
318    sink.valid := source.valid
319    sink.bits  := source.bits.robIdx
320  }
321  memScheduler.io.fromMem.get.memWaitUpdateReq.sqIdx := DontCare // TODO
322  memScheduler.io.fromDataPath.resp := dataPath.io.toMemIQ
323  memScheduler.io.fromMem.get.ldaFeedback := io.mem.ldaIqFeedback
324  memScheduler.io.fromMem.get.staFeedback := io.mem.staIqFeedback
325  memScheduler.io.fromMem.get.hyuFeedback := io.mem.hyuIqFeedback
326  memScheduler.io.fromMem.get.vstuFeedback := io.mem.vstuIqFeedback
327  memScheduler.io.fromMem.get.vlduFeedback := io.mem.vlduIqFeedback
328  memScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) }
329  memScheduler.io.fromDataPath.og0Cancel := og0Cancel
330  memScheduler.io.fromDataPath.og1Cancel := og1Cancel
331  memScheduler.io.ldCancel := io.mem.ldCancel
332  memScheduler.io.fromDataPath.replaceRCIdx.get := dataPath.io.toWakeupQueueRCIdx.takeRight(params.getMemExuRCWriteSize)
333  memScheduler.io.vlWriteBackInfo.vlFromIntIsZero := vlFromIntIsZero
334  memScheduler.io.vlWriteBackInfo.vlFromIntIsVlmax := vlFromIntIsVlmax
335  memScheduler.io.vlWriteBackInfo.vlFromVfIsZero := vlFromVfIsZero
336  memScheduler.io.vlWriteBackInfo.vlFromVfIsVlmax := vlFromVfIsVlmax
337  memScheduler.io.fromOg2Resp.get := og2ForVector.io.toMemIQOg2Resp
338
339  vfScheduler.io.fromTop.hartId := io.fromTop.hartId
340  vfScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush
341  vfScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs
342  vfScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.vfUops
343  vfScheduler.io.intWriteBack := 0.U.asTypeOf(vfScheduler.io.intWriteBack)
344  vfScheduler.io.fpWriteBack := 0.U.asTypeOf(vfScheduler.io.fpWriteBack)
345  vfScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg
346  vfScheduler.io.v0WriteBack := wbDataPath.io.toV0Preg
347  vfScheduler.io.vlWriteBack := wbDataPath.io.toVlPreg
348  vfScheduler.io.fromDataPath.resp := dataPath.io.toVfIQ
349  vfScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) }
350  vfScheduler.io.fromDataPath.og0Cancel := og0Cancel
351  vfScheduler.io.fromDataPath.og1Cancel := og1Cancel
352  vfScheduler.io.ldCancel := io.mem.ldCancel
353  vfScheduler.io.vlWriteBackInfo.vlFromIntIsZero := vlFromIntIsZero
354  vfScheduler.io.vlWriteBackInfo.vlFromIntIsVlmax := vlFromIntIsVlmax
355  vfScheduler.io.vlWriteBackInfo.vlFromVfIsZero := vlFromVfIsZero
356  vfScheduler.io.vlWriteBackInfo.vlFromVfIsVlmax := vlFromVfIsVlmax
357  vfScheduler.io.fromOg2Resp.get := og2ForVector.io.toVfIQOg2Resp
358
359  dataPath.io.hartId := io.fromTop.hartId
360  dataPath.io.flush := ctrlBlock.io.toDataPath.flush
361
362  dataPath.io.fromIntIQ <> intScheduler.io.toDataPathAfterDelay
363  dataPath.io.fromFpIQ <> fpScheduler.io.toDataPathAfterDelay
364  dataPath.io.fromVfIQ <> vfScheduler.io.toDataPathAfterDelay
365  dataPath.io.fromMemIQ <> memScheduler.io.toDataPathAfterDelay
366
367  dataPath.io.ldCancel := io.mem.ldCancel
368
369  println(s"[Backend] wbDataPath.io.toIntPreg: ${wbDataPath.io.toIntPreg.size}, dataPath.io.fromIntWb: ${dataPath.io.fromIntWb.size}")
370  println(s"[Backend] wbDataPath.io.toVfPreg: ${wbDataPath.io.toVfPreg.size}, dataPath.io.fromFpWb: ${dataPath.io.fromVfWb.size}")
371  dataPath.io.fromIntWb := wbDataPath.io.toIntPreg
372  dataPath.io.fromFpWb := wbDataPath.io.toFpPreg
373  dataPath.io.fromVfWb := wbDataPath.io.toVfPreg
374  dataPath.io.fromV0Wb := wbDataPath.io.toV0Preg
375  dataPath.io.fromVlWb := wbDataPath.io.toVlPreg
376  dataPath.io.diffIntRat.foreach(_ := ctrlBlock.io.diff_int_rat.get)
377  dataPath.io.diffFpRat .foreach(_ := ctrlBlock.io.diff_fp_rat.get)
378  dataPath.io.diffVecRat.foreach(_ := ctrlBlock.io.diff_vec_rat.get)
379  dataPath.io.diffV0Rat .foreach(_ := ctrlBlock.io.diff_v0_rat.get)
380  dataPath.io.diffVlRat .foreach(_ := ctrlBlock.io.diff_vl_rat.get)
381  dataPath.io.fromBypassNetwork := bypassNetwork.io.toDataPath
382  dataPath.io.fromVecExcpMod.r := vecExcpMod.o.toVPRF.r
383  dataPath.io.fromVecExcpMod.w := vecExcpMod.o.toVPRF.w
384
385  og2ForVector.io.flush := ctrlBlock.io.toDataPath.flush
386  og2ForVector.io.ldCancel := io.mem.ldCancel
387  og2ForVector.io.fromOg1VfArith <> dataPath.io.toVecExu
388  og2ForVector.io.fromOg1VecMem.zip(dataPath.io.toMemExu.zip(params.memSchdParams.get.issueBlockParams).filter(_._2.needOg2Resp).map(_._1))
389    .foreach {
390      case (og1Mem, datapathMem) => og1Mem <> datapathMem
391    }
392  og2ForVector.io.fromOg1ImmInfo := dataPath.io.og1ImmInfo.zip(params.allExuParams).filter(_._2.needOg2).map(_._1)
393
394  println(s"[Backend] BypassNetwork OG1 Mem Size: ${bypassNetwork.io.fromDataPath.mem.zip(params.memSchdParams.get.issueBlockParams).filterNot(_._2.needOg2Resp).size}")
395  println(s"[Backend] BypassNetwork OG2 Mem Size: ${bypassNetwork.io.fromDataPath.mem.zip(params.memSchdParams.get.issueBlockParams).filter(_._2.needOg2Resp).size}")
396  println(s"[Backend] bypassNetwork.io.fromDataPath.mem: ${bypassNetwork.io.fromDataPath.mem.size}, dataPath.io.toMemExu: ${dataPath.io.toMemExu.size}")
397  bypassNetwork.io.fromDataPath.int <> dataPath.io.toIntExu
398  bypassNetwork.io.fromDataPath.fp <> dataPath.io.toFpExu
399  bypassNetwork.io.fromDataPath.vf <> og2ForVector.io.toVfArithExu
400  bypassNetwork.io.fromDataPath.mem.lazyZip(params.memSchdParams.get.issueBlockParams).lazyZip(dataPath.io.toMemExu).filterNot(_._2.needOg2Resp)
401    .map(x => (x._1, x._3)).foreach {
402      case (bypassMem, datapathMem) => bypassMem <> datapathMem
403    }
404  bypassNetwork.io.fromDataPath.mem.zip(params.memSchdParams.get.issueBlockParams).filter(_._2.needOg2Resp).map(_._1)
405    .zip(og2ForVector.io.toVecMemExu).foreach {
406      case (bypassMem, og2Mem) => bypassMem <> og2Mem
407    }
408  bypassNetwork.io.fromDataPath.immInfo := dataPath.io.og1ImmInfo
409  bypassNetwork.io.fromDataPath.immInfo.zip(params.allExuParams).filter(_._2.needOg2).map(_._1)
410    .zip(og2ForVector.io.toBypassNetworkImmInfo).foreach {
411      case (immInfo, og2ImmInfo) => immInfo := og2ImmInfo
412    }
413  bypassNetwork.io.fromDataPath.rcData := dataPath.io.toBypassNetworkRCData
414  bypassNetwork.io.fromExus.connectExuOutput(_.int)(intExuBlock.io.out)
415  bypassNetwork.io.fromExus.connectExuOutput(_.fp)(fpExuBlock.io.out)
416  bypassNetwork.io.fromExus.connectExuOutput(_.vf)(vfExuBlock.io.out)
417
418  require(bypassNetwork.io.fromExus.mem.flatten.size == io.mem.writeBack.size,
419    s"bypassNetwork.io.fromExus.mem.flatten.size(${bypassNetwork.io.fromExus.mem.flatten.size}: ${bypassNetwork.io.fromExus.mem.map(_.size)}, " +
420    s"io.mem.writeback(${io.mem.writeBack.size})"
421  )
422  bypassNetwork.io.fromExus.mem.flatten.zip(io.mem.writeBack).foreach { case (sink, source) =>
423    sink.valid := source.valid
424    sink.bits.intWen := source.bits.uop.rfWen && source.bits.isFromLoadUnit
425    sink.bits.pdest := source.bits.uop.pdest
426    sink.bits.data := source.bits.data
427  }
428
429
430  intExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush
431  for (i <- 0 until intExuBlock.io.in.length) {
432    for (j <- 0 until intExuBlock.io.in(i).length) {
433      val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.int(i)(j).bits.loadDependency, io.mem.ldCancel)
434      NewPipelineConnect(
435        bypassNetwork.io.toExus.int(i)(j), intExuBlock.io.in(i)(j), intExuBlock.io.in(i)(j).fire,
436        Mux(
437          bypassNetwork.io.toExus.int(i)(j).fire,
438          bypassNetwork.io.toExus.int(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel,
439          intExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush)
440        ),
441        Option("bypassNetwork2intExuBlock")
442      )
443    }
444  }
445
446  pcTargetMem.io.fromFrontendFtq := io.frontend.fromFtq
447  pcTargetMem.io.toDataPath <> dataPath.io.fromPcTargetMem
448
449  private val csrin = intExuBlock.io.csrin.get
450  csrin.hartId := io.fromTop.hartId
451  csrin.msiInfo.valid := RegNext(io.fromTop.msiInfo.valid)
452  csrin.msiInfo.bits := RegEnable(io.fromTop.msiInfo.bits, io.fromTop.msiInfo.valid)
453  csrin.clintTime.valid := RegNext(io.fromTop.clintTime.valid)
454  csrin.clintTime.bits := RegEnable(io.fromTop.clintTime.bits, io.fromTop.clintTime.valid)
455  csrin.trapInstInfo := ctrlBlock.io.toCSR.trapInstInfo
456  csrin.fromVecExcpMod.busy := vecExcpMod.o.status.busy
457
458  private val csrio = intExuBlock.io.csrio.get
459  csrio.hartId := io.fromTop.hartId
460  csrio.fpu.fflags := ctrlBlock.io.robio.csr.fflags
461  csrio.fpu.isIllegal := false.B // Todo: remove it
462  csrio.fpu.dirty_fs := ctrlBlock.io.robio.csr.dirty_fs
463  csrio.vpu <> WireDefault(0.U.asTypeOf(csrio.vpu)) // Todo
464
465  val fromIntExuVsetVType = intExuBlock.io.vtype.getOrElse(0.U.asTypeOf((Valid(new VType))))
466  val fromVfExuVsetVType = vfExuBlock.io.vtype.getOrElse(0.U.asTypeOf((Valid(new VType))))
467  val fromVsetVType = Mux(fromIntExuVsetVType.valid, fromIntExuVsetVType.bits, fromVfExuVsetVType.bits)
468  val vsetvlVType = RegEnable(fromVsetVType, 0.U.asTypeOf(new VType), fromIntExuVsetVType.valid || fromVfExuVsetVType.valid)
469  ctrlBlock.io.toDecode.vsetvlVType := vsetvlVType
470
471  val commitVType = ctrlBlock.io.robio.commitVType.vtype
472  val hasVsetvl = ctrlBlock.io.robio.commitVType.hasVsetvl
473  val vtype = VType.toVtypeStruct(Mux(hasVsetvl, vsetvlVType, commitVType.bits)).asUInt
474
475  // csr not store the value of vl, so when using difftest we assign the value of vl to debugVl
476  val debugVl_s0 = WireInit(UInt(VlData().dataWidth.W), 0.U)
477  val debugVl_s1 = WireInit(UInt(VlData().dataWidth.W), 0.U)
478  debugVl_s0 := dataPath.io.diffVl.getOrElse(0.U.asTypeOf(UInt(VlData().dataWidth.W)))
479  debugVl_s1 := RegNext(debugVl_s0)
480  csrio.vpu.set_vxsat := ctrlBlock.io.robio.csr.vxsat
481  csrio.vpu.set_vstart.valid := ctrlBlock.io.robio.csr.vstart.valid
482  csrio.vpu.set_vstart.bits := ctrlBlock.io.robio.csr.vstart.bits
483  ctrlBlock.io.toDecode.vstart := csrio.vpu.vstart
484  //Todo here need change design
485  csrio.vpu.set_vtype.valid := commitVType.valid
486  csrio.vpu.set_vtype.bits := ZeroExt(vtype, XLEN)
487  csrio.vpu.vl := ZeroExt(debugVl_s1, XLEN)
488  csrio.vpu.dirty_vs := ctrlBlock.io.robio.csr.dirty_vs
489  csrio.exception := ctrlBlock.io.robio.exception
490  csrio.robDeqPtr := ctrlBlock.io.robio.robDeqPtr
491  csrio.memExceptionVAddr := io.mem.exceptionAddr.vaddr
492  csrio.memExceptionGPAddr := io.mem.exceptionAddr.gpaddr
493  csrio.memExceptionIsForVSnonLeafPTE := io.mem.exceptionAddr.isForVSnonLeafPTE
494  csrio.externalInterrupt := RegNext(io.fromTop.externalInterrupt)
495  csrio.perf <> io.perf
496  csrio.perf.retiredInstr <> ctrlBlock.io.robio.csr.perfinfo.retiredInstr
497  csrio.perf.ctrlInfo <> ctrlBlock.io.perfInfo.ctrlInfo
498  private val fenceio = intExuBlock.io.fenceio.get
499  io.fenceio <> fenceio
500
501  // to fpExuBlock
502  fpExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush
503  for (i <- 0 until fpExuBlock.io.in.length) {
504    for (j <- 0 until fpExuBlock.io.in(i).length) {
505      val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.fp(i)(j).bits.loadDependency, io.mem.ldCancel)
506      NewPipelineConnect(
507        bypassNetwork.io.toExus.fp(i)(j), fpExuBlock.io.in(i)(j), fpExuBlock.io.in(i)(j).fire,
508        Mux(
509          bypassNetwork.io.toExus.fp(i)(j).fire,
510          bypassNetwork.io.toExus.fp(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel,
511          fpExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush)
512        ),
513        Option("bypassNetwork2fpExuBlock")
514      )
515    }
516  }
517
518  vfExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush
519  for (i <- 0 until vfExuBlock.io.in.size) {
520    for (j <- 0 until vfExuBlock.io.in(i).size) {
521      val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.vf(i)(j).bits.loadDependency, io.mem.ldCancel)
522      NewPipelineConnect(
523        bypassNetwork.io.toExus.vf(i)(j), vfExuBlock.io.in(i)(j), vfExuBlock.io.in(i)(j).fire,
524        Mux(
525          bypassNetwork.io.toExus.vf(i)(j).fire,
526          bypassNetwork.io.toExus.vf(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel,
527          vfExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush)
528        ),
529        Option("bypassNetwork2vfExuBlock")
530      )
531
532    }
533  }
534
535  intExuBlock.io.frm.foreach(_ := csrio.fpu.frm)
536  fpExuBlock.io.frm.foreach(_ := csrio.fpu.frm)
537  fpExuBlock.io.vxrm.foreach(_ := csrio.vpu.vxrm)
538  vfExuBlock.io.frm.foreach(_ := csrio.fpu.frm)
539  vfExuBlock.io.vxrm.foreach(_ := csrio.vpu.vxrm)
540
541  wbDataPath.io.flush := ctrlBlock.io.redirect
542  wbDataPath.io.fromTop.hartId := io.fromTop.hartId
543  wbDataPath.io.fromIntExu <> intExuBlock.io.out
544  wbDataPath.io.fromFpExu <> fpExuBlock.io.out
545  wbDataPath.io.fromVfExu <> vfExuBlock.io.out
546  wbDataPath.io.fromMemExu.flatten.zip(io.mem.writeBack).foreach { case (sink, source) =>
547    sink.valid := source.valid
548    source.ready := sink.ready
549    sink.bits.data   := VecInit(Seq.fill(sink.bits.params.wbPathNum)(source.bits.data))
550    sink.bits.pdest  := source.bits.uop.pdest
551    sink.bits.robIdx := source.bits.uop.robIdx
552    sink.bits.intWen.foreach(_ := source.bits.uop.rfWen)
553    sink.bits.fpWen.foreach(_ := source.bits.uop.fpWen)
554    sink.bits.vecWen.foreach(_ := source.bits.uop.vecWen)
555    sink.bits.v0Wen.foreach(_ := source.bits.uop.v0Wen)
556    sink.bits.vlWen.foreach(_ := source.bits.uop.vlWen)
557    sink.bits.exceptionVec.foreach(_ := source.bits.uop.exceptionVec)
558    sink.bits.flushPipe.foreach(_ := source.bits.uop.flushPipe)
559    sink.bits.replay.foreach(_ := source.bits.uop.replayInst)
560    sink.bits.debug := source.bits.debug
561    sink.bits.debugInfo := source.bits.uop.debugInfo
562    sink.bits.lqIdx.foreach(_ := source.bits.uop.lqIdx)
563    sink.bits.sqIdx.foreach(_ := source.bits.uop.sqIdx)
564    sink.bits.predecodeInfo.foreach(_ := source.bits.uop.preDecodeInfo)
565    sink.bits.vls.foreach(x => {
566      x.vdIdx := source.bits.vdIdx.get
567      x.vdIdxInField := source.bits.vdIdxInField.get
568      x.vpu   := source.bits.uop.vpu
569      x.oldVdPsrc := source.bits.uop.psrc(2)
570      x.isIndexed := VlduType.isIndexed(source.bits.uop.fuOpType)
571      x.isMasked := VlduType.isMasked(source.bits.uop.fuOpType)
572      x.isStrided := VlduType.isStrided(source.bits.uop.fuOpType)
573      x.isWhole := VlduType.isWhole(source.bits.uop.fuOpType)
574      x.isVecLoad := VlduType.isVecLd(source.bits.uop.fuOpType)
575      x.isVlm := VlduType.isMasked(source.bits.uop.fuOpType) && VlduType.isVecLd(source.bits.uop.fuOpType)
576    })
577    sink.bits.trigger.foreach(_ := source.bits.uop.trigger)
578  }
579  wbDataPath.io.fromCSR.vstart := csrio.vpu.vstart
580
581  vecExcpMod.i.fromExceptionGen := ctrlBlock.io.toVecExcpMod.excpInfo
582  vecExcpMod.i.fromRab.logicPhyRegMap := ctrlBlock.io.toVecExcpMod.logicPhyRegMap
583  vecExcpMod.i.fromRat := ctrlBlock.io.toVecExcpMod.ratOldPest
584  vecExcpMod.i.fromVprf := dataPath.io.toVecExcpMod
585
586  // to mem
587  private val memIssueParams = params.memSchdParams.get.issueBlockParams
588  private val memExuBlocksHasLDU = memIssueParams.map(_.exuBlockParams.map(x => x.hasLoadFu || x.hasHyldaFu))
589  private val memExuBlocksHasVecLoad = memIssueParams.map(_.exuBlockParams.map(x => x.hasVLoadFu))
590  println(s"[Backend] memExuBlocksHasLDU: $memExuBlocksHasLDU")
591  println(s"[Backend] memExuBlocksHasVecLoad: $memExuBlocksHasVecLoad")
592
593  private val toMem = Wire(bypassNetwork.io.toExus.mem.cloneType)
594  for (i <- toMem.indices) {
595    for (j <- toMem(i).indices) {
596      val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.mem(i)(j).bits.loadDependency, io.mem.ldCancel)
597      val needIssueTimeout = memExuBlocksHasLDU(i)(j) || memExuBlocksHasVecLoad(i)(j)
598      val issueTimeout =
599        if (needIssueTimeout)
600          Counter(0 until 16, toMem(i)(j).valid && !toMem(i)(j).fire, bypassNetwork.io.toExus.mem(i)(j).fire)._2
601        else
602          false.B
603
604      if (memScheduler.io.loadFinalIssueResp(i).nonEmpty && memExuBlocksHasLDU(i)(j)) {
605        memScheduler.io.loadFinalIssueResp(i)(j).valid := issueTimeout
606        memScheduler.io.loadFinalIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType
607        memScheduler.io.loadFinalIssueResp(i)(j).bits.resp := RespType.block
608        memScheduler.io.loadFinalIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx
609        memScheduler.io.loadFinalIssueResp(i)(j).bits.uopIdx.foreach(_ := toMem(i)(j).bits.vpu.get.vuopIdx)
610        memScheduler.io.loadFinalIssueResp(i)(j).bits.sqIdx.foreach(_ := toMem(i)(j).bits.sqIdx.get)
611        memScheduler.io.loadFinalIssueResp(i)(j).bits.lqIdx.foreach(_ := toMem(i)(j).bits.lqIdx.get)
612      }
613
614      if (memScheduler.io.vecLoadFinalIssueResp(i).nonEmpty && memExuBlocksHasVecLoad(i)(j)) {
615        memScheduler.io.vecLoadFinalIssueResp(i)(j).valid := issueTimeout
616        memScheduler.io.vecLoadFinalIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType
617        memScheduler.io.vecLoadFinalIssueResp(i)(j).bits.resp := RespType.block
618        memScheduler.io.vecLoadFinalIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx
619        memScheduler.io.vecLoadFinalIssueResp(i)(j).bits.uopIdx.foreach(_ := toMem(i)(j).bits.vpu.get.vuopIdx)
620        memScheduler.io.vecLoadFinalIssueResp(i)(j).bits.sqIdx.foreach(_ := toMem(i)(j).bits.sqIdx.get)
621        memScheduler.io.vecLoadFinalIssueResp(i)(j).bits.lqIdx.foreach(_ := toMem(i)(j).bits.lqIdx.get)
622      }
623
624      NewPipelineConnect(
625        bypassNetwork.io.toExus.mem(i)(j), toMem(i)(j), toMem(i)(j).fire,
626        Mux(
627          bypassNetwork.io.toExus.mem(i)(j).fire,
628          bypassNetwork.io.toExus.mem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel,
629          toMem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || issueTimeout
630        ),
631        Option("bypassNetwork2toMemExus")
632      )
633
634      if (memScheduler.io.memAddrIssueResp(i).nonEmpty && memExuBlocksHasLDU(i)(j)) {
635        memScheduler.io.memAddrIssueResp(i)(j).valid := toMem(i)(j).fire && FuType.isLoad(toMem(i)(j).bits.fuType)
636        memScheduler.io.memAddrIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType
637        memScheduler.io.memAddrIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx
638        memScheduler.io.memAddrIssueResp(i)(j).bits.sqIdx.foreach(_ := toMem(i)(j).bits.sqIdx.get)
639        memScheduler.io.memAddrIssueResp(i)(j).bits.lqIdx.foreach(_ := toMem(i)(j).bits.lqIdx.get)
640        memScheduler.io.memAddrIssueResp(i)(j).bits.resp := RespType.success // for load inst, firing at toMem means issuing successfully
641      }
642
643      if (memScheduler.io.vecLoadIssueResp(i).nonEmpty && memExuBlocksHasVecLoad(i)(j)) {
644        memScheduler.io.vecLoadIssueResp(i)(j) match {
645          case resp =>
646            resp.valid := toMem(i)(j).fire && VlduType.isVecLd(toMem(i)(j).bits.fuOpType)
647            resp.bits.fuType := toMem(i)(j).bits.fuType
648            resp.bits.robIdx := toMem(i)(j).bits.robIdx
649            resp.bits.uopIdx.get := toMem(i)(j).bits.vpu.get.vuopIdx
650            resp.bits.sqIdx.get := toMem(i)(j).bits.sqIdx.get
651            resp.bits.lqIdx.get := toMem(i)(j).bits.lqIdx.get
652            resp.bits.resp := RespType.success
653        }
654        if (backendParams.debugEn){
655          dontTouch(memScheduler.io.vecLoadIssueResp(i)(j))
656        }
657      }
658    }
659  }
660
661  io.mem.redirect := ctrlBlock.io.redirect
662  io.mem.issueUops.zip(toMem.flatten).foreach { case (sink, source) =>
663    val enableMdp = Constantin.createRecord("EnableMdp", true)
664    sink.valid := source.valid
665    source.ready := sink.ready
666    sink.bits.iqIdx              := source.bits.iqIdx
667    sink.bits.isFirstIssue       := source.bits.isFirstIssue
668    sink.bits.uop                := 0.U.asTypeOf(sink.bits.uop)
669    sink.bits.src                := 0.U.asTypeOf(sink.bits.src)
670    sink.bits.src.zip(source.bits.src).foreach { case (l, r) => l := r}
671    sink.bits.uop.fuType         := source.bits.fuType
672    sink.bits.uop.fuOpType       := source.bits.fuOpType
673    sink.bits.uop.imm            := source.bits.imm
674    sink.bits.uop.robIdx         := source.bits.robIdx
675    sink.bits.uop.pdest          := source.bits.pdest
676    sink.bits.uop.rfWen          := source.bits.rfWen.getOrElse(false.B)
677    sink.bits.uop.fpWen          := source.bits.fpWen.getOrElse(false.B)
678    sink.bits.uop.vecWen         := source.bits.vecWen.getOrElse(false.B)
679    sink.bits.uop.v0Wen          := source.bits.v0Wen.getOrElse(false.B)
680    sink.bits.uop.vlWen          := source.bits.vlWen.getOrElse(false.B)
681    sink.bits.uop.flushPipe      := source.bits.flushPipe.getOrElse(false.B)
682    sink.bits.uop.pc             := source.bits.pc.getOrElse(0.U)
683    sink.bits.uop.loadWaitBit    := Mux(enableMdp, source.bits.loadWaitBit.getOrElse(false.B), false.B)
684    sink.bits.uop.waitForRobIdx  := Mux(enableMdp, source.bits.waitForRobIdx.getOrElse(0.U.asTypeOf(new RobPtr)), 0.U.asTypeOf(new RobPtr))
685    sink.bits.uop.storeSetHit    := Mux(enableMdp, source.bits.storeSetHit.getOrElse(false.B), false.B)
686    sink.bits.uop.loadWaitStrict := Mux(enableMdp, source.bits.loadWaitStrict.getOrElse(false.B), false.B)
687    sink.bits.uop.ssid           := Mux(enableMdp, source.bits.ssid.getOrElse(0.U(SSIDWidth.W)), 0.U(SSIDWidth.W))
688    sink.bits.uop.lqIdx          := source.bits.lqIdx.getOrElse(0.U.asTypeOf(new LqPtr))
689    sink.bits.uop.sqIdx          := source.bits.sqIdx.getOrElse(0.U.asTypeOf(new SqPtr))
690    sink.bits.uop.ftqPtr         := source.bits.ftqIdx.getOrElse(0.U.asTypeOf(new FtqPtr))
691    sink.bits.uop.ftqOffset      := source.bits.ftqOffset.getOrElse(0.U)
692    sink.bits.uop.debugInfo      := source.bits.perfDebugInfo
693    sink.bits.uop.vpu            := source.bits.vpu.getOrElse(0.U.asTypeOf(new VPUCtrlSignals))
694    sink.bits.uop.preDecodeInfo  := source.bits.preDecode.getOrElse(0.U.asTypeOf(new PreDecodeInfo))
695    sink.bits.uop.numLsElem      := source.bits.numLsElem.getOrElse(0.U) // Todo: remove this bundle, keep only the one below
696    sink.bits.flowNum.foreach(_  := source.bits.numLsElem.get)
697  }
698  io.mem.loadFastMatch := memScheduler.io.toMem.get.loadFastMatch.map(_.fastMatch)
699  io.mem.loadFastImm := memScheduler.io.toMem.get.loadFastMatch.map(_.fastImm)
700  io.mem.tlbCsr := csrio.tlb
701  io.mem.csrCtrl := csrio.customCtrl
702  io.mem.sfence := fenceio.sfence
703  io.mem.isStoreException := CommitType.lsInstIsStore(ctrlBlock.io.robio.exception.bits.commitType)
704  io.mem.isVlsException := ctrlBlock.io.robio.exception.bits.vls
705  require(io.mem.loadPcRead.size == params.LduCnt)
706  io.mem.loadPcRead.zipWithIndex.foreach { case (loadPcRead, i) =>
707    loadPcRead := ctrlBlock.io.memLdPcRead(i).data
708    ctrlBlock.io.memLdPcRead(i).valid := io.mem.issueLda(i).valid
709    ctrlBlock.io.memLdPcRead(i).ptr := io.mem.issueLda(i).bits.uop.ftqPtr
710    ctrlBlock.io.memLdPcRead(i).offset := io.mem.issueLda(i).bits.uop.ftqOffset
711  }
712
713  io.mem.storePcRead.zipWithIndex.foreach { case (storePcRead, i) =>
714    storePcRead := ctrlBlock.io.memStPcRead(i).data
715    ctrlBlock.io.memStPcRead(i).valid := io.mem.issueSta(i).valid
716    ctrlBlock.io.memStPcRead(i).ptr := io.mem.issueSta(i).bits.uop.ftqPtr
717    ctrlBlock.io.memStPcRead(i).offset := io.mem.issueSta(i).bits.uop.ftqOffset
718  }
719
720  io.mem.hyuPcRead.zipWithIndex.foreach( { case (hyuPcRead, i) =>
721    hyuPcRead := ctrlBlock.io.memHyPcRead(i).data
722    ctrlBlock.io.memHyPcRead(i).valid := io.mem.issueHylda(i).valid
723    ctrlBlock.io.memHyPcRead(i).ptr := io.mem.issueHylda(i).bits.uop.ftqPtr
724    ctrlBlock.io.memHyPcRead(i).offset := io.mem.issueHylda(i).bits.uop.ftqOffset
725  })
726
727  ctrlBlock.io.robio.robHeadLsIssue := io.mem.issueUops.map(deq => deq.fire && deq.bits.uop.robIdx === ctrlBlock.io.robio.robDeqPtr).reduce(_ || _)
728
729  // mem io
730  io.mem.lsqEnqIO <> memScheduler.io.memIO.get.lsqEnqIO
731  io.mem.robLsqIO <> ctrlBlock.io.robio.lsq
732
733  io.frontendSfence := fenceio.sfence
734  io.frontendTlbCsr := csrio.tlb
735  io.frontendCsrCtrl := csrio.customCtrl
736
737  io.tlb <> csrio.tlb
738
739  io.csrCustomCtrl := csrio.customCtrl
740
741  io.toTop.cpuHalted := ctrlBlock.io.toTop.cpuHalt
742
743  io.debugTopDown.fromRob := ctrlBlock.io.debugTopDown.fromRob
744  ctrlBlock.io.debugTopDown.fromCore := io.debugTopDown.fromCore
745
746  io.debugRolling := ctrlBlock.io.debugRolling
747
748  if(backendParams.debugEn) {
749    dontTouch(memScheduler.io)
750    dontTouch(dataPath.io.toMemExu)
751    dontTouch(wbDataPath.io.fromMemExu)
752  }
753
754  // reset tree
755  if (p(DebugOptionsKey).ResetGen) {
756    val rightResetTree = ResetGenNode(Seq(
757      ModuleNode(dataPath),
758      ModuleNode(intExuBlock),
759      ModuleNode(fpExuBlock),
760      ModuleNode(vfExuBlock),
761      ModuleNode(bypassNetwork),
762      ModuleNode(wbDataPath)
763    ))
764    val leftResetTree = ResetGenNode(Seq(
765      ModuleNode(pcTargetMem),
766      ModuleNode(intScheduler),
767      ModuleNode(fpScheduler),
768      ModuleNode(vfScheduler),
769      ModuleNode(memScheduler),
770      ModuleNode(og2ForVector),
771      ModuleNode(wbFuBusyTable),
772      ResetGenNode(Seq(
773        ModuleNode(ctrlBlock),
774        // ResetGenNode(Seq(
775          CellNode(io.frontendReset)
776        // ))
777      ))
778    ))
779    ResetGen(leftResetTree, reset, sim = false)
780    ResetGen(rightResetTree, reset, sim = false)
781  } else {
782    io.frontendReset := DontCare
783  }
784
785  // perf events
786  val pfevent = Module(new PFEvent)
787  pfevent.io.distribute_csr := RegNext(csrio.customCtrl.distribute_csr)
788  val csrevents = pfevent.io.hpmevent.slice(8,16)
789
790  val ctrlBlockPerf    = ctrlBlock.getPerfEvents
791  val intSchedulerPerf = intScheduler.asInstanceOf[SchedulerArithImp].getPerfEvents
792  val fpSchedulerPerf  = fpScheduler.asInstanceOf[SchedulerArithImp].getPerfEvents
793  val vecSchedulerPerf = vfScheduler.asInstanceOf[SchedulerArithImp].getPerfEvents
794  val memSchedulerPerf = memScheduler.asInstanceOf[SchedulerMemImp].getPerfEvents
795
796  val perfBackend  = Seq()
797  // let index = 0 be no event
798  val allPerfEvents = Seq(("noEvent", 0.U)) ++ ctrlBlockPerf ++ intSchedulerPerf ++ fpSchedulerPerf ++ vecSchedulerPerf ++ memSchedulerPerf ++ perfBackend
799
800
801  if (printEventCoding) {
802    for (((name, inc), i) <- allPerfEvents.zipWithIndex) {
803      println("backend perfEvents Set", name, inc, i)
804    }
805  }
806
807  val allPerfInc = allPerfEvents.map(_._2.asTypeOf(new PerfEvent))
808  val perfEvents = HPerfMonitor(csrevents, allPerfInc).getPerfEvents
809  csrio.perf.perfEventsBackend := VecInit(perfEvents.map(_._2.asTypeOf(new PerfEvent)))
810
811  val ctrlBlockError = ctrlBlock.getCriticalErrors
812  val intExuBlockError = intExuBlock.getCriticalErrors
813  val criticalErrors = ctrlBlockError ++ intExuBlockError
814
815  if (printCriticalError) {
816    for (((name, error), _) <- criticalErrors.zipWithIndex) {
817      XSError(error, s"critical error: $name \n")
818    }
819  }
820
821  // expand to collect frontend/memblock/L2 critical errors
822  val backendCriticalError = criticalErrors.map(_._2).reduce(_ || _)
823
824  ctrlBlock.io.robio.criticalError := backendCriticalError
825  io.toTop.cpuCriticalError := backendCriticalError
826
827}
828
829class BackendMemIO(implicit p: Parameters, params: BackendParams) extends XSBundle {
830  // Since fast load replay always use load unit 0, Backend flips two load port to avoid conflicts
831  val flippedLda = true
832  // params alias
833  private val LoadQueueSize = VirtualLoadQueueSize
834  // In/Out // Todo: split it into one-direction bundle
835  val lsqEnqIO = Flipped(new LsqEnqIO)
836  val robLsqIO = new RobLsqIO
837  val ldaIqFeedback = Vec(params.LduCnt, Flipped(new MemRSFeedbackIO))
838  val staIqFeedback = Vec(params.StaCnt, Flipped(new MemRSFeedbackIO))
839  val hyuIqFeedback = Vec(params.HyuCnt, Flipped(new MemRSFeedbackIO))
840  val vstuIqFeedback = Flipped(Vec(params.VstuCnt, new MemRSFeedbackIO(isVector = true)))
841  val vlduIqFeedback = Flipped(Vec(params.VlduCnt, new MemRSFeedbackIO(isVector = true)))
842  val ldCancel = Vec(params.LdExuCnt, Input(new LoadCancelIO))
843  val wakeup = Vec(params.LdExuCnt, Flipped(Valid(new DynInst)))
844  val loadPcRead = Vec(params.LduCnt, Output(UInt(VAddrBits.W)))
845  val storePcRead = Vec(params.StaCnt, Output(UInt(VAddrBits.W)))
846  val hyuPcRead = Vec(params.HyuCnt, Output(UInt(VAddrBits.W)))
847  // Input
848  val writebackLda = Vec(params.LduCnt, Flipped(DecoupledIO(new MemExuOutput)))
849  val writebackSta = Vec(params.StaCnt, Flipped(DecoupledIO(new MemExuOutput)))
850  val writebackStd = Vec(params.StdCnt, Flipped(DecoupledIO(new MemExuOutput)))
851  val writebackHyuLda = Vec(params.HyuCnt, Flipped(DecoupledIO(new MemExuOutput)))
852  val writebackHyuSta = Vec(params.HyuCnt, Flipped(DecoupledIO(new MemExuOutput)))
853  val writebackVldu = Vec(params.VlduCnt, Flipped(DecoupledIO(new MemExuOutput(true))))
854
855  val s3_delayed_load_error = Input(Vec(LoadPipelineWidth, Bool()))
856  val stIn = Input(Vec(params.StaExuCnt, ValidIO(new DynInst())))
857  val memoryViolation = Flipped(ValidIO(new Redirect))
858  val exceptionAddr = Input(new Bundle {
859    val vaddr = UInt(XLEN.W)
860    val gpaddr = UInt(XLEN.W)
861    val isForVSnonLeafPTE = Bool()
862  })
863  val sqDeq = Input(UInt(log2Ceil(EnsbufferWidth + 1).W))
864  val lqDeq = Input(UInt(log2Up(CommitWidth + 1).W))
865  val sqDeqPtr = Input(new SqPtr)
866  val lqDeqPtr = Input(new LqPtr)
867
868  val lqCancelCnt = Input(UInt(log2Up(VirtualLoadQueueSize + 1).W))
869  val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W))
870
871  val lqCanAccept = Input(Bool())
872  val sqCanAccept = Input(Bool())
873
874  val otherFastWakeup = Flipped(Vec(params.LduCnt + params.HyuCnt, ValidIO(new DynInst)))
875  val stIssuePtr = Input(new SqPtr())
876
877  val debugLS = Flipped(Output(new DebugLSIO))
878
879  val lsTopdownInfo = Vec(params.LduCnt + params.HyuCnt, Flipped(Output(new LsTopdownInfo)))
880  // Output
881  val redirect = ValidIO(new Redirect)   // rob flush MemBlock
882  val issueLda = MixedVec(Seq.fill(params.LduCnt)(DecoupledIO(new MemExuInput())))
883  val issueSta = MixedVec(Seq.fill(params.StaCnt)(DecoupledIO(new MemExuInput())))
884  val issueStd = MixedVec(Seq.fill(params.StdCnt)(DecoupledIO(new MemExuInput())))
885  val issueHylda = MixedVec(Seq.fill(params.HyuCnt)(DecoupledIO(new MemExuInput())))
886  val issueHysta = MixedVec(Seq.fill(params.HyuCnt)(DecoupledIO(new MemExuInput())))
887  val issueVldu = MixedVec(Seq.fill(params.VlduCnt)(DecoupledIO(new MemExuInput(true))))
888
889  val loadFastMatch = Vec(params.LduCnt, Output(UInt(params.LduCnt.W)))
890  val loadFastImm   = Vec(params.LduCnt, Output(UInt(12.W))) // Imm_I
891
892  val tlbCsr = Output(new TlbCsrBundle)
893  val csrCtrl = Output(new CustomCSRCtrlIO)
894  val sfence = Output(new SfenceBundle)
895  val isStoreException = Output(Bool())
896  val isVlsException = Output(Bool())
897
898  // ATTENTION: The issue ports' sequence order should be the same as IQs' deq config
899  private [backend] def issueUops: Seq[DecoupledIO[MemExuInput]] = {
900    issueSta ++
901      issueHylda ++ issueHysta ++
902      issueLda ++
903      issueVldu ++
904      issueStd
905  }.toSeq
906
907  // ATTENTION: The writeback ports' sequence order should be the same as IQs' deq config
908  private [backend] def writeBack: Seq[DecoupledIO[MemExuOutput]] = {
909    writebackSta ++
910      writebackHyuLda ++ writebackHyuSta ++
911      writebackLda ++
912      writebackVldu ++
913      writebackStd
914  }
915}
916
917class TopToBackendBundle(implicit p: Parameters) extends XSBundle {
918  val hartId            = Output(UInt(hartIdLen.W))
919  val externalInterrupt = Output(new ExternalInterruptIO)
920  val msiInfo           = Output(ValidIO(new MsiInfoBundle))
921  val clintTime         = Output(ValidIO(UInt(64.W)))
922}
923
924class BackendToTopBundle extends Bundle {
925  val cpuHalted = Output(Bool())
926  val cpuCriticalError = Output(Bool())
927}
928
929class BackendIO(implicit p: Parameters, params: BackendParams) extends XSBundle with HasSoCParameter {
930  val fromTop = Flipped(new TopToBackendBundle)
931
932  val toTop = new BackendToTopBundle
933
934  val fenceio = new FenceIO
935  // Todo: merge these bundles into BackendFrontendIO
936  val frontend = Flipped(new FrontendToCtrlIO)
937  val frontendSfence = Output(new SfenceBundle)
938  val frontendCsrCtrl = Output(new CustomCSRCtrlIO)
939  val frontendTlbCsr = Output(new TlbCsrBundle)
940  val frontendReset = Output(Reset())
941
942  val mem = new BackendMemIO
943
944  val perf = Input(new PerfCounterIO)
945
946  val tlb = Output(new TlbCsrBundle)
947
948  val csrCustomCtrl = Output(new CustomCSRCtrlIO)
949
950  val debugTopDown = new Bundle {
951    val fromRob = new RobCoreTopDownIO
952    val fromCore = new CoreDispatchTopDownIO
953  }
954  val debugRolling = new RobDebugRollingIO
955}
956