1package xiangshan.backend 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import utility.{Constantin, ZeroExt} 8import xiangshan._ 9import xiangshan.backend.Bundles.{DynInst, IssueQueueIQWakeUpBundle, LoadShouldCancel, MemExuInput, MemExuOutput, VPUCtrlSignals} 10import xiangshan.backend.ctrlblock.{DebugLSIO, LsTopdownInfo} 11import xiangshan.backend.datapath.DataConfig.{IntData, VecData} 12import xiangshan.backend.datapath.RdConfig.{IntRD, VfRD} 13import xiangshan.backend.datapath.WbConfig._ 14import xiangshan.backend.datapath._ 15import xiangshan.backend.dispatch.CoreDispatchTopDownIO 16import xiangshan.backend.exu.ExuBlock 17import xiangshan.backend.fu.vector.Bundles.{VConfig, VType} 18import xiangshan.backend.fu.{FenceIO, FenceToSbuffer, FuConfig, FuType, PerfCounterIO} 19import xiangshan.backend.issue.{CancelNetwork, Scheduler, SchedulerImpBase} 20import xiangshan.backend.rob.{RobCoreTopDownIO, RobDebugRollingIO, RobLsqIO, RobPtr} 21import xiangshan.frontend.{FtqPtr, FtqRead, PreDecodeInfo} 22import xiangshan.mem.{LqPtr, LsqEnqIO, SqPtr} 23 24class Backend(val params: BackendParams)(implicit p: Parameters) extends LazyModule 25 with HasXSParameter { 26 27 override def shouldBeInlined: Boolean = false 28 29 /* Only update the idx in mem-scheduler here 30 * Idx in other schedulers can be updated the same way if needed 31 * 32 * Also note that we filter out the 'stData issue-queues' when counting 33 */ 34 for ((ibp, idx) <- params.memSchdParams.get.issueBlockParams.filter(iq => iq.StdCnt == 0 && iq.VstdCnt == 0).zipWithIndex) { 35 ibp.updateIdx(idx) 36 } 37 38 println(params.iqWakeUpParams) 39 40 for ((schdCfg, i) <- params.allSchdParams.zipWithIndex) { 41 schdCfg.bindBackendParam(params) 42 } 43 44 for ((iqCfg, i) <- params.allIssueParams.zipWithIndex) { 45 iqCfg.bindBackendParam(params) 46 } 47 48 for ((exuCfg, i) <- params.allExuParams.zipWithIndex) { 49 exuCfg.bindBackendParam(params) 50 exuCfg.updateIQWakeUpConfigs(params.iqWakeUpParams) 51 exuCfg.updateExuIdx(i) 52 } 53 54 println("[Backend] ExuConfigs:") 55 for (exuCfg <- params.allExuParams) { 56 val fuConfigs = exuCfg.fuConfigs 57 val wbPortConfigs = exuCfg.wbPortConfigs 58 val immType = exuCfg.immType 59 60 println("[Backend] " + 61 s"${exuCfg.name}: " + 62 (if (exuCfg.fakeUnit) "fake, " else "") + 63 (if (exuCfg.hasLoadFu || exuCfg.hasHyldaFu) s"LdExuIdx(${backendParams.getLdExuIdx(exuCfg)})" else "") + 64 s"${fuConfigs.map(_.name).mkString("fu(s): {", ",", "}")}, " + 65 s"${wbPortConfigs.mkString("wb: {", ",", "}")}, " + 66 s"${immType.map(SelImm.mkString(_)).mkString("imm: {", ",", "}")}, " + 67 s"latMax(${exuCfg.latencyValMax}), ${exuCfg.fuLatancySet.mkString("lat: {", ",", "}")}, " + 68 s"srcReg(${exuCfg.numRegSrc})" 69 ) 70 require( 71 wbPortConfigs.collectFirst { case x: IntWB => x }.nonEmpty == 72 fuConfigs.map(_.writeIntRf).reduce(_ || _), 73 s"${exuCfg.name} int wb port has no priority" 74 ) 75 require( 76 wbPortConfigs.collectFirst { case x: VfWB => x }.nonEmpty == 77 fuConfigs.map(x => x.writeFpRf || x.writeVecRf).reduce(_ || _), 78 s"${exuCfg.name} vec wb port has no priority" 79 ) 80 } 81 82 println(s"[Backend] all fu configs") 83 for (cfg <- FuConfig.allConfigs) { 84 println(s"[Backend] $cfg") 85 } 86 87 println(s"[Backend] Int RdConfigs: ExuName(Priority)") 88 for ((port, seq) <- params.getRdPortParams(IntData())) { 89 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 90 } 91 92 println(s"[Backend] Int WbConfigs: ExuName(Priority)") 93 for ((port, seq) <- params.getWbPortParams(IntData())) { 94 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 95 } 96 97 println(s"[Backend] Vf RdConfigs: ExuName(Priority)") 98 for ((port, seq) <- params.getRdPortParams(VecData())) { 99 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 100 } 101 102 println(s"[Backend] Vf WbConfigs: ExuName(Priority)") 103 for ((port, seq) <- params.getWbPortParams(VecData())) { 104 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 105 } 106 107 println(s"[Backend] Dispatch Configs:") 108 println(s"[Backend] Load IQ enq width(${params.numLoadDp}), Store IQ enq width(${params.numStoreDp})") 109 println(s"[Backend] Load DP width(${LSQLdEnqWidth}), Store DP width(${LSQStEnqWidth})") 110 111 val ctrlBlock = LazyModule(new CtrlBlock(params)) 112 val pcTargetMem = LazyModule(new PcTargetMem(params)) 113 val intScheduler = params.intSchdParams.map(x => LazyModule(new Scheduler(x))) 114 val vfScheduler = params.vfSchdParams.map(x => LazyModule(new Scheduler(x))) 115 val memScheduler = params.memSchdParams.map(x => LazyModule(new Scheduler(x))) 116 val dataPath = LazyModule(new DataPath(params)) 117 val intExuBlock = params.intSchdParams.map(x => LazyModule(new ExuBlock(x))) 118 val vfExuBlock = params.vfSchdParams.map(x => LazyModule(new ExuBlock(x))) 119 val wbFuBusyTable = LazyModule(new WbFuBusyTable(params)) 120 121 lazy val module = new BackendImp(this) 122} 123 124class BackendImp(override val wrapper: Backend)(implicit p: Parameters) extends LazyModuleImp(wrapper) 125 with HasXSParameter { 126 implicit private val params = wrapper.params 127 128 val io = IO(new BackendIO()(p, wrapper.params)) 129 130 private val ctrlBlock = wrapper.ctrlBlock.module 131 private val pcTargetMem = wrapper.pcTargetMem.module 132 private val intScheduler: SchedulerImpBase = wrapper.intScheduler.get.module 133 private val vfScheduler = wrapper.vfScheduler.get.module 134 private val memScheduler = wrapper.memScheduler.get.module 135 private val dataPath = wrapper.dataPath.module 136 private val intExuBlock = wrapper.intExuBlock.get.module 137 private val vfExuBlock = wrapper.vfExuBlock.get.module 138 private val bypassNetwork = Module(new BypassNetwork) 139 private val wbDataPath = Module(new WbDataPath(params)) 140 private val wbFuBusyTable = wrapper.wbFuBusyTable.module 141 142 private val iqWakeUpMappedBundle: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = ( 143 intScheduler.io.toSchedulers.wakeupVec ++ 144 vfScheduler.io.toSchedulers.wakeupVec ++ 145 memScheduler.io.toSchedulers.wakeupVec 146 ).map(x => (x.bits.exuIdx, x)).toMap 147 148 println(s"[Backend] iq wake up keys: ${iqWakeUpMappedBundle.keys}") 149 150 wbFuBusyTable.io.in.intSchdBusyTable := intScheduler.io.wbFuBusyTable 151 wbFuBusyTable.io.in.vfSchdBusyTable := vfScheduler.io.wbFuBusyTable 152 wbFuBusyTable.io.in.memSchdBusyTable := memScheduler.io.wbFuBusyTable 153 intScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.intRespRead 154 vfScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.vfRespRead 155 memScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.memRespRead 156 dataPath.io.wbConfictRead := wbFuBusyTable.io.out.wbConflictRead 157 158 wbDataPath.io.fromIntExu.flatten.filter(x => x.bits.params.writeIntRf) 159 160 private val vconfig = dataPath.io.vconfigReadPort.data 161 private val og1CancelOH: UInt = dataPath.io.og1CancelOH 162 private val og0CancelOH: UInt = dataPath.io.og0CancelOH 163 private val cancelToBusyTable = dataPath.io.cancelToBusyTable 164 private val finalBlockMem = Wire(Vec(params.memSchdParams.get.numExu, Bool())) 165 166 ctrlBlock.io.fromTop.hartId := io.fromTop.hartId 167 ctrlBlock.io.frontend <> io.frontend 168 ctrlBlock.io.fromWB.wbData <> wbDataPath.io.toCtrlBlock.writeback 169 ctrlBlock.io.fromMem.stIn <> io.mem.stIn 170 ctrlBlock.io.fromMem.violation <> io.mem.memoryViolation 171 ctrlBlock.io.lqCanAccept := io.mem.lqCanAccept 172 ctrlBlock.io.sqCanAccept := io.mem.sqCanAccept 173 ctrlBlock.io.csrCtrl <> intExuBlock.io.csrio.get.customCtrl 174 ctrlBlock.io.robio.csr.intrBitSet := intExuBlock.io.csrio.get.interrupt 175 ctrlBlock.io.robio.csr.trapTarget := intExuBlock.io.csrio.get.trapTarget 176 ctrlBlock.io.robio.csr.isXRet := intExuBlock.io.csrio.get.isXRet 177 ctrlBlock.io.robio.csr.wfiEvent := intExuBlock.io.csrio.get.wfi_event 178 ctrlBlock.io.robio.lsq <> io.mem.robLsqIO 179 ctrlBlock.io.robio.lsTopdownInfo <> io.mem.lsTopdownInfo 180 ctrlBlock.io.robio.debug_ls <> io.mem.debugLS 181 ctrlBlock.io.fromDataPath.vtype := vconfig(7, 0).asTypeOf(new VType) 182 ctrlBlock.perfinfo := DontCare // TODO: Implement backend hpm 183 ctrlBlock.io.debugEnqLsq.canAccept := io.mem.lsqEnqIO.canAccept 184 ctrlBlock.io.debugEnqLsq.resp := io.mem.lsqEnqIO.resp 185 ctrlBlock.io.debugEnqLsq.req := memScheduler.io.memIO.get.lsqEnqIO.req 186 ctrlBlock.io.debugEnqLsq.needAlloc := memScheduler.io.memIO.get.lsqEnqIO.needAlloc 187 188 189 intScheduler.io.fromTop.hartId := io.fromTop.hartId 190 intScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 191 intScheduler.io.fromCtrlBlock.pcVec := ctrlBlock.io.toIssueBlock.pcVec 192 intScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 193 intScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.intUops 194 intScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 195 intScheduler.io.vfWriteBack := 0.U.asTypeOf(intScheduler.io.vfWriteBack) 196 intScheduler.io.fromDataPath.resp := dataPath.io.toIntIQ 197 intScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 198 intScheduler.io.fromDataPath.og0Cancel := og0CancelOH 199 intScheduler.io.fromDataPath.og1Cancel := og1CancelOH 200 intScheduler.io.ldCancel := io.mem.ldCancel 201 intScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 202 203 memScheduler.io.fromTop.hartId := io.fromTop.hartId 204 memScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 205 memScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 206 memScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.memUops 207 memScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 208 memScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 209 memScheduler.io.finalBlockMem.get.flatten.zip(finalBlockMem).foreach(x => x._1 := x._2) 210 memScheduler.io.fromMem.get.scommit := io.mem.sqDeq 211 memScheduler.io.fromMem.get.lcommit := io.mem.lqDeq 212 memScheduler.io.fromMem.get.sqDeqPtr := io.mem.sqDeqPtr 213 memScheduler.io.fromMem.get.lqDeqPtr := io.mem.lqDeqPtr 214 memScheduler.io.fromMem.get.sqCancelCnt := io.mem.sqCancelCnt 215 memScheduler.io.fromMem.get.lqCancelCnt := io.mem.lqCancelCnt 216 memScheduler.io.fromMem.get.stIssuePtr := io.mem.stIssuePtr 217 require(memScheduler.io.fromMem.get.memWaitUpdateReq.robIdx.length == io.mem.stIn.length) 218 memScheduler.io.fromMem.get.memWaitUpdateReq.robIdx.zip(io.mem.stIn).foreach { case (sink, source) => 219 sink.valid := source.valid 220 sink.bits := source.bits.robIdx 221 } 222 memScheduler.io.fromMem.get.memWaitUpdateReq.sqIdx := DontCare // TODO 223 memScheduler.io.fromDataPath.resp := dataPath.io.toMemIQ 224 memScheduler.io.fromMem.get.ldaFeedback := io.mem.ldaIqFeedback 225 memScheduler.io.fromMem.get.staFeedback := io.mem.staIqFeedback 226 memScheduler.io.fromMem.get.hyuFeedback := io.mem.hyuIqFeedback 227 memScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 228 memScheduler.io.fromDataPath.og0Cancel := og0CancelOH 229 memScheduler.io.fromDataPath.og1Cancel := og1CancelOH 230 memScheduler.io.ldCancel := io.mem.ldCancel 231 memScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 232 233 vfScheduler.io.fromTop.hartId := io.fromTop.hartId 234 vfScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 235 vfScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 236 vfScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.vfUops 237 vfScheduler.io.intWriteBack := 0.U.asTypeOf(vfScheduler.io.intWriteBack) 238 vfScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 239 vfScheduler.io.fromDataPath.resp := dataPath.io.toVfIQ 240 vfScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 241 vfScheduler.io.fromDataPath.og0Cancel := og0CancelOH 242 vfScheduler.io.fromDataPath.og1Cancel := og1CancelOH 243 vfScheduler.io.ldCancel := io.mem.ldCancel 244 vfScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 245 246 dataPath.io.hartId := io.fromTop.hartId 247 dataPath.io.flush := ctrlBlock.io.toDataPath.flush 248 dataPath.io.vconfigReadPort.addr := ctrlBlock.io.toDataPath.vtypeAddr 249 dataPath.io.vldReadPort.addr := wbDataPath.io.oldVdAddrToDataPath 250 251 dataPath.io.fromIntIQ <> intScheduler.io.toDataPathAfterDelay 252 dataPath.io.fromVfIQ <> vfScheduler.io.toDataPathAfterDelay 253 dataPath.io.fromMemIQ <> memScheduler.io.toDataPathAfterDelay 254 255 dataPath.io.ldCancel := io.mem.ldCancel 256 257 println(s"[Backend] wbDataPath.io.toIntPreg: ${wbDataPath.io.toIntPreg.size}, dataPath.io.fromIntWb: ${dataPath.io.fromIntWb.size}") 258 println(s"[Backend] wbDataPath.io.toVfPreg: ${wbDataPath.io.toVfPreg.size}, dataPath.io.fromFpWb: ${dataPath.io.fromVfWb.size}") 259 dataPath.io.fromIntWb := wbDataPath.io.toIntPreg 260 dataPath.io.fromVfWb := wbDataPath.io.toVfPreg 261 dataPath.io.debugIntRat .foreach(_ := ctrlBlock.io.debug_int_rat.get) 262 dataPath.io.debugFpRat .foreach(_ := ctrlBlock.io.debug_fp_rat.get) 263 dataPath.io.debugVecRat .foreach(_ := ctrlBlock.io.debug_vec_rat.get) 264 dataPath.io.debugVconfigRat.foreach(_ := ctrlBlock.io.debug_vconfig_rat.get) 265 266 bypassNetwork.io.fromDataPath.int <> dataPath.io.toIntExu 267 bypassNetwork.io.fromDataPath.vf <> dataPath.io.toFpExu 268 bypassNetwork.io.fromDataPath.mem <> dataPath.io.toMemExu 269 bypassNetwork.io.fromExus.connectExuOutput(_.int)(intExuBlock.io.out) 270 bypassNetwork.io.fromExus.connectExuOutput(_.vf)(vfExuBlock.io.out) 271 272 require(bypassNetwork.io.fromExus.mem.flatten.size == io.mem.writeBack.size, 273 s"bypassNetwork.io.fromExus.mem.flatten.size(${bypassNetwork.io.fromExus.mem.flatten.size}: ${bypassNetwork.io.fromExus.mem.map(_.size)}, " + 274 s"io.mem.writeback(${io.mem.writeBack.size})" 275 ) 276 bypassNetwork.io.fromExus.mem.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 277 sink.valid := source.valid 278 sink.bits.pdest := source.bits.uop.pdest 279 sink.bits.data := source.bits.data 280 } 281 282 283 intExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 284 for (i <- 0 until intExuBlock.io.in.length) { 285 for (j <- 0 until intExuBlock.io.in(i).length) { 286 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.int(i)(j).bits.loadDependency, io.mem.ldCancel) 287 NewPipelineConnect( 288 bypassNetwork.io.toExus.int(i)(j), intExuBlock.io.in(i)(j), intExuBlock.io.in(i)(j).fire, 289 Mux( 290 bypassNetwork.io.toExus.int(i)(j).fire, 291 bypassNetwork.io.toExus.int(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 292 intExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 293 ), 294 Option("intExuBlock2bypassNetwork") 295 ) 296 } 297 } 298 299 pcTargetMem.io.fromFrontendFtq := io.frontend.fromFtq 300 pcTargetMem.io.fromDataPathFtq := bypassNetwork.io.toExus.int.flatten.filter(_.bits.params.needTarget).map(_.bits.ftqIdx.get).toSeq 301 intExuBlock.io.in.flatten.filter(_.bits.params.needTarget).map(_.bits.predictInfo.get.target).zipWithIndex.foreach { 302 case (sink, i) => 303 sink := pcTargetMem.io.toExus(i) 304 } 305 306 private val csrio = intExuBlock.io.csrio.get 307 csrio.hartId := io.fromTop.hartId 308 csrio.fpu.fflags := ctrlBlock.io.robio.csr.fflags 309 csrio.fpu.isIllegal := false.B // Todo: remove it 310 csrio.fpu.dirty_fs := ctrlBlock.io.robio.csr.dirty_fs 311 csrio.vpu <> 0.U.asTypeOf(csrio.vpu) // Todo 312 313// val debugVconfig = dataPath.io.debugVconfig.get.asTypeOf(new VConfig) 314// val debugVtype = VType.toVtypeStruct(debugVconfig.vtype).asUInt 315// val debugVl = debugVconfig.vl 316 csrio.vpu.set_vxsat := ctrlBlock.io.robio.csr.vxsat 317 csrio.vpu.set_vstart.valid := ctrlBlock.io.robio.csr.vstart.valid 318 csrio.vpu.set_vstart.bits := ctrlBlock.io.robio.csr.vstart.bits 319 csrio.vpu.set_vtype.valid := ctrlBlock.io.robio.csr.vcsrFlag 320 //Todo here need change design 321 csrio.vpu.set_vtype.bits := 0.U//ZeroExt(debugVtype, XLEN) 322 csrio.vpu.set_vl.valid := ctrlBlock.io.robio.csr.vcsrFlag 323 csrio.vpu.set_vl.bits := 0.U//ZeroExt(debugVl, XLEN) 324 csrio.exception := ctrlBlock.io.robio.exception 325 csrio.memExceptionVAddr := io.mem.exceptionVAddr 326 csrio.externalInterrupt := io.fromTop.externalInterrupt 327 csrio.distributedUpdate(0) := io.mem.csrDistributedUpdate 328 csrio.distributedUpdate(1) := io.frontendCsrDistributedUpdate 329 csrio.perf <> io.perf 330 csrio.perf.retiredInstr <> ctrlBlock.io.robio.csr.perfinfo.retiredInstr 331 csrio.perf.ctrlInfo <> ctrlBlock.io.perfInfo.ctrlInfo 332 csrio.perf.perfEventsCtrl <> ctrlBlock.getPerf 333 private val fenceio = intExuBlock.io.fenceio.get 334 io.fenceio <> fenceio 335 fenceio.disableSfence := csrio.disableSfence 336 337 vfExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 338 for (i <- 0 until vfExuBlock.io.in.size) { 339 for (j <- 0 until vfExuBlock.io.in(i).size) { 340 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.vf(i)(j).bits.loadDependency, io.mem.ldCancel) 341 NewPipelineConnect( 342 bypassNetwork.io.toExus.vf(i)(j), vfExuBlock.io.in(i)(j), vfExuBlock.io.in(i)(j).fire, 343 Mux( 344 bypassNetwork.io.toExus.vf(i)(j).fire, 345 bypassNetwork.io.toExus.vf(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 346 vfExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 347 ), 348 Option("vfExuBlock2bypassNetwork") 349 ) 350 351 vfExuBlock.io.in(i)(j).bits.vpu.foreach(_.vstart := csrio.vpu.vstart) 352 } 353 } 354 355 intExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 356 vfExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 357 358 wbDataPath.io.flush := ctrlBlock.io.redirect 359 wbDataPath.io.oldVdDataFromDataPath := dataPath.io.vldReadPort.data 360 wbDataPath.io.fromTop.hartId := io.fromTop.hartId 361 wbDataPath.io.fromIntExu <> intExuBlock.io.out 362 wbDataPath.io.fromVfExu <> vfExuBlock.io.out 363 wbDataPath.io.fromMemExu.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 364 sink.valid := source.valid 365 source.ready := sink.ready 366 sink.bits.data := source.bits.data 367 sink.bits.pdest := source.bits.uop.pdest 368 sink.bits.robIdx := source.bits.uop.robIdx 369 sink.bits.intWen.foreach(_ := source.bits.uop.rfWen) 370 sink.bits.fpWen.foreach(_ := source.bits.uop.fpWen) 371 sink.bits.vecWen.foreach(_ := source.bits.uop.vecWen) 372 sink.bits.exceptionVec.foreach(_ := source.bits.uop.exceptionVec) 373 sink.bits.flushPipe.foreach(_ := source.bits.uop.flushPipe) 374 sink.bits.replay.foreach(_ := source.bits.uop.replayInst) 375 sink.bits.debug := source.bits.debug 376 sink.bits.debugInfo := source.bits.uop.debugInfo 377 sink.bits.lqIdx.foreach(_ := source.bits.uop.lqIdx) 378 sink.bits.sqIdx.foreach(_ := source.bits.uop.sqIdx) 379 sink.bits.predecodeInfo.foreach(_ := source.bits.uop.preDecodeInfo) 380 sink.bits.vls.foreach(x => { 381 x.vdIdx := source.bits.vdIdx.get 382 x.vdIdxInField := source.bits.vdIdxInField.get 383 x.vpu := source.bits.uop.vpu 384 x.oldVdPsrc := source.bits.uop.psrc(2) 385 x.isIndexed := VlduType.isIndexed(source.bits.uop.fuOpType) 386 }) 387 sink.bits.trigger.foreach(_ := source.bits.uop.trigger) 388 } 389 390 // to mem 391 private val memIssueParams = params.memSchdParams.get.issueBlockParams 392 private val memExuBlocksHasLDU = memIssueParams.map(_.exuBlockParams.map(x => x.hasLoadFu || x.hasHyldaFu)) 393 println(s"[Backend] memExuBlocksHasLDU: $memExuBlocksHasLDU") 394 395 private val toMem = Wire(bypassNetwork.io.toExus.mem.cloneType) 396 for (i <- toMem.indices) { 397 for (j <- toMem(i).indices) { 398 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.mem(i)(j).bits.loadDependency, io.mem.ldCancel) 399 val issueTimeout = 400 if (memExuBlocksHasLDU(i)(j)) 401 Counter(0 until 16, toMem(i)(j).valid && !toMem(i)(j).fire, bypassNetwork.io.toExus.mem(i)(j).fire)._2 402 else 403 false.B 404 405 if (memScheduler.io.loadFinalIssueResp(i).nonEmpty && memExuBlocksHasLDU(i)(j)) { 406 memScheduler.io.loadFinalIssueResp(i)(j).valid := issueTimeout 407 memScheduler.io.loadFinalIssueResp(i)(j).bits.dataInvalidSqIdx := DontCare 408 memScheduler.io.loadFinalIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType 409 memScheduler.io.loadFinalIssueResp(i)(j).bits.respType := RSFeedbackType.fuBusy 410 memScheduler.io.loadFinalIssueResp(i)(j).bits.rfWen := toMem(i)(j).bits.rfWen.getOrElse(false.B) 411 memScheduler.io.loadFinalIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx 412 memScheduler.io.loadFinalIssueResp(i)(j).bits.uopIdx := toMem(i)(j).bits.vpu.getOrElse(0.U.asTypeOf(new VPUCtrlSignals)).vuopIdx 413 } 414 415 NewPipelineConnect( 416 bypassNetwork.io.toExus.mem(i)(j), toMem(i)(j), toMem(i)(j).fire, 417 Mux( 418 bypassNetwork.io.toExus.mem(i)(j).fire, 419 bypassNetwork.io.toExus.mem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 420 toMem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || issueTimeout 421 ), 422 Option("bypassNetwork2toMemExus") 423 ) 424 425 if (memScheduler.io.memAddrIssueResp(i).nonEmpty && memExuBlocksHasLDU(i)(j)) { 426 memScheduler.io.memAddrIssueResp(i)(j).valid := toMem(i)(j).fire && FuType.isLoad(toMem(i)(j).bits.fuType) 427 memScheduler.io.memAddrIssueResp(i)(j).bits.dataInvalidSqIdx := DontCare 428 memScheduler.io.memAddrIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType 429 memScheduler.io.memAddrIssueResp(i)(j).bits.respType := RSFeedbackType.fuIdle 430 memScheduler.io.memAddrIssueResp(i)(j).bits.rfWen := toMem(i)(j).bits.rfWen.getOrElse(false.B) 431 memScheduler.io.memAddrIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx 432 memScheduler.io.memAddrIssueResp(i)(j).bits.uopIdx := 0.U 433 } 434 } 435 } 436 437 io.mem.redirect := ctrlBlock.io.redirect 438 io.mem.issueUops.zip(toMem.flatten).foreach { case (sink, source) => 439 val enableMdp = Constantin.createRecord("EnableMdp", true.B)(0) 440 sink.valid := source.valid 441 source.ready := sink.ready 442 sink.bits.iqIdx := source.bits.iqIdx 443 sink.bits.isFirstIssue := source.bits.isFirstIssue 444 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 445 sink.bits.src := 0.U.asTypeOf(sink.bits.src) 446 sink.bits.src.zip(source.bits.src).foreach { case (l, r) => l := r} 447 sink.bits.deqPortIdx := source.bits.deqLdExuIdx.getOrElse(0.U) 448 sink.bits.uop.fuType := source.bits.fuType 449 sink.bits.uop.fuOpType := source.bits.fuOpType 450 sink.bits.uop.imm := source.bits.imm 451 sink.bits.uop.robIdx := source.bits.robIdx 452 sink.bits.uop.pdest := source.bits.pdest 453 sink.bits.uop.rfWen := source.bits.rfWen.getOrElse(false.B) 454 sink.bits.uop.fpWen := source.bits.fpWen.getOrElse(false.B) 455 sink.bits.uop.vecWen := source.bits.vecWen.getOrElse(false.B) 456 sink.bits.uop.flushPipe := source.bits.flushPipe.getOrElse(false.B) 457 sink.bits.uop.pc := source.bits.pc.getOrElse(0.U) 458 sink.bits.uop.loadWaitBit := Mux(enableMdp, source.bits.loadWaitBit.getOrElse(false.B), false.B) 459 sink.bits.uop.waitForRobIdx := Mux(enableMdp, source.bits.waitForRobIdx.getOrElse(0.U.asTypeOf(new RobPtr)), 0.U.asTypeOf(new RobPtr)) 460 sink.bits.uop.storeSetHit := Mux(enableMdp, source.bits.storeSetHit.getOrElse(false.B), false.B) 461 sink.bits.uop.loadWaitStrict := Mux(enableMdp, source.bits.loadWaitStrict.getOrElse(false.B), false.B) 462 sink.bits.uop.ssid := Mux(enableMdp, source.bits.ssid.getOrElse(0.U(SSIDWidth.W)), 0.U(SSIDWidth.W)) 463 sink.bits.uop.lqIdx := source.bits.lqIdx.getOrElse(0.U.asTypeOf(new LqPtr)) 464 sink.bits.uop.sqIdx := source.bits.sqIdx.getOrElse(0.U.asTypeOf(new SqPtr)) 465 sink.bits.uop.ftqPtr := source.bits.ftqIdx.getOrElse(0.U.asTypeOf(new FtqPtr)) 466 sink.bits.uop.ftqOffset := source.bits.ftqOffset.getOrElse(0.U) 467 sink.bits.uop.debugInfo := source.bits.perfDebugInfo 468 sink.bits.uop.vpu := source.bits.vpu.getOrElse(0.U.asTypeOf(new VPUCtrlSignals)) 469 sink.bits.uop.preDecodeInfo := source.bits.preDecode.getOrElse(0.U.asTypeOf(new PreDecodeInfo)) 470 } 471 io.mem.loadFastMatch := memScheduler.io.toMem.get.loadFastMatch.map(_.fastMatch) 472 io.mem.loadFastImm := memScheduler.io.toMem.get.loadFastMatch.map(_.fastImm) 473 io.mem.tlbCsr := csrio.tlb 474 io.mem.csrCtrl := csrio.customCtrl 475 io.mem.sfence := fenceio.sfence 476 io.mem.isStoreException := CommitType.lsInstIsStore(ctrlBlock.io.robio.exception.bits.commitType) 477 io.mem.isVlsException := ctrlBlock.io.robio.exception.bits.vls 478 require(io.mem.loadPcRead.size == params.LduCnt) 479 io.mem.loadPcRead.zipWithIndex.foreach { case (loadPcRead, i) => 480 loadPcRead := ctrlBlock.io.memLdPcRead(i).data 481 ctrlBlock.io.memLdPcRead(i).ptr := io.mem.issueLda(i).bits.uop.ftqPtr 482 ctrlBlock.io.memLdPcRead(i).offset := io.mem.issueLda(i).bits.uop.ftqOffset 483 } 484 485 io.mem.storePcRead.zipWithIndex.foreach { case (storePcRead, i) => 486 storePcRead := ctrlBlock.io.memStPcRead(i).data 487 ctrlBlock.io.memStPcRead(i).ptr := io.mem.issueSta(i).bits.uop.ftqPtr 488 ctrlBlock.io.memStPcRead(i).offset := io.mem.issueSta(i).bits.uop.ftqOffset 489 } 490 491 io.mem.hyuPcRead.zipWithIndex.foreach( { case (hyuPcRead, i) => 492 hyuPcRead := ctrlBlock.io.memHyPcRead(i).data 493 ctrlBlock.io.memHyPcRead(i).ptr := io.mem.issueHylda(i).bits.uop.ftqPtr 494 ctrlBlock.io.memHyPcRead(i).offset := io.mem.issueHylda(i).bits.uop.ftqOffset 495 }) 496 497 ctrlBlock.io.robio.robHeadLsIssue := io.mem.issueUops.map(deq => deq.fire && deq.bits.uop.robIdx === ctrlBlock.io.robio.robDeqPtr).reduce(_ || _) 498 499 // mem io 500 io.mem.lsqEnqIO <> memScheduler.io.memIO.get.lsqEnqIO 501 io.mem.robLsqIO <> ctrlBlock.io.robio.lsq 502 503 private val memFinalIssueBlock = io.mem.issueUops zip memExuBlocksHasLDU.flatten map { 504 case (out, isLdu) => 505 if (isLdu) out.valid && !out.ready 506 else false.B 507 } 508 509 println(s"[backend]: width of memFinalIssueBlock: ${memFinalIssueBlock.size}") 510 finalBlockMem.zip(memFinalIssueBlock).foreach(x => x._1 := x._2) 511 512 io.frontendSfence := fenceio.sfence 513 io.frontendTlbCsr := csrio.tlb 514 io.frontendCsrCtrl := csrio.customCtrl 515 516 io.tlb <> csrio.tlb 517 518 io.csrCustomCtrl := csrio.customCtrl 519 520 io.toTop.cpuHalted := false.B // TODO: implement cpu halt 521 522 io.debugTopDown.fromRob := ctrlBlock.io.debugTopDown.fromRob 523 ctrlBlock.io.debugTopDown.fromCore := io.debugTopDown.fromCore 524 525 io.debugRolling := ctrlBlock.io.debugRolling 526 527 if(backendParams.debugEn) { 528 dontTouch(memScheduler.io) 529 dontTouch(dataPath.io.toMemExu) 530 dontTouch(wbDataPath.io.fromMemExu) 531 } 532} 533 534class BackendMemIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 535 // Since fast load replay always use load unit 0, Backend flips two load port to avoid conflicts 536 val flippedLda = true 537 // params alias 538 private val LoadQueueSize = VirtualLoadQueueSize 539 // In/Out // Todo: split it into one-direction bundle 540 val lsqEnqIO = Flipped(new LsqEnqIO) 541 val robLsqIO = new RobLsqIO 542 val ldaIqFeedback = Vec(params.LduCnt, Flipped(new MemRSFeedbackIO)) 543 val staIqFeedback = Vec(params.StaCnt, Flipped(new MemRSFeedbackIO)) 544 val hyuIqFeedback = Vec(params.HyuCnt, Flipped(new MemRSFeedbackIO)) 545 val ldCancel = Vec(params.LduCnt + params.HyuCnt, Flipped(new LoadCancelIO)) 546 val loadPcRead = Vec(params.LduCnt, Output(UInt(VAddrBits.W))) 547 val storePcRead = Vec(params.StaCnt, Output(UInt(VAddrBits.W))) 548 val hyuPcRead = Vec(params.HyuCnt, Output(UInt(VAddrBits.W))) 549 // Input 550 val writebackLda = Vec(params.LduCnt, Flipped(DecoupledIO(new MemExuOutput))) 551 val writebackSta = Vec(params.StaCnt, Flipped(DecoupledIO(new MemExuOutput))) 552 val writebackStd = Vec(params.StdCnt, Flipped(DecoupledIO(new MemExuOutput))) 553 val writebackHyuLda = Vec(params.HyuCnt, Flipped(DecoupledIO(new MemExuOutput))) 554 val writebackHyuSta = Vec(params.HyuCnt, Flipped(DecoupledIO(new MemExuOutput))) 555 val writebackVldu = Vec(params.VlduCnt, Flipped(DecoupledIO(new MemExuOutput(true)))) 556 557 val s3_delayed_load_error = Input(Vec(LoadPipelineWidth, Bool())) 558 val stIn = Input(Vec(params.StaExuCnt, ValidIO(new DynInst()))) 559 val memoryViolation = Flipped(ValidIO(new Redirect)) 560 val exceptionVAddr = Input(UInt(VAddrBits.W)) 561 val sqDeq = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) 562 val lqDeq = Input(UInt(log2Up(CommitWidth + 1).W)) 563 val sqDeqPtr = Input(new SqPtr) 564 val lqDeqPtr = Input(new LqPtr) 565 566 val lqCancelCnt = Input(UInt(log2Up(VirtualLoadQueueSize + 1).W)) 567 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 568 569 val lqCanAccept = Input(Bool()) 570 val sqCanAccept = Input(Bool()) 571 572 val otherFastWakeup = Flipped(Vec(params.LduCnt + params.HyuCnt, ValidIO(new DynInst))) 573 val stIssuePtr = Input(new SqPtr()) 574 575 val csrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 576 577 val debugLS = Flipped(Output(new DebugLSIO)) 578 579 val lsTopdownInfo = Vec(params.LduCnt + params.HyuCnt, Flipped(Output(new LsTopdownInfo))) 580 // Output 581 val redirect = ValidIO(new Redirect) // rob flush MemBlock 582 val issueLda = MixedVec(Seq.fill(params.LduCnt)(DecoupledIO(new MemExuInput()))) 583 val issueSta = MixedVec(Seq.fill(params.StaCnt)(DecoupledIO(new MemExuInput()))) 584 val issueStd = MixedVec(Seq.fill(params.StdCnt)(DecoupledIO(new MemExuInput()))) 585 val issueHylda = MixedVec(Seq.fill(params.HyuCnt)(DecoupledIO(new MemExuInput()))) 586 val issueHysta = MixedVec(Seq.fill(params.HyuCnt)(DecoupledIO(new MemExuInput()))) 587 val issueVldu = MixedVec(Seq.fill(params.VlduCnt)(DecoupledIO(new MemExuInput(true)))) 588 589 val loadFastMatch = Vec(params.LduCnt, Output(UInt(params.LduCnt.W))) 590 val loadFastImm = Vec(params.LduCnt, Output(UInt(12.W))) // Imm_I 591 592 val tlbCsr = Output(new TlbCsrBundle) 593 val csrCtrl = Output(new CustomCSRCtrlIO) 594 val sfence = Output(new SfenceBundle) 595 val isStoreException = Output(Bool()) 596 val isVlsException = Output(Bool()) 597 598 // ATTENTION: The issue ports' sequence order should be the same as IQs' deq config 599 private [backend] def issueUops: Seq[DecoupledIO[MemExuInput]] = { 600 issueSta ++ 601 issueHylda ++ issueHysta ++ 602 issueLda ++ 603 issueVldu ++ 604 issueStd 605 }.toSeq 606 607 // ATTENTION: The writeback ports' sequence order should be the same as IQs' deq config 608 private [backend] def writeBack: Seq[DecoupledIO[MemExuOutput]] = { 609 writebackSta ++ 610 writebackHyuLda ++ writebackHyuSta ++ 611 writebackLda ++ 612 writebackVldu ++ 613 writebackStd 614 } 615} 616 617class BackendIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 618 val fromTop = new Bundle { 619 val hartId = Input(UInt(8.W)) 620 val externalInterrupt = new ExternalInterruptIO 621 } 622 623 val toTop = new Bundle { 624 val cpuHalted = Output(Bool()) 625 } 626 627 val fenceio = new FenceIO 628 // Todo: merge these bundles into BackendFrontendIO 629 val frontend = Flipped(new FrontendToCtrlIO) 630 val frontendSfence = Output(new SfenceBundle) 631 val frontendCsrCtrl = Output(new CustomCSRCtrlIO) 632 val frontendTlbCsr = Output(new TlbCsrBundle) 633 // distributed csr write 634 val frontendCsrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 635 636 val mem = new BackendMemIO 637 638 val perf = Input(new PerfCounterIO) 639 640 val tlb = Output(new TlbCsrBundle) 641 642 val csrCustomCtrl = Output(new CustomCSRCtrlIO) 643 644 val debugTopDown = new Bundle { 645 val fromRob = new RobCoreTopDownIO 646 val fromCore = new CoreDispatchTopDownIO 647 } 648 val debugRolling = new RobDebugRollingIO 649} 650