1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import device.MsiInfoBundle 23import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 24import system.HasSoCParameter 25import utility._ 26import xiangshan._ 27import xiangshan.backend.Bundles.{DynInst, IssueQueueIQWakeUpBundle, LoadShouldCancel, MemExuInput, MemExuOutput, VPUCtrlSignals} 28import xiangshan.backend.ctrlblock.{DebugLSIO, LsTopdownInfo} 29import xiangshan.backend.datapath.DataConfig.{IntData, VecData, FpData} 30import xiangshan.backend.datapath.RdConfig.{IntRD, VfRD} 31import xiangshan.backend.datapath.WbConfig._ 32import xiangshan.backend.datapath.DataConfig._ 33import xiangshan.backend.datapath._ 34import xiangshan.backend.dispatch.CoreDispatchTopDownIO 35import xiangshan.backend.exu.ExuBlock 36import xiangshan.backend.fu.vector.Bundles.{VConfig, VType} 37import xiangshan.backend.fu.{FenceIO, FenceToSbuffer, FuConfig, FuType, PFEvent, PerfCounterIO} 38import xiangshan.backend.issue.EntryBundles._ 39import xiangshan.backend.issue.{CancelNetwork, Scheduler, SchedulerArithImp, SchedulerImpBase, SchedulerMemImp} 40import xiangshan.backend.rob.{RobCoreTopDownIO, RobDebugRollingIO, RobLsqIO, RobPtr} 41import xiangshan.frontend.{FtqPtr, FtqRead, PreDecodeInfo} 42import xiangshan.mem.{LqPtr, LsqEnqIO, SqPtr} 43 44import scala.collection.mutable 45 46class Backend(val params: BackendParams)(implicit p: Parameters) extends LazyModule 47 with HasXSParameter { 48 override def shouldBeInlined: Boolean = false 49 val inner = LazyModule(new BackendInlined(params)) 50 lazy val module = new BackendImp(this) 51} 52 53class BackendImp(wrapper: Backend)(implicit p: Parameters) extends LazyModuleImp(wrapper) { 54 val io = IO(new BackendIO()(p, wrapper.params)) 55 io <> wrapper.inner.module.io 56 if (p(DebugOptionsKey).ResetGen) { 57 ResetGen(ResetGenNode(Seq(ModuleNode(wrapper.inner.module))), reset, sim = false) 58 } 59} 60 61class BackendInlined(val params: BackendParams)(implicit p: Parameters) extends LazyModule 62 with HasXSParameter { 63 64 override def shouldBeInlined: Boolean = true 65 66 // check read & write port config 67 params.configChecks 68 69 /* Only update the idx in mem-scheduler here 70 * Idx in other schedulers can be updated the same way if needed 71 * 72 * Also note that we filter out the 'stData issue-queues' when counting 73 */ 74 for ((ibp, idx) <- params.memSchdParams.get.issueBlockParams.filter(iq => iq.StdCnt == 0).zipWithIndex) { 75 ibp.updateIdx(idx) 76 } 77 78 println(params.iqWakeUpParams) 79 80 for ((schdCfg, i) <- params.allSchdParams.zipWithIndex) { 81 schdCfg.bindBackendParam(params) 82 } 83 84 for ((iqCfg, i) <- params.allIssueParams.zipWithIndex) { 85 iqCfg.bindBackendParam(params) 86 } 87 88 for ((exuCfg, i) <- params.allExuParams.zipWithIndex) { 89 exuCfg.bindBackendParam(params) 90 exuCfg.updateIQWakeUpConfigs(params.iqWakeUpParams) 91 exuCfg.updateExuIdx(i) 92 } 93 94 println("[Backend] ExuConfigs:") 95 for (exuCfg <- params.allExuParams) { 96 val fuConfigs = exuCfg.fuConfigs 97 val wbPortConfigs = exuCfg.wbPortConfigs 98 val immType = exuCfg.immType 99 100 println("[Backend] " + 101 s"${exuCfg.name}: " + 102 (if (exuCfg.fakeUnit) "fake, " else "") + 103 (if (exuCfg.hasLoadFu || exuCfg.hasHyldaFu) s"LdExuIdx(${backendParams.getLdExuIdx(exuCfg)})" else "") + 104 s"${fuConfigs.map(_.name).mkString("fu(s): {", ",", "}")}, " + 105 s"${wbPortConfigs.mkString("wb: {", ",", "}")}, " + 106 s"${immType.map(SelImm.mkString(_)).mkString("imm: {", ",", "}")}, " + 107 s"latMax(${exuCfg.latencyValMax}), ${exuCfg.fuLatancySet.mkString("lat: {", ",", "}")}, " + 108 s"srcReg(${exuCfg.numRegSrc})" 109 ) 110 require( 111 wbPortConfigs.collectFirst { case x: IntWB => x }.nonEmpty == 112 fuConfigs.map(_.writeIntRf).reduce(_ || _), 113 s"${exuCfg.name} int wb port has no priority" 114 ) 115 require( 116 wbPortConfigs.collectFirst { case x: FpWB => x }.nonEmpty == 117 fuConfigs.map(x => x.writeFpRf).reduce(_ || _), 118 s"${exuCfg.name} fp wb port has no priority" 119 ) 120 require( 121 wbPortConfigs.collectFirst { case x: VfWB => x }.nonEmpty == 122 fuConfigs.map(x => x.writeVecRf).reduce(_ || _), 123 s"${exuCfg.name} vec wb port has no priority" 124 ) 125 } 126 127 println(s"[Backend] all fu configs") 128 for (cfg <- FuConfig.allConfigs) { 129 println(s"[Backend] $cfg") 130 } 131 132 println(s"[Backend] Int RdConfigs: ExuName(Priority)") 133 for ((port, seq) <- params.getRdPortParams(IntData())) { 134 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 135 } 136 137 println(s"[Backend] Int WbConfigs: ExuName(Priority)") 138 for ((port, seq) <- params.getWbPortParams(IntData())) { 139 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 140 } 141 142 println(s"[Backend] Fp RdConfigs: ExuName(Priority)") 143 for ((port, seq) <- params.getRdPortParams(FpData())) { 144 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 145 } 146 147 println(s"[Backend] Fp WbConfigs: ExuName(Priority)") 148 for ((port, seq) <- params.getWbPortParams(FpData())) { 149 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 150 } 151 152 println(s"[Backend] Vf RdConfigs: ExuName(Priority)") 153 for ((port, seq) <- params.getRdPortParams(VecData())) { 154 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 155 } 156 157 println(s"[Backend] Vf WbConfigs: ExuName(Priority)") 158 for ((port, seq) <- params.getWbPortParams(VecData())) { 159 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 160 } 161 162 println(s"[Backend] Dispatch Configs:") 163 println(s"[Backend] Load IQ enq width(${params.numLoadDp}), Store IQ enq width(${params.numStoreDp})") 164 println(s"[Backend] Load DP width(${LSQLdEnqWidth}), Store DP width(${LSQStEnqWidth})") 165 166 params.updateCopyPdestInfo 167 println(s"[Backend] copyPdestInfo ${params.copyPdestInfo}") 168 params.allExuParams.map(_.copyNum) 169 val ctrlBlock = LazyModule(new CtrlBlock(params)) 170 val pcTargetMem = LazyModule(new PcTargetMem(params)) 171 val intScheduler = params.intSchdParams.map(x => LazyModule(new Scheduler(x))) 172 val fpScheduler = params.fpSchdParams.map(x => LazyModule(new Scheduler(x))) 173 val vfScheduler = params.vfSchdParams.map(x => LazyModule(new Scheduler(x))) 174 val memScheduler = params.memSchdParams.map(x => LazyModule(new Scheduler(x))) 175 val dataPath = LazyModule(new DataPath(params)) 176 val intExuBlock = params.intSchdParams.map(x => LazyModule(new ExuBlock(x))) 177 val fpExuBlock = params.fpSchdParams.map(x => LazyModule(new ExuBlock(x))) 178 val vfExuBlock = params.vfSchdParams.map(x => LazyModule(new ExuBlock(x))) 179 val wbFuBusyTable = LazyModule(new WbFuBusyTable(params)) 180 181 lazy val module = new BackendInlinedImp(this) 182} 183 184class BackendInlinedImp(override val wrapper: BackendInlined)(implicit p: Parameters) extends LazyModuleImp(wrapper) 185 with HasXSParameter 186 with HasPerfEvents { 187 implicit private val params: BackendParams = wrapper.params 188 189 val io = IO(new BackendIO()(p, wrapper.params)) 190 191 private val ctrlBlock = wrapper.ctrlBlock.module 192 private val pcTargetMem = wrapper.pcTargetMem.module 193 private val intScheduler: SchedulerImpBase = wrapper.intScheduler.get.module 194 private val fpScheduler = wrapper.fpScheduler.get.module 195 private val vfScheduler = wrapper.vfScheduler.get.module 196 private val memScheduler = wrapper.memScheduler.get.module 197 private val dataPath = wrapper.dataPath.module 198 private val intExuBlock = wrapper.intExuBlock.get.module 199 private val fpExuBlock = wrapper.fpExuBlock.get.module 200 private val vfExuBlock = wrapper.vfExuBlock.get.module 201 private val og2ForVector = Module(new Og2ForVector(params)) 202 private val bypassNetwork = Module(new BypassNetwork) 203 private val wbDataPath = Module(new WbDataPath(params)) 204 private val wbFuBusyTable = wrapper.wbFuBusyTable.module 205 private val vecExcpMod = Module(new VecExcpDataMergeModule) 206 207 private val iqWakeUpMappedBundle: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = ( 208 intScheduler.io.toSchedulers.wakeupVec ++ 209 fpScheduler.io.toSchedulers.wakeupVec ++ 210 vfScheduler.io.toSchedulers.wakeupVec ++ 211 memScheduler.io.toSchedulers.wakeupVec 212 ).map(x => (x.bits.exuIdx, x)).toMap 213 214 println(s"[Backend] iq wake up keys: ${iqWakeUpMappedBundle.keys}") 215 216 wbFuBusyTable.io.in.intSchdBusyTable := intScheduler.io.wbFuBusyTable 217 wbFuBusyTable.io.in.fpSchdBusyTable := fpScheduler.io.wbFuBusyTable 218 wbFuBusyTable.io.in.vfSchdBusyTable := vfScheduler.io.wbFuBusyTable 219 wbFuBusyTable.io.in.memSchdBusyTable := memScheduler.io.wbFuBusyTable 220 intScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.intRespRead 221 fpScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.fpRespRead 222 vfScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.vfRespRead 223 memScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.memRespRead 224 dataPath.io.wbConfictRead := wbFuBusyTable.io.out.wbConflictRead 225 226 private val og1Cancel = dataPath.io.og1Cancel 227 private val og0Cancel = dataPath.io.og0Cancel 228 private val vlFromIntIsZero = intExuBlock.io.vlIsZero.get 229 private val vlFromIntIsVlmax = intExuBlock.io.vlIsVlmax.get 230 private val vlFromVfIsZero = vfExuBlock.io.vlIsZero.get 231 private val vlFromVfIsVlmax = vfExuBlock.io.vlIsVlmax.get 232 233 ctrlBlock.io.intIQValidNumVec := intScheduler.io.intIQValidNumVec 234 ctrlBlock.io.fpIQValidNumVec := fpScheduler.io.fpIQValidNumVec 235 ctrlBlock.io.fromTop.hartId := io.fromTop.hartId 236 ctrlBlock.io.frontend <> io.frontend 237 ctrlBlock.io.fromCSR.toDecode := intExuBlock.io.csrToDecode.get 238 ctrlBlock.io.fromWB.wbData <> wbDataPath.io.toCtrlBlock.writeback 239 ctrlBlock.io.fromMem.stIn <> io.mem.stIn 240 ctrlBlock.io.fromMem.violation <> io.mem.memoryViolation 241 ctrlBlock.io.lqCanAccept := io.mem.lqCanAccept 242 ctrlBlock.io.sqCanAccept := io.mem.sqCanAccept 243 ctrlBlock.io.csrCtrl <> intExuBlock.io.csrio.get.customCtrl 244 ctrlBlock.io.robio.csr.intrBitSet := intExuBlock.io.csrio.get.interrupt 245 ctrlBlock.io.robio.csr.trapTarget := intExuBlock.io.csrio.get.trapTarget 246 ctrlBlock.io.robio.csr.isXRet := intExuBlock.io.csrio.get.isXRet 247 ctrlBlock.io.robio.csr.wfiEvent := intExuBlock.io.csrio.get.wfi_event 248 ctrlBlock.io.robio.lsq <> io.mem.robLsqIO 249 ctrlBlock.io.robio.lsTopdownInfo <> io.mem.lsTopdownInfo 250 ctrlBlock.io.robio.debug_ls <> io.mem.debugLS 251 ctrlBlock.io.debugEnqLsq.canAccept := io.mem.lsqEnqIO.canAccept 252 ctrlBlock.io.debugEnqLsq.resp := io.mem.lsqEnqIO.resp 253 ctrlBlock.io.debugEnqLsq.req := memScheduler.io.memIO.get.lsqEnqIO.req 254 ctrlBlock.io.debugEnqLsq.needAlloc := memScheduler.io.memIO.get.lsqEnqIO.needAlloc 255 ctrlBlock.io.debugEnqLsq.iqAccept := memScheduler.io.memIO.get.lsqEnqIO.iqAccept 256 ctrlBlock.io.fromVecExcpMod.busy := vecExcpMod.o.status.busy 257 258 intScheduler.io.fromTop.hartId := io.fromTop.hartId 259 intScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 260 intScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 261 intScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.intUops 262 intScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 263 intScheduler.io.fpWriteBack := 0.U.asTypeOf(intScheduler.io.fpWriteBack) 264 intScheduler.io.vfWriteBack := 0.U.asTypeOf(intScheduler.io.vfWriteBack) 265 intScheduler.io.v0WriteBack := 0.U.asTypeOf(intScheduler.io.v0WriteBack) 266 intScheduler.io.vlWriteBack := 0.U.asTypeOf(intScheduler.io.vlWriteBack) 267 intScheduler.io.fromDataPath.resp := dataPath.io.toIntIQ 268 intScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 269 intScheduler.io.fromDataPath.og0Cancel := og0Cancel 270 intScheduler.io.fromDataPath.og1Cancel := og1Cancel 271 intScheduler.io.ldCancel := io.mem.ldCancel 272 intScheduler.io.fromDataPath.replaceRCIdx.get := dataPath.io.toWakeupQueueRCIdx.take(params.getIntExuRCWriteSize) 273 intScheduler.io.vlWriteBackInfo.vlFromIntIsZero := false.B 274 intScheduler.io.vlWriteBackInfo.vlFromIntIsVlmax := false.B 275 intScheduler.io.vlWriteBackInfo.vlFromVfIsZero := false.B 276 intScheduler.io.vlWriteBackInfo.vlFromVfIsVlmax := false.B 277 278 fpScheduler.io.fromTop.hartId := io.fromTop.hartId 279 fpScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 280 fpScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 281 fpScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.fpUops 282 fpScheduler.io.intWriteBack := 0.U.asTypeOf(fpScheduler.io.intWriteBack) 283 fpScheduler.io.fpWriteBack := wbDataPath.io.toFpPreg 284 fpScheduler.io.vfWriteBack := 0.U.asTypeOf(fpScheduler.io.vfWriteBack) 285 fpScheduler.io.v0WriteBack := 0.U.asTypeOf(fpScheduler.io.v0WriteBack) 286 fpScheduler.io.vlWriteBack := 0.U.asTypeOf(fpScheduler.io.vlWriteBack) 287 fpScheduler.io.fromDataPath.resp := dataPath.io.toFpIQ 288 fpScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 289 fpScheduler.io.fromDataPath.og0Cancel := og0Cancel 290 fpScheduler.io.fromDataPath.og1Cancel := og1Cancel 291 fpScheduler.io.ldCancel := io.mem.ldCancel 292 fpScheduler.io.vlWriteBackInfo.vlFromIntIsZero := false.B 293 fpScheduler.io.vlWriteBackInfo.vlFromIntIsVlmax := false.B 294 fpScheduler.io.vlWriteBackInfo.vlFromVfIsZero := false.B 295 fpScheduler.io.vlWriteBackInfo.vlFromVfIsVlmax := false.B 296 297 memScheduler.io.fromTop.hartId := io.fromTop.hartId 298 memScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 299 memScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 300 memScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.memUops 301 memScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 302 memScheduler.io.fpWriteBack := wbDataPath.io.toFpPreg 303 memScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 304 memScheduler.io.v0WriteBack := wbDataPath.io.toV0Preg 305 memScheduler.io.vlWriteBack := wbDataPath.io.toVlPreg 306 memScheduler.io.fromMem.get.scommit := io.mem.sqDeq 307 memScheduler.io.fromMem.get.lcommit := io.mem.lqDeq 308 memScheduler.io.fromMem.get.wakeup := io.mem.wakeup 309 memScheduler.io.fromMem.get.sqDeqPtr := io.mem.sqDeqPtr 310 memScheduler.io.fromMem.get.lqDeqPtr := io.mem.lqDeqPtr 311 memScheduler.io.fromMem.get.sqCancelCnt := io.mem.sqCancelCnt 312 memScheduler.io.fromMem.get.lqCancelCnt := io.mem.lqCancelCnt 313 memScheduler.io.fromMem.get.stIssuePtr := io.mem.stIssuePtr 314 require(memScheduler.io.fromMem.get.memWaitUpdateReq.robIdx.length == io.mem.stIn.length) 315 memScheduler.io.fromMem.get.memWaitUpdateReq.robIdx.zip(io.mem.stIn).foreach { case (sink, source) => 316 sink.valid := source.valid 317 sink.bits := source.bits.robIdx 318 } 319 memScheduler.io.fromMem.get.memWaitUpdateReq.sqIdx := DontCare // TODO 320 memScheduler.io.fromDataPath.resp := dataPath.io.toMemIQ 321 memScheduler.io.fromMem.get.ldaFeedback := io.mem.ldaIqFeedback 322 memScheduler.io.fromMem.get.staFeedback := io.mem.staIqFeedback 323 memScheduler.io.fromMem.get.hyuFeedback := io.mem.hyuIqFeedback 324 memScheduler.io.fromMem.get.vstuFeedback := io.mem.vstuIqFeedback 325 memScheduler.io.fromMem.get.vlduFeedback := io.mem.vlduIqFeedback 326 memScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 327 memScheduler.io.fromDataPath.og0Cancel := og0Cancel 328 memScheduler.io.fromDataPath.og1Cancel := og1Cancel 329 memScheduler.io.ldCancel := io.mem.ldCancel 330 memScheduler.io.fromDataPath.replaceRCIdx.get := dataPath.io.toWakeupQueueRCIdx.takeRight(params.getMemExuRCWriteSize) 331 memScheduler.io.vlWriteBackInfo.vlFromIntIsZero := vlFromIntIsZero 332 memScheduler.io.vlWriteBackInfo.vlFromIntIsVlmax := vlFromIntIsVlmax 333 memScheduler.io.vlWriteBackInfo.vlFromVfIsZero := vlFromVfIsZero 334 memScheduler.io.vlWriteBackInfo.vlFromVfIsVlmax := vlFromVfIsVlmax 335 memScheduler.io.fromOg2Resp.get := og2ForVector.io.toMemIQOg2Resp 336 337 vfScheduler.io.fromTop.hartId := io.fromTop.hartId 338 vfScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 339 vfScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 340 vfScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.vfUops 341 vfScheduler.io.intWriteBack := 0.U.asTypeOf(vfScheduler.io.intWriteBack) 342 vfScheduler.io.fpWriteBack := 0.U.asTypeOf(vfScheduler.io.fpWriteBack) 343 vfScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 344 vfScheduler.io.v0WriteBack := wbDataPath.io.toV0Preg 345 vfScheduler.io.vlWriteBack := wbDataPath.io.toVlPreg 346 vfScheduler.io.fromDataPath.resp := dataPath.io.toVfIQ 347 vfScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 348 vfScheduler.io.fromDataPath.og0Cancel := og0Cancel 349 vfScheduler.io.fromDataPath.og1Cancel := og1Cancel 350 vfScheduler.io.ldCancel := io.mem.ldCancel 351 vfScheduler.io.vlWriteBackInfo.vlFromIntIsZero := vlFromIntIsZero 352 vfScheduler.io.vlWriteBackInfo.vlFromIntIsVlmax := vlFromIntIsVlmax 353 vfScheduler.io.vlWriteBackInfo.vlFromVfIsZero := vlFromVfIsZero 354 vfScheduler.io.vlWriteBackInfo.vlFromVfIsVlmax := vlFromVfIsVlmax 355 vfScheduler.io.fromOg2Resp.get := og2ForVector.io.toVfIQOg2Resp 356 357 dataPath.io.hartId := io.fromTop.hartId 358 dataPath.io.flush := ctrlBlock.io.toDataPath.flush 359 360 dataPath.io.fromIntIQ <> intScheduler.io.toDataPathAfterDelay 361 dataPath.io.fromFpIQ <> fpScheduler.io.toDataPathAfterDelay 362 dataPath.io.fromVfIQ <> vfScheduler.io.toDataPathAfterDelay 363 dataPath.io.fromMemIQ <> memScheduler.io.toDataPathAfterDelay 364 365 dataPath.io.ldCancel := io.mem.ldCancel 366 367 println(s"[Backend] wbDataPath.io.toIntPreg: ${wbDataPath.io.toIntPreg.size}, dataPath.io.fromIntWb: ${dataPath.io.fromIntWb.size}") 368 println(s"[Backend] wbDataPath.io.toVfPreg: ${wbDataPath.io.toVfPreg.size}, dataPath.io.fromFpWb: ${dataPath.io.fromVfWb.size}") 369 dataPath.io.fromIntWb := wbDataPath.io.toIntPreg 370 dataPath.io.fromFpWb := wbDataPath.io.toFpPreg 371 dataPath.io.fromVfWb := wbDataPath.io.toVfPreg 372 dataPath.io.fromV0Wb := wbDataPath.io.toV0Preg 373 dataPath.io.fromVlWb := wbDataPath.io.toVlPreg 374 dataPath.io.diffIntRat.foreach(_ := ctrlBlock.io.diff_int_rat.get) 375 dataPath.io.diffFpRat .foreach(_ := ctrlBlock.io.diff_fp_rat.get) 376 dataPath.io.diffVecRat.foreach(_ := ctrlBlock.io.diff_vec_rat.get) 377 dataPath.io.diffV0Rat .foreach(_ := ctrlBlock.io.diff_v0_rat.get) 378 dataPath.io.diffVlRat .foreach(_ := ctrlBlock.io.diff_vl_rat.get) 379 dataPath.io.fromBypassNetwork := bypassNetwork.io.toDataPath 380 dataPath.io.fromVecExcpMod.r := vecExcpMod.o.toVPRF.r 381 dataPath.io.fromVecExcpMod.w := vecExcpMod.o.toVPRF.w 382 383 og2ForVector.io.flush := ctrlBlock.io.toDataPath.flush 384 og2ForVector.io.ldCancel := io.mem.ldCancel 385 og2ForVector.io.fromOg1VfArith <> dataPath.io.toVecExu 386 og2ForVector.io.fromOg1VecMem.zip(dataPath.io.toMemExu.zip(params.memSchdParams.get.issueBlockParams).filter(_._2.needOg2Resp).map(_._1)) 387 .foreach { 388 case (og1Mem, datapathMem) => og1Mem <> datapathMem 389 } 390 og2ForVector.io.fromOg1ImmInfo := dataPath.io.og1ImmInfo.zip(params.allExuParams).filter(_._2.needOg2).map(_._1) 391 392 println(s"[Backend] BypassNetwork OG1 Mem Size: ${bypassNetwork.io.fromDataPath.mem.zip(params.memSchdParams.get.issueBlockParams).filterNot(_._2.needOg2Resp).size}") 393 println(s"[Backend] BypassNetwork OG2 Mem Size: ${bypassNetwork.io.fromDataPath.mem.zip(params.memSchdParams.get.issueBlockParams).filter(_._2.needOg2Resp).size}") 394 println(s"[Backend] bypassNetwork.io.fromDataPath.mem: ${bypassNetwork.io.fromDataPath.mem.size}, dataPath.io.toMemExu: ${dataPath.io.toMemExu.size}") 395 bypassNetwork.io.fromDataPath.int <> dataPath.io.toIntExu 396 bypassNetwork.io.fromDataPath.fp <> dataPath.io.toFpExu 397 bypassNetwork.io.fromDataPath.vf <> og2ForVector.io.toVfArithExu 398 bypassNetwork.io.fromDataPath.mem.lazyZip(params.memSchdParams.get.issueBlockParams).lazyZip(dataPath.io.toMemExu).filterNot(_._2.needOg2Resp) 399 .map(x => (x._1, x._3)).foreach { 400 case (bypassMem, datapathMem) => bypassMem <> datapathMem 401 } 402 bypassNetwork.io.fromDataPath.mem.zip(params.memSchdParams.get.issueBlockParams).filter(_._2.needOg2Resp).map(_._1) 403 .zip(og2ForVector.io.toVecMemExu).foreach { 404 case (bypassMem, og2Mem) => bypassMem <> og2Mem 405 } 406 bypassNetwork.io.fromDataPath.immInfo := dataPath.io.og1ImmInfo 407 bypassNetwork.io.fromDataPath.immInfo.zip(params.allExuParams).filter(_._2.needOg2).map(_._1) 408 .zip(og2ForVector.io.toBypassNetworkImmInfo).foreach { 409 case (immInfo, og2ImmInfo) => immInfo := og2ImmInfo 410 } 411 bypassNetwork.io.fromDataPath.rcData := dataPath.io.toBypassNetworkRCData 412 bypassNetwork.io.fromExus.connectExuOutput(_.int)(intExuBlock.io.out) 413 bypassNetwork.io.fromExus.connectExuOutput(_.fp)(fpExuBlock.io.out) 414 bypassNetwork.io.fromExus.connectExuOutput(_.vf)(vfExuBlock.io.out) 415 416 require(bypassNetwork.io.fromExus.mem.flatten.size == io.mem.writeBack.size, 417 s"bypassNetwork.io.fromExus.mem.flatten.size(${bypassNetwork.io.fromExus.mem.flatten.size}: ${bypassNetwork.io.fromExus.mem.map(_.size)}, " + 418 s"io.mem.writeback(${io.mem.writeBack.size})" 419 ) 420 bypassNetwork.io.fromExus.mem.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 421 sink.valid := source.valid 422 sink.bits.intWen := source.bits.uop.rfWen && FuType.isLoad(source.bits.uop.fuType) 423 sink.bits.pdest := source.bits.uop.pdest 424 sink.bits.data := source.bits.data 425 } 426 427 428 intExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 429 for (i <- 0 until intExuBlock.io.in.length) { 430 for (j <- 0 until intExuBlock.io.in(i).length) { 431 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.int(i)(j).bits.loadDependency, io.mem.ldCancel) 432 NewPipelineConnect( 433 bypassNetwork.io.toExus.int(i)(j), intExuBlock.io.in(i)(j), intExuBlock.io.in(i)(j).fire, 434 Mux( 435 bypassNetwork.io.toExus.int(i)(j).fire, 436 bypassNetwork.io.toExus.int(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 437 intExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 438 ), 439 Option("bypassNetwork2intExuBlock") 440 ) 441 } 442 } 443 444 pcTargetMem.io.fromFrontendFtq := io.frontend.fromFtq 445 pcTargetMem.io.toDataPath <> dataPath.io.fromPcTargetMem 446 447 private val csrin = intExuBlock.io.csrin.get 448 csrin.hartId := io.fromTop.hartId 449 csrin.msiInfo.valid := RegNext(io.fromTop.msiInfo.valid) 450 csrin.msiInfo.bits := RegEnable(io.fromTop.msiInfo.bits, io.fromTop.msiInfo.valid) 451 csrin.clintTime.valid := RegNext(io.fromTop.clintTime.valid) 452 csrin.clintTime.bits := RegEnable(io.fromTop.clintTime.bits, io.fromTop.clintTime.valid) 453 csrin.trapInstInfo := ctrlBlock.io.toCSR.trapInstInfo 454 csrin.fromVecExcpMod.busy := vecExcpMod.o.status.busy 455 456 private val csrio = intExuBlock.io.csrio.get 457 csrio.hartId := io.fromTop.hartId 458 csrio.fpu.fflags := ctrlBlock.io.robio.csr.fflags 459 csrio.fpu.isIllegal := false.B // Todo: remove it 460 csrio.fpu.dirty_fs := ctrlBlock.io.robio.csr.dirty_fs 461 csrio.vpu <> WireDefault(0.U.asTypeOf(csrio.vpu)) // Todo 462 463 val fromIntExuVsetVType = intExuBlock.io.vtype.getOrElse(0.U.asTypeOf((Valid(new VType)))) 464 val fromVfExuVsetVType = vfExuBlock.io.vtype.getOrElse(0.U.asTypeOf((Valid(new VType)))) 465 val fromVsetVType = Mux(fromIntExuVsetVType.valid, fromIntExuVsetVType.bits, fromVfExuVsetVType.bits) 466 val vsetvlVType = RegEnable(fromVsetVType, 0.U.asTypeOf(new VType), fromIntExuVsetVType.valid || fromVfExuVsetVType.valid) 467 ctrlBlock.io.toDecode.vsetvlVType := vsetvlVType 468 469 val commitVType = ctrlBlock.io.robio.commitVType.vtype 470 val hasVsetvl = ctrlBlock.io.robio.commitVType.hasVsetvl 471 val vtype = VType.toVtypeStruct(Mux(hasVsetvl, vsetvlVType, commitVType.bits)).asUInt 472 473 // csr not store the value of vl, so when using difftest we assign the value of vl to debugVl 474 val debugVl_s0 = WireInit(UInt(VlData().dataWidth.W), 0.U) 475 val debugVl_s1 = WireInit(UInt(VlData().dataWidth.W), 0.U) 476 debugVl_s0 := dataPath.io.diffVl.getOrElse(0.U.asTypeOf(UInt(VlData().dataWidth.W))) 477 debugVl_s1 := RegNext(debugVl_s0) 478 csrio.vpu.set_vxsat := ctrlBlock.io.robio.csr.vxsat 479 csrio.vpu.set_vstart.valid := ctrlBlock.io.robio.csr.vstart.valid 480 csrio.vpu.set_vstart.bits := ctrlBlock.io.robio.csr.vstart.bits 481 ctrlBlock.io.toDecode.vstart := csrio.vpu.vstart 482 //Todo here need change design 483 csrio.vpu.set_vtype.valid := commitVType.valid 484 csrio.vpu.set_vtype.bits := ZeroExt(vtype, XLEN) 485 csrio.vpu.vl := ZeroExt(debugVl_s1, XLEN) 486 csrio.vpu.dirty_vs := ctrlBlock.io.robio.csr.dirty_vs 487 csrio.exception := ctrlBlock.io.robio.exception 488 csrio.robDeqPtr := ctrlBlock.io.robio.robDeqPtr 489 csrio.memExceptionVAddr := io.mem.exceptionAddr.vaddr 490 csrio.memExceptionGPAddr := io.mem.exceptionAddr.gpaddr 491 csrio.memExceptionIsForVSnonLeafPTE := io.mem.exceptionAddr.isForVSnonLeafPTE 492 csrio.externalInterrupt := RegNext(io.fromTop.externalInterrupt) 493 csrio.perf <> io.perf 494 csrio.perf.retiredInstr <> ctrlBlock.io.robio.csr.perfinfo.retiredInstr 495 csrio.perf.ctrlInfo <> ctrlBlock.io.perfInfo.ctrlInfo 496 private val fenceio = intExuBlock.io.fenceio.get 497 io.fenceio <> fenceio 498 499 // to fpExuBlock 500 fpExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 501 for (i <- 0 until fpExuBlock.io.in.length) { 502 for (j <- 0 until fpExuBlock.io.in(i).length) { 503 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.fp(i)(j).bits.loadDependency, io.mem.ldCancel) 504 NewPipelineConnect( 505 bypassNetwork.io.toExus.fp(i)(j), fpExuBlock.io.in(i)(j), fpExuBlock.io.in(i)(j).fire, 506 Mux( 507 bypassNetwork.io.toExus.fp(i)(j).fire, 508 bypassNetwork.io.toExus.fp(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 509 fpExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 510 ), 511 Option("bypassNetwork2fpExuBlock") 512 ) 513 } 514 } 515 516 vfExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 517 for (i <- 0 until vfExuBlock.io.in.size) { 518 for (j <- 0 until vfExuBlock.io.in(i).size) { 519 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.vf(i)(j).bits.loadDependency, io.mem.ldCancel) 520 NewPipelineConnect( 521 bypassNetwork.io.toExus.vf(i)(j), vfExuBlock.io.in(i)(j), vfExuBlock.io.in(i)(j).fire, 522 Mux( 523 bypassNetwork.io.toExus.vf(i)(j).fire, 524 bypassNetwork.io.toExus.vf(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 525 vfExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 526 ), 527 Option("bypassNetwork2vfExuBlock") 528 ) 529 530 } 531 } 532 533 intExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 534 fpExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 535 fpExuBlock.io.vxrm.foreach(_ := csrio.vpu.vxrm) 536 vfExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 537 vfExuBlock.io.vxrm.foreach(_ := csrio.vpu.vxrm) 538 539 wbDataPath.io.flush := ctrlBlock.io.redirect 540 wbDataPath.io.fromTop.hartId := io.fromTop.hartId 541 wbDataPath.io.fromIntExu <> intExuBlock.io.out 542 wbDataPath.io.fromFpExu <> fpExuBlock.io.out 543 wbDataPath.io.fromVfExu <> vfExuBlock.io.out 544 wbDataPath.io.fromMemExu.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 545 sink.valid := source.valid 546 source.ready := sink.ready 547 sink.bits.data := VecInit(Seq.fill(sink.bits.params.wbPathNum)(source.bits.data)) 548 sink.bits.pdest := source.bits.uop.pdest 549 sink.bits.robIdx := source.bits.uop.robIdx 550 sink.bits.intWen.foreach(_ := source.bits.uop.rfWen) 551 sink.bits.fpWen.foreach(_ := source.bits.uop.fpWen) 552 sink.bits.vecWen.foreach(_ := source.bits.uop.vecWen) 553 sink.bits.v0Wen.foreach(_ := source.bits.uop.v0Wen) 554 sink.bits.vlWen.foreach(_ := source.bits.uop.vlWen) 555 sink.bits.exceptionVec.foreach(_ := source.bits.uop.exceptionVec) 556 sink.bits.flushPipe.foreach(_ := source.bits.uop.flushPipe) 557 sink.bits.replay.foreach(_ := source.bits.uop.replayInst) 558 sink.bits.debug := source.bits.debug 559 sink.bits.debugInfo := source.bits.uop.debugInfo 560 sink.bits.lqIdx.foreach(_ := source.bits.uop.lqIdx) 561 sink.bits.sqIdx.foreach(_ := source.bits.uop.sqIdx) 562 sink.bits.predecodeInfo.foreach(_ := source.bits.uop.preDecodeInfo) 563 sink.bits.vls.foreach(x => { 564 x.vdIdx := source.bits.vdIdx.get 565 x.vdIdxInField := source.bits.vdIdxInField.get 566 x.vpu := source.bits.uop.vpu 567 x.oldVdPsrc := source.bits.uop.psrc(2) 568 x.isIndexed := VlduType.isIndexed(source.bits.uop.fuOpType) 569 x.isMasked := VlduType.isMasked(source.bits.uop.fuOpType) 570 x.isStrided := VlduType.isStrided(source.bits.uop.fuOpType) 571 x.isWhole := VlduType.isWhole(source.bits.uop.fuOpType) 572 x.isVecLoad := VlduType.isVecLd(source.bits.uop.fuOpType) 573 x.isVlm := VlduType.isMasked(source.bits.uop.fuOpType) && VlduType.isVecLd(source.bits.uop.fuOpType) 574 }) 575 sink.bits.trigger.foreach(_ := source.bits.uop.trigger) 576 } 577 wbDataPath.io.fromCSR.vstart := csrio.vpu.vstart 578 579 vecExcpMod.i.fromExceptionGen := ctrlBlock.io.toVecExcpMod.excpInfo 580 vecExcpMod.i.fromRab.logicPhyRegMap := ctrlBlock.io.toVecExcpMod.logicPhyRegMap 581 vecExcpMod.i.fromRat := ctrlBlock.io.toVecExcpMod.ratOldPest 582 vecExcpMod.i.fromVprf := dataPath.io.toVecExcpMod 583 584 // to mem 585 private val memIssueParams = params.memSchdParams.get.issueBlockParams 586 private val memExuBlocksHasLDU = memIssueParams.map(_.exuBlockParams.map(x => x.hasLoadFu || x.hasHyldaFu)) 587 private val memExuBlocksHasVecLoad = memIssueParams.map(_.exuBlockParams.map(x => x.hasVLoadFu)) 588 println(s"[Backend] memExuBlocksHasLDU: $memExuBlocksHasLDU") 589 println(s"[Backend] memExuBlocksHasVecLoad: $memExuBlocksHasVecLoad") 590 591 private val toMem = Wire(bypassNetwork.io.toExus.mem.cloneType) 592 for (i <- toMem.indices) { 593 for (j <- toMem(i).indices) { 594 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.mem(i)(j).bits.loadDependency, io.mem.ldCancel) 595 val issueTimeout = 596 if (memExuBlocksHasLDU(i)(j)) 597 Counter(0 until 16, toMem(i)(j).valid && !toMem(i)(j).fire, bypassNetwork.io.toExus.mem(i)(j).fire)._2 598 else 599 false.B 600 601 if (memScheduler.io.loadFinalIssueResp(i).nonEmpty && memExuBlocksHasLDU(i)(j)) { 602 memScheduler.io.loadFinalIssueResp(i)(j).valid := issueTimeout 603 memScheduler.io.loadFinalIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType 604 memScheduler.io.loadFinalIssueResp(i)(j).bits.resp := RespType.block 605 memScheduler.io.loadFinalIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx 606 memScheduler.io.loadFinalIssueResp(i)(j).bits.uopIdx.foreach(_ := toMem(i)(j).bits.vpu.get.vuopIdx) 607 memScheduler.io.loadFinalIssueResp(i)(j).bits.sqIdx.foreach(_ := toMem(i)(j).bits.sqIdx.get) 608 memScheduler.io.loadFinalIssueResp(i)(j).bits.lqIdx.foreach(_ := toMem(i)(j).bits.lqIdx.get) 609 } 610 611 NewPipelineConnect( 612 bypassNetwork.io.toExus.mem(i)(j), toMem(i)(j), toMem(i)(j).fire, 613 Mux( 614 bypassNetwork.io.toExus.mem(i)(j).fire, 615 bypassNetwork.io.toExus.mem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 616 toMem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || issueTimeout 617 ), 618 Option("bypassNetwork2toMemExus") 619 ) 620 621 if (memScheduler.io.memAddrIssueResp(i).nonEmpty && memExuBlocksHasLDU(i)(j)) { 622 memScheduler.io.memAddrIssueResp(i)(j).valid := toMem(i)(j).fire && FuType.isLoad(toMem(i)(j).bits.fuType) 623 memScheduler.io.memAddrIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType 624 memScheduler.io.memAddrIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx 625 memScheduler.io.memAddrIssueResp(i)(j).bits.sqIdx.foreach(_ := toMem(i)(j).bits.sqIdx.get) 626 memScheduler.io.memAddrIssueResp(i)(j).bits.lqIdx.foreach(_ := toMem(i)(j).bits.lqIdx.get) 627 memScheduler.io.memAddrIssueResp(i)(j).bits.resp := RespType.success // for load inst, firing at toMem means issuing successfully 628 } 629 630 if (memScheduler.io.vecLoadIssueResp(i).nonEmpty && memExuBlocksHasVecLoad(i)(j)) { 631 memScheduler.io.vecLoadIssueResp(i)(j) match { 632 case resp => 633 resp.valid := toMem(i)(j).fire && VlduType.isVecLd(toMem(i)(j).bits.fuOpType) 634 resp.bits.fuType := toMem(i)(j).bits.fuType 635 resp.bits.robIdx := toMem(i)(j).bits.robIdx 636 resp.bits.uopIdx.get := toMem(i)(j).bits.vpu.get.vuopIdx 637 resp.bits.sqIdx.get := toMem(i)(j).bits.sqIdx.get 638 resp.bits.lqIdx.get := toMem(i)(j).bits.lqIdx.get 639 resp.bits.resp := RespType.success 640 } 641 if (backendParams.debugEn){ 642 dontTouch(memScheduler.io.vecLoadIssueResp(i)(j)) 643 } 644 } 645 } 646 } 647 648 io.mem.redirect := ctrlBlock.io.redirect 649 io.mem.issueUops.zip(toMem.flatten).foreach { case (sink, source) => 650 val enableMdp = Constantin.createRecord("EnableMdp", true) 651 sink.valid := source.valid 652 source.ready := sink.ready 653 sink.bits.iqIdx := source.bits.iqIdx 654 sink.bits.isFirstIssue := source.bits.isFirstIssue 655 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 656 sink.bits.src := 0.U.asTypeOf(sink.bits.src) 657 sink.bits.src.zip(source.bits.src).foreach { case (l, r) => l := r} 658 sink.bits.uop.fuType := source.bits.fuType 659 sink.bits.uop.fuOpType := source.bits.fuOpType 660 sink.bits.uop.imm := source.bits.imm 661 sink.bits.uop.robIdx := source.bits.robIdx 662 sink.bits.uop.pdest := source.bits.pdest 663 sink.bits.uop.rfWen := source.bits.rfWen.getOrElse(false.B) 664 sink.bits.uop.fpWen := source.bits.fpWen.getOrElse(false.B) 665 sink.bits.uop.vecWen := source.bits.vecWen.getOrElse(false.B) 666 sink.bits.uop.v0Wen := source.bits.v0Wen.getOrElse(false.B) 667 sink.bits.uop.vlWen := source.bits.vlWen.getOrElse(false.B) 668 sink.bits.uop.flushPipe := source.bits.flushPipe.getOrElse(false.B) 669 sink.bits.uop.pc := source.bits.pc.getOrElse(0.U) 670 sink.bits.uop.loadWaitBit := Mux(enableMdp, source.bits.loadWaitBit.getOrElse(false.B), false.B) 671 sink.bits.uop.waitForRobIdx := Mux(enableMdp, source.bits.waitForRobIdx.getOrElse(0.U.asTypeOf(new RobPtr)), 0.U.asTypeOf(new RobPtr)) 672 sink.bits.uop.storeSetHit := Mux(enableMdp, source.bits.storeSetHit.getOrElse(false.B), false.B) 673 sink.bits.uop.loadWaitStrict := Mux(enableMdp, source.bits.loadWaitStrict.getOrElse(false.B), false.B) 674 sink.bits.uop.ssid := Mux(enableMdp, source.bits.ssid.getOrElse(0.U(SSIDWidth.W)), 0.U(SSIDWidth.W)) 675 sink.bits.uop.lqIdx := source.bits.lqIdx.getOrElse(0.U.asTypeOf(new LqPtr)) 676 sink.bits.uop.sqIdx := source.bits.sqIdx.getOrElse(0.U.asTypeOf(new SqPtr)) 677 sink.bits.uop.ftqPtr := source.bits.ftqIdx.getOrElse(0.U.asTypeOf(new FtqPtr)) 678 sink.bits.uop.ftqOffset := source.bits.ftqOffset.getOrElse(0.U) 679 sink.bits.uop.debugInfo := source.bits.perfDebugInfo 680 sink.bits.uop.vpu := source.bits.vpu.getOrElse(0.U.asTypeOf(new VPUCtrlSignals)) 681 sink.bits.uop.preDecodeInfo := source.bits.preDecode.getOrElse(0.U.asTypeOf(new PreDecodeInfo)) 682 sink.bits.uop.numLsElem := source.bits.numLsElem.getOrElse(0.U) // Todo: remove this bundle, keep only the one below 683 sink.bits.flowNum.foreach(_ := source.bits.numLsElem.get) 684 } 685 io.mem.loadFastMatch := memScheduler.io.toMem.get.loadFastMatch.map(_.fastMatch) 686 io.mem.loadFastImm := memScheduler.io.toMem.get.loadFastMatch.map(_.fastImm) 687 io.mem.tlbCsr := csrio.tlb 688 io.mem.csrCtrl := csrio.customCtrl 689 io.mem.sfence := fenceio.sfence 690 io.mem.isStoreException := CommitType.lsInstIsStore(ctrlBlock.io.robio.exception.bits.commitType) 691 io.mem.isVlsException := ctrlBlock.io.robio.exception.bits.vls 692 require(io.mem.loadPcRead.size == params.LduCnt) 693 io.mem.loadPcRead.zipWithIndex.foreach { case (loadPcRead, i) => 694 loadPcRead := ctrlBlock.io.memLdPcRead(i).data 695 ctrlBlock.io.memLdPcRead(i).valid := io.mem.issueLda(i).valid 696 ctrlBlock.io.memLdPcRead(i).ptr := io.mem.issueLda(i).bits.uop.ftqPtr 697 ctrlBlock.io.memLdPcRead(i).offset := io.mem.issueLda(i).bits.uop.ftqOffset 698 } 699 700 io.mem.storePcRead.zipWithIndex.foreach { case (storePcRead, i) => 701 storePcRead := ctrlBlock.io.memStPcRead(i).data 702 ctrlBlock.io.memStPcRead(i).valid := io.mem.issueSta(i).valid 703 ctrlBlock.io.memStPcRead(i).ptr := io.mem.issueSta(i).bits.uop.ftqPtr 704 ctrlBlock.io.memStPcRead(i).offset := io.mem.issueSta(i).bits.uop.ftqOffset 705 } 706 707 io.mem.hyuPcRead.zipWithIndex.foreach( { case (hyuPcRead, i) => 708 hyuPcRead := ctrlBlock.io.memHyPcRead(i).data 709 ctrlBlock.io.memHyPcRead(i).valid := io.mem.issueHylda(i).valid 710 ctrlBlock.io.memHyPcRead(i).ptr := io.mem.issueHylda(i).bits.uop.ftqPtr 711 ctrlBlock.io.memHyPcRead(i).offset := io.mem.issueHylda(i).bits.uop.ftqOffset 712 }) 713 714 ctrlBlock.io.robio.robHeadLsIssue := io.mem.issueUops.map(deq => deq.fire && deq.bits.uop.robIdx === ctrlBlock.io.robio.robDeqPtr).reduce(_ || _) 715 716 // mem io 717 io.mem.lsqEnqIO <> memScheduler.io.memIO.get.lsqEnqIO 718 io.mem.robLsqIO <> ctrlBlock.io.robio.lsq 719 720 io.frontendSfence := fenceio.sfence 721 io.frontendTlbCsr := csrio.tlb 722 io.frontendCsrCtrl := csrio.customCtrl 723 724 io.tlb <> csrio.tlb 725 726 io.csrCustomCtrl := csrio.customCtrl 727 728 io.toTop.cpuHalted := ctrlBlock.io.toTop.cpuHalt 729 730 io.debugTopDown.fromRob := ctrlBlock.io.debugTopDown.fromRob 731 ctrlBlock.io.debugTopDown.fromCore := io.debugTopDown.fromCore 732 733 io.debugRolling := ctrlBlock.io.debugRolling 734 735 if(backendParams.debugEn) { 736 dontTouch(memScheduler.io) 737 dontTouch(dataPath.io.toMemExu) 738 dontTouch(wbDataPath.io.fromMemExu) 739 } 740 741 // reset tree 742 if (p(DebugOptionsKey).ResetGen) { 743 val rightResetTree = ResetGenNode(Seq( 744 ModuleNode(dataPath), 745 ModuleNode(intExuBlock), 746 ModuleNode(fpExuBlock), 747 ModuleNode(vfExuBlock), 748 ModuleNode(bypassNetwork), 749 ModuleNode(wbDataPath) 750 )) 751 val leftResetTree = ResetGenNode(Seq( 752 ModuleNode(pcTargetMem), 753 ModuleNode(intScheduler), 754 ModuleNode(fpScheduler), 755 ModuleNode(vfScheduler), 756 ModuleNode(memScheduler), 757 ModuleNode(og2ForVector), 758 ModuleNode(wbFuBusyTable), 759 ResetGenNode(Seq( 760 ModuleNode(ctrlBlock), 761 // ResetGenNode(Seq( 762 CellNode(io.frontendReset) 763 // )) 764 )) 765 )) 766 ResetGen(leftResetTree, reset, sim = false) 767 ResetGen(rightResetTree, reset, sim = false) 768 } else { 769 io.frontendReset := DontCare 770 } 771 772 // perf events 773 val pfevent = Module(new PFEvent) 774 pfevent.io.distribute_csr := RegNext(csrio.customCtrl.distribute_csr) 775 val csrevents = pfevent.io.hpmevent.slice(8,16) 776 777 val ctrlBlockPerf = ctrlBlock.getPerfEvents 778 val intSchedulerPerf = intScheduler.asInstanceOf[SchedulerArithImp].getPerfEvents 779 val fpSchedulerPerf = fpScheduler.asInstanceOf[SchedulerArithImp].getPerfEvents 780 val vecSchedulerPerf = vfScheduler.asInstanceOf[SchedulerArithImp].getPerfEvents 781 val memSchedulerPerf = memScheduler.asInstanceOf[SchedulerMemImp].getPerfEvents 782 783 val perfBackend = Seq() 784 // let index = 0 be no event 785 val allPerfEvents = Seq(("noEvent", 0.U)) ++ ctrlBlockPerf ++ intSchedulerPerf ++ fpSchedulerPerf ++ vecSchedulerPerf ++ memSchedulerPerf ++ perfBackend 786 787 788 if (printEventCoding) { 789 for (((name, inc), i) <- allPerfEvents.zipWithIndex) { 790 println("backend perfEvents Set", name, inc, i) 791 } 792 } 793 794 val allPerfInc = allPerfEvents.map(_._2.asTypeOf(new PerfEvent)) 795 val perfEvents = HPerfMonitor(csrevents, allPerfInc).getPerfEvents 796 csrio.perf.perfEventsBackend := VecInit(perfEvents.map(_._2.asTypeOf(new PerfEvent))) 797 generatePerfEvent() 798} 799 800class BackendMemIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 801 // Since fast load replay always use load unit 0, Backend flips two load port to avoid conflicts 802 val flippedLda = true 803 // params alias 804 private val LoadQueueSize = VirtualLoadQueueSize 805 // In/Out // Todo: split it into one-direction bundle 806 val lsqEnqIO = Flipped(new LsqEnqIO) 807 val robLsqIO = new RobLsqIO 808 val ldaIqFeedback = Vec(params.LduCnt, Flipped(new MemRSFeedbackIO)) 809 val staIqFeedback = Vec(params.StaCnt, Flipped(new MemRSFeedbackIO)) 810 val hyuIqFeedback = Vec(params.HyuCnt, Flipped(new MemRSFeedbackIO)) 811 val vstuIqFeedback = Flipped(Vec(params.VstuCnt, new MemRSFeedbackIO(isVector = true))) 812 val vlduIqFeedback = Flipped(Vec(params.VlduCnt, new MemRSFeedbackIO(isVector = true))) 813 val ldCancel = Vec(params.LdExuCnt, Input(new LoadCancelIO)) 814 val wakeup = Vec(params.LdExuCnt, Flipped(Valid(new DynInst))) 815 val loadPcRead = Vec(params.LduCnt, Output(UInt(VAddrBits.W))) 816 val storePcRead = Vec(params.StaCnt, Output(UInt(VAddrBits.W))) 817 val hyuPcRead = Vec(params.HyuCnt, Output(UInt(VAddrBits.W))) 818 // Input 819 val writebackLda = Vec(params.LduCnt, Flipped(DecoupledIO(new MemExuOutput))) 820 val writebackSta = Vec(params.StaCnt, Flipped(DecoupledIO(new MemExuOutput))) 821 val writebackStd = Vec(params.StdCnt, Flipped(DecoupledIO(new MemExuOutput))) 822 val writebackHyuLda = Vec(params.HyuCnt, Flipped(DecoupledIO(new MemExuOutput))) 823 val writebackHyuSta = Vec(params.HyuCnt, Flipped(DecoupledIO(new MemExuOutput))) 824 val writebackVldu = Vec(params.VlduCnt, Flipped(DecoupledIO(new MemExuOutput(true)))) 825 826 val s3_delayed_load_error = Input(Vec(LoadPipelineWidth, Bool())) 827 val stIn = Input(Vec(params.StaExuCnt, ValidIO(new DynInst()))) 828 val memoryViolation = Flipped(ValidIO(new Redirect)) 829 val exceptionAddr = Input(new Bundle { 830 val vaddr = UInt(XLEN.W) 831 val gpaddr = UInt(XLEN.W) 832 val isForVSnonLeafPTE = Bool() 833 }) 834 val sqDeq = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) 835 val lqDeq = Input(UInt(log2Up(CommitWidth + 1).W)) 836 val sqDeqPtr = Input(new SqPtr) 837 val lqDeqPtr = Input(new LqPtr) 838 839 val lqCancelCnt = Input(UInt(log2Up(VirtualLoadQueueSize + 1).W)) 840 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 841 842 val lqCanAccept = Input(Bool()) 843 val sqCanAccept = Input(Bool()) 844 845 val otherFastWakeup = Flipped(Vec(params.LduCnt + params.HyuCnt, ValidIO(new DynInst))) 846 val stIssuePtr = Input(new SqPtr()) 847 848 val debugLS = Flipped(Output(new DebugLSIO)) 849 850 val lsTopdownInfo = Vec(params.LduCnt + params.HyuCnt, Flipped(Output(new LsTopdownInfo))) 851 // Output 852 val redirect = ValidIO(new Redirect) // rob flush MemBlock 853 val issueLda = MixedVec(Seq.fill(params.LduCnt)(DecoupledIO(new MemExuInput()))) 854 val issueSta = MixedVec(Seq.fill(params.StaCnt)(DecoupledIO(new MemExuInput()))) 855 val issueStd = MixedVec(Seq.fill(params.StdCnt)(DecoupledIO(new MemExuInput()))) 856 val issueHylda = MixedVec(Seq.fill(params.HyuCnt)(DecoupledIO(new MemExuInput()))) 857 val issueHysta = MixedVec(Seq.fill(params.HyuCnt)(DecoupledIO(new MemExuInput()))) 858 val issueVldu = MixedVec(Seq.fill(params.VlduCnt)(DecoupledIO(new MemExuInput(true)))) 859 860 val loadFastMatch = Vec(params.LduCnt, Output(UInt(params.LduCnt.W))) 861 val loadFastImm = Vec(params.LduCnt, Output(UInt(12.W))) // Imm_I 862 863 val tlbCsr = Output(new TlbCsrBundle) 864 val csrCtrl = Output(new CustomCSRCtrlIO) 865 val sfence = Output(new SfenceBundle) 866 val isStoreException = Output(Bool()) 867 val isVlsException = Output(Bool()) 868 869 // ATTENTION: The issue ports' sequence order should be the same as IQs' deq config 870 private [backend] def issueUops: Seq[DecoupledIO[MemExuInput]] = { 871 issueSta ++ 872 issueHylda ++ issueHysta ++ 873 issueLda ++ 874 issueVldu ++ 875 issueStd 876 }.toSeq 877 878 // ATTENTION: The writeback ports' sequence order should be the same as IQs' deq config 879 private [backend] def writeBack: Seq[DecoupledIO[MemExuOutput]] = { 880 writebackSta ++ 881 writebackHyuLda ++ writebackHyuSta ++ 882 writebackLda ++ 883 writebackVldu ++ 884 writebackStd 885 } 886} 887 888class TopToBackendBundle(implicit p: Parameters) extends XSBundle { 889 val hartId = Output(UInt(hartIdLen.W)) 890 val externalInterrupt = Output(new ExternalInterruptIO) 891 val msiInfo = Output(ValidIO(new MsiInfoBundle)) 892 val clintTime = Output(ValidIO(UInt(64.W))) 893} 894 895class BackendToTopBundle extends Bundle { 896 val cpuHalted = Output(Bool()) 897} 898 899class BackendIO(implicit p: Parameters, params: BackendParams) extends XSBundle with HasSoCParameter { 900 val fromTop = Flipped(new TopToBackendBundle) 901 902 val toTop = new BackendToTopBundle 903 904 val fenceio = new FenceIO 905 // Todo: merge these bundles into BackendFrontendIO 906 val frontend = Flipped(new FrontendToCtrlIO) 907 val frontendSfence = Output(new SfenceBundle) 908 val frontendCsrCtrl = Output(new CustomCSRCtrlIO) 909 val frontendTlbCsr = Output(new TlbCsrBundle) 910 val frontendReset = Output(Reset()) 911 912 val mem = new BackendMemIO 913 914 val perf = Input(new PerfCounterIO) 915 916 val tlb = Output(new TlbCsrBundle) 917 918 val csrCustomCtrl = Output(new CustomCSRCtrlIO) 919 920 val debugTopDown = new Bundle { 921 val fromRob = new RobCoreTopDownIO 922 val fromCore = new CoreDispatchTopDownIO 923 } 924 val debugRolling = new RobDebugRollingIO 925} 926