1/*************************************************************************************** 2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC) 3* Copyright (c) 2024 Institute of Computing Technology, Chinese Academy of Sciences 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chisel3._ 20import chisel3.util._ 21import org.chipsalliance.cde.config._ 22import freechips.rocketchip.diplomacy._ 23import freechips.rocketchip.interrupts._ 24import freechips.rocketchip.tilelink._ 25import freechips.rocketchip.util._ 26import system.HasSoCParameter 27import device.{IMSICAsync, MsiInfoBundle} 28import coupledL2.tl2chi.{PortIO, AsyncPortIO, CHIAsyncBridgeSource} 29import utility.{IntBuffer, ResetGen} 30import xiangshan.backend.trace.TraceCoreInterface 31 32// This module is used for XSNoCTop for async time domain and divide different 33// voltage domain. Everything in this module should be in the core clock domain 34// and higher voltage domain. 35class XSTileWrap()(implicit p: Parameters) extends LazyModule 36 with HasXSParameter 37 with HasSoCParameter 38{ 39 override def shouldBeInlined: Boolean = false 40 41 val tile = LazyModule(new XSTile()) 42 43 // interrupts sync 44 val clintIntNode = IntIdentityNode() 45 val debugIntNode = IntIdentityNode() 46 val plicIntNode = IntIdentityNode() 47 val beuIntNode = IntIdentityNode() 48 val nmiIntNode = IntIdentityNode() 49 tile.clint_int_node := IntBuffer(3, cdc = true) := clintIntNode 50 tile.debug_int_node := IntBuffer(3, cdc = true) := debugIntNode 51 tile.plic_int_node :*= IntBuffer(3, cdc = true) :*= plicIntNode 52 tile.nmi_int_node := IntBuffer(3, cdc = true) := nmiIntNode 53 beuIntNode := IntBuffer() := tile.beu_int_source 54 55 // seperate DebugModule bus 56 val EnableDMAsync = EnableDMAsyncBridge.isDefined 57 println(s"SeperateDMBus = $SeperateDMBus") 58 println(s"EnableDMAsync = $EnableDMAsync") 59 // asynchronous bridge source node 60 val dmAsyncSourceOpt = Option.when(SeperateDMBus && EnableDMAsync)(LazyModule(new TLAsyncCrossingSource())) 61 dmAsyncSourceOpt.foreach(_.node := tile.sep_dm_opt.get) 62 // synchronous source node 63 val dmSyncSourceOpt = Option.when(SeperateDMBus && !EnableDMAsync)(TLTempNode()) 64 dmSyncSourceOpt.foreach(_ := tile.sep_dm_opt.get) 65 66 class XSTileWrapImp(wrapper: LazyModule) extends LazyRawModuleImp(wrapper) { 67 val clock = IO(Input(Clock())) 68 val reset = IO(Input(AsyncReset())) 69 val noc_reset = EnableCHIAsyncBridge.map(_ => IO(Input(AsyncReset()))) 70 val soc_reset = IO(Input(AsyncReset())) 71 val io = IO(new Bundle { 72 val hartId = Input(UInt(hartIdLen.W)) 73 val msiInfo = Input(ValidIO(new MsiInfoBundle)) 74 val reset_vector = Input(UInt(PAddrBits.W)) 75 val cpu_halt = Output(Bool()) 76 val cpu_crtical_error = Output(Bool()) 77 val hartResetReq = Input(Bool()) 78 val hartIsInReset = Output(Bool()) 79 val traceCoreInterface = new TraceCoreInterface 80 val debugTopDown = new Bundle { 81 val robHeadPaddr = Valid(UInt(PAddrBits.W)) 82 val l3MissMatch = Input(Bool()) 83 } 84 val l3Miss = Input(Bool()) 85 val chi = EnableCHIAsyncBridge match { 86 case Some(param) => new AsyncPortIO(param) 87 case None => new PortIO 88 } 89 val nodeID = if (enableCHI) Some(Input(UInt(NodeIDWidth.W))) else None 90 val clintTime = EnableClintAsyncBridge match { 91 case Some(param) => Flipped(new AsyncBundle(UInt(64.W), param)) 92 case None => Input(ValidIO(UInt(64.W))) 93 } 94 }) 95 96 val reset_sync = withClockAndReset(clock, (reset.asBool || io.hartResetReq).asAsyncReset)(ResetGen()) 97 val noc_reset_sync = EnableCHIAsyncBridge.map(_ => withClockAndReset(clock, noc_reset.get)(ResetGen())) 98 val soc_reset_sync = withClockAndReset(clock, soc_reset)(ResetGen()) 99 100 // override LazyRawModuleImp's clock and reset 101 childClock := clock 102 childReset := reset_sync 103 104 val imsicAsync = withClockAndReset(clock, reset_sync)(Module(new IMSICAsync())) 105 imsicAsync.i.msiInfo := io.msiInfo 106 107 tile.module.io.hartId := io.hartId 108 tile.module.io.msiInfo := imsicAsync.o.msiInfo 109 tile.module.io.reset_vector := io.reset_vector 110 io.cpu_halt := tile.module.io.cpu_halt 111 io.cpu_crtical_error := tile.module.io.cpu_crtical_error 112 io.hartIsInReset := tile.module.io.hartIsInReset 113 io.traceCoreInterface <> tile.module.io.traceCoreInterface 114 io.debugTopDown <> tile.module.io.debugTopDown 115 tile.module.io.l3Miss := io.l3Miss 116 tile.module.io.nodeID.foreach(_ := io.nodeID.get) 117 118 // CLINT Async Queue Sink 119 EnableClintAsyncBridge match { 120 case Some(param) => 121 val sink = withClockAndReset(clock, soc_reset_sync)(Module(new AsyncQueueSink(UInt(64.W), param))) 122 sink.io.async <> io.clintTime 123 sink.io.deq.ready := true.B 124 tile.module.io.clintTime.valid := sink.io.deq.valid 125 tile.module.io.clintTime.bits := sink.io.deq.bits 126 case None => 127 tile.module.io.clintTime := io.clintTime 128 } 129 130 // CHI Async Queue Source 131 EnableCHIAsyncBridge match { 132 case Some(param) => 133 val source = withClockAndReset(clock, noc_reset_sync.get)(Module(new CHIAsyncBridgeSource(param))) 134 source.io.enq <> tile.module.io.chi.get 135 io.chi <> source.io.async 136 case None => 137 require(enableCHI) 138 io.chi <> tile.module.io.chi.get 139 } 140 141 // Seperate DebugModule TL Async Queue Source 142 if (SeperateDMBus && EnableDMAsync) { 143 dmAsyncSourceOpt.get.module.clock := clock 144 dmAsyncSourceOpt.get.module.reset := soc_reset_sync 145 } 146 147 withClockAndReset(clock, reset_sync) { 148 // Modules are reset one by one 149 // reset ----> SYNC --> XSTile 150 val resetChain = Seq(Seq(tile.module)) 151 ResetGen(resetChain, reset_sync, !debugOpts.FPGAPlatform) 152 } 153 dontTouch(io.hartId) 154 dontTouch(io.msiInfo) 155 } 156 lazy val module = new XSTileWrapImp(this) 157} 158