xref: /XiangShan/src/main/scala/xiangshan/XSTileWrap.scala (revision 211d620b07edb797ba35b635d24fef4e7294bae2) 
1/***************************************************************************************
2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC)
3* Copyright (c) 2024 Institute of Computing Technology, Chinese Academy of Sciences
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package xiangshan
18
19import chisel3._
20import chisel3.util._
21import org.chipsalliance.cde.config._
22import freechips.rocketchip.diplomacy._
23import freechips.rocketchip.interrupts._
24import freechips.rocketchip.util._
25import system.HasSoCParameter
26import device.{IMSICAsync, MsiInfoBundle}
27import coupledL2.tl2chi.{PortIO, AsyncPortIO, CHIAsyncBridgeSource}
28import utility.{IntBuffer, ResetGen}
29
30// This module is used for XSNoCTop for async time domain and divide different
31// voltage domain. Everything in this module should be in the core clock domain
32// and higher voltage domain.
33class XSTileWrap()(implicit p: Parameters) extends LazyModule
34  with HasXSParameter
35  with HasSoCParameter
36{
37  override def shouldBeInlined: Boolean = false
38
39  val tile = LazyModule(new XSTile())
40
41  // interrupts sync
42  val clintIntNode = IntIdentityNode()
43  val debugIntNode = IntIdentityNode()
44  val plicIntNode = IntIdentityNode()
45  val beuIntNode = IntIdentityNode()
46  val nmiIntNode = IntIdentityNode()
47  tile.clint_int_node := IntBuffer(3, cdc = true) := clintIntNode
48  tile.debug_int_node := IntBuffer(3, cdc = true) := debugIntNode
49  tile.plic_int_node :*= IntBuffer(3, cdc = true) :*= plicIntNode
50  tile.nmi_int_node := IntBuffer(3, cdc = true) := nmiIntNode
51  beuIntNode := IntBuffer() := tile.beu_int_source
52  class XSTileWrapImp(wrapper: LazyModule) extends LazyRawModuleImp(wrapper) {
53    val clock = IO(Input(Clock()))
54    val reset = IO(Input(AsyncReset()))
55    val noc_reset = EnableCHIAsyncBridge.map(_ => IO(Input(AsyncReset())))
56    val soc_reset = IO(Input(AsyncReset()))
57    val io = IO(new Bundle {
58      val hartId = Input(UInt(hartIdLen.W))
59      val msiInfo = Input(ValidIO(new MsiInfoBundle))
60      val reset_vector = Input(UInt(PAddrBits.W))
61      val cpu_halt = Output(Bool())
62      val cpu_crtical_error = Output(Bool())
63      val hartIsInReset = Output(Bool())
64      val debugTopDown = new Bundle {
65        val robHeadPaddr = Valid(UInt(PAddrBits.W))
66        val l3MissMatch = Input(Bool())
67      }
68      val chi = EnableCHIAsyncBridge match {
69        case Some(param) => new AsyncPortIO(param)
70        case None => new PortIO
71      }
72      val nodeID = if (enableCHI) Some(Input(UInt(NodeIDWidth.W))) else None
73      val clintTime = EnableClintAsyncBridge match {
74        case Some(param) => Flipped(new AsyncBundle(UInt(64.W), param))
75        case None => Input(ValidIO(UInt(64.W)))
76      }
77    })
78
79    val reset_sync = withClockAndReset(clock, reset)(ResetGen())
80    val noc_reset_sync = EnableCHIAsyncBridge.map(_ => withClockAndReset(clock, noc_reset.get)(ResetGen()))
81    val soc_reset_sync = withClockAndReset(clock, soc_reset)(ResetGen())
82
83    // override LazyRawModuleImp's clock and reset
84    childClock := clock
85    childReset := reset_sync
86
87    val imsicAsync = withClockAndReset(clock, reset_sync)(Module(new IMSICAsync()))
88    imsicAsync.i.msiInfo := io.msiInfo
89
90    tile.module.io.hartId := io.hartId
91    tile.module.io.msiInfo := imsicAsync.o.msiInfo
92    tile.module.io.reset_vector := io.reset_vector
93    io.cpu_halt := tile.module.io.cpu_halt
94    io.cpu_crtical_error := tile.module.io.cpu_crtical_error
95    io.hartIsInReset := tile.module.io.hartIsInReset
96    io.debugTopDown <> tile.module.io.debugTopDown
97    tile.module.io.nodeID.foreach(_ := io.nodeID.get)
98
99    // CLINT Async Queue Sink
100    EnableClintAsyncBridge match {
101      case Some(param) =>
102        val sink = withClockAndReset(clock, soc_reset_sync)(Module(new AsyncQueueSink(UInt(64.W), param)))
103        sink.io.async <> io.clintTime
104        sink.io.deq.ready := true.B
105        tile.module.io.clintTime.valid := sink.io.deq.valid
106        tile.module.io.clintTime.bits := sink.io.deq.bits
107      case None =>
108        tile.module.io.clintTime := io.clintTime
109    }
110
111    // CHI Async Queue Source
112    EnableCHIAsyncBridge match {
113      case Some(param) =>
114        val source = withClockAndReset(clock, noc_reset_sync.get)(Module(new CHIAsyncBridgeSource(param)))
115        source.io.enq <> tile.module.io.chi.get
116        io.chi <> source.io.async
117      case None =>
118        require(enableCHI)
119        io.chi <> tile.module.io.chi.get
120    }
121
122    withClockAndReset(clock, reset_sync) {
123      // Modules are reset one by one
124      // reset ----> SYNC --> XSTile
125      val resetChain = Seq(Seq(tile.module))
126      ResetGen(resetChain, reset_sync, !debugOpts.FPGAPlatform)
127    }
128    dontTouch(io.hartId)
129    dontTouch(io.msiInfo)
130  }
131  lazy val module = new XSTileWrapImp(this)
132}
133