1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config.{Config, Parameters} 20import chisel3._ 21import chisel3.util.{Valid, ValidIO} 22import freechips.rocketchip.diplomacy._ 23import freechips.rocketchip.interrupts._ 24import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, BusErrors} 25import freechips.rocketchip.tilelink._ 26import freechips.rocketchip.amba.axi4._ 27import system.HasSoCParameter 28import top.{BusPerfMonitor, ArgParser, Generator} 29import utility.{DelayN, ResetGen, TLClientsMerger, TLEdgeBuffer, TLLogger, Constantin, ChiselDB, FileRegisters} 30import coupledL2.EnableCHI 31import coupledL2.tl2chi.PortIO 32 33class XSTile()(implicit p: Parameters) extends LazyModule 34 with HasXSParameter 35 with HasSoCParameter 36{ 37 override def shouldBeInlined: Boolean = false 38 val core = LazyModule(new XSCore()) 39 val l2top = LazyModule(new L2Top()) 40 41 val enableL2 = coreParams.L2CacheParamsOpt.isDefined 42 // =========== Public Ports ============ 43 val core_l3_pf_port = core.memBlock.l3_pf_sender_opt 44 val memory_port = if (enableCHI && enableL2) None else Some(l2top.memory_port.get) 45 val tl_uncache = l2top.mmio_port 46 // val axi4_uncache = if (enableCHI) Some(AXI4UserYanker()) else None 47 val beu_int_source = l2top.beu.intNode 48 val core_reset_sink = BundleBridgeSink(Some(() => Reset())) 49 val clint_int_node = l2top.clint_int_node 50 val plic_int_node = l2top.plic_int_node 51 val debug_int_node = l2top.debug_int_node 52 core.memBlock.clint_int_sink := clint_int_node 53 core.memBlock.plic_int_sink :*= plic_int_node 54 core.memBlock.debug_int_sink := debug_int_node 55 56 // =========== Components' Connection ============ 57 // L1 to l1_xbar 58 coreParams.dcacheParametersOpt.map { _ => 59 l2top.misc_l2_pmu := l2top.l1d_logger := core.memBlock.dcache_port := 60 core.memBlock.l1d_to_l2_buffer.node := core.memBlock.dcache.clientNode 61 } 62 63 l2top.misc_l2_pmu := l2top.l1i_logger := core.memBlock.frontendBridge.icache_node 64 if (!coreParams.softPTW) { 65 l2top.misc_l2_pmu := l2top.ptw_logger := l2top.ptw_to_l2_buffer.node := core.memBlock.ptw_to_l2_buffer.node 66 } 67 68 // L2 Prefetch 69 l2top.l2cache match { 70 case Some(l2) => 71 l2.pf_recv_node.foreach(recv => { 72 println("Connecting L1 prefetcher to L2!") 73 recv := core.memBlock.l2_pf_sender_opt.get 74 }) 75 case None => 76 } 77 78 val core_l3_tpmeta_source_port = l2top.l2cache match { 79 case Some(l2) => l2.tpmeta_source_node 80 case None => None 81 } 82 val core_l3_tpmeta_sink_port = l2top.l2cache match { 83 case Some(l2) => l2.tpmeta_sink_node 84 case None => None 85 } 86 87 // mmio 88 l2top.i_mmio_port := l2top.i_mmio_buffer.node := core.memBlock.frontendBridge.instr_uncache_node 89 l2top.d_mmio_port := core.memBlock.uncache.clientNode 90 91 // =========== IO Connection ============ 92 class XSTileImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) { 93 val io = IO(new Bundle { 94 val hartId = Input(UInt(hartIdLen.W)) 95 val reset_vector = Input(UInt(PAddrBits.W)) 96 val cpu_halt = Output(Bool()) 97 val debugTopDown = new Bundle { 98 val robHeadPaddr = Valid(UInt(PAddrBits.W)) 99 val l3MissMatch = Input(Bool()) 100 } 101 val chi = if (enableCHI) Some(new PortIO) else None 102 val nodeID = if (enableCHI) Some(Input(UInt(NodeIDWidth.W))) else None 103 }) 104 105 dontTouch(io.hartId) 106 if (!io.chi.isEmpty) { dontTouch(io.chi.get) } 107 108 val core_soft_rst = core_reset_sink.in.head._1 // unused 109 110 l2top.module.hartId.fromTile := io.hartId 111 core.module.io.hartId := l2top.module.hartId.toCore 112 core.module.io.reset_vector := l2top.module.reset_vector.toCore 113 l2top.module.reset_vector.fromTile := io.reset_vector 114 l2top.module.cpu_halt.fromCore := core.module.io.cpu_halt 115 io.cpu_halt := l2top.module.cpu_halt.toTile 116 117 core.module.io.perfEvents <> DontCare 118 119 l2top.module.beu_errors.icache <> core.module.io.beu_errors.icache 120 l2top.module.beu_errors.dcache <> core.module.io.beu_errors.dcache 121 if (enableL2) { 122 // TODO: add ECC interface of L2 123 124 l2top.module.beu_errors.l2 <> 0.U.asTypeOf(l2top.module.beu_errors.l2) 125 core.module.io.l2_hint.bits.sourceId := l2top.module.l2_hint.bits.sourceId 126 core.module.io.l2_hint.bits.isKeyword := l2top.module.l2_hint.bits.isKeyword 127 core.module.io.l2_hint.valid := l2top.module.l2_hint.valid 128 129 core.module.io.l2PfqBusy := false.B 130 core.module.io.debugTopDown.l2MissMatch := l2top.module.debugTopDown.l2MissMatch 131 l2top.module.debugTopDown.robHeadPaddr := core.module.io.debugTopDown.robHeadPaddr 132 l2top.module.debugTopDown.robTrueCommit := core.module.io.debugTopDown.robTrueCommit 133 core.module.io.l2_tlb_req <> l2top.module.l2_tlb_req 134 } else { 135 136 l2top.module.beu_errors.l2 <> 0.U.asTypeOf(l2top.module.beu_errors.l2) 137 core.module.io.l2_hint.bits.sourceId := l2top.module.l2_hint.bits.sourceId 138 core.module.io.l2_hint.bits.isKeyword := l2top.module.l2_hint.bits.isKeyword 139 core.module.io.l2_hint.valid := l2top.module.l2_hint.valid 140 141 core.module.io.l2PfqBusy := false.B 142 core.module.io.debugTopDown.l2MissMatch := false.B 143 144 core.module.io.l2_tlb_req.req.valid := false.B 145 core.module.io.l2_tlb_req.req.bits := DontCare 146 core.module.io.l2_tlb_req.req_kill := DontCare 147 core.module.io.l2_tlb_req.resp.ready := true.B 148 } 149 150 io.debugTopDown.robHeadPaddr := core.module.io.debugTopDown.robHeadPaddr 151 core.module.io.debugTopDown.l3MissMatch := io.debugTopDown.l3MissMatch 152 153 io.chi.foreach(_ <> l2top.module.chi.get) 154 l2top.module.nodeID.foreach(_ := io.nodeID.get) 155 156 // Modules are reset one by one 157 // io_reset ---- 158 // | 159 // v 160 // reset ----> OR_SYNC --> {Misc, L2 Cache, Cores} 161 // val resetChain = Seq( 162 // Seq(l2top.module, core.module) 163 // ) 164 // ResetGen(resetChain, reset, !debugOpts.FPGAPlatform) 165 } 166 167 lazy val module = new XSTileImp(this) 168} 169