1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17// See LICENSE.SiFive for license details. 18 19package xiangshan 20 21import freechips.rocketchip.diplomacy._ 22 23trait HasXSDts { 24 this: XSCore => 25 26 val device: SimpleDevice = new SimpleDevice("cpu", Seq("ICT,xiangshan", "riscv")) { 27 override def parent: Some[Device] = Some(ResourceAnchors.cpus) 28 29 def cpuProperties: PropertyMap = Map( 30 "device_type" -> "cpu".asProperty, 31 "status" -> "okay".asProperty, 32 "clock-frequency" -> 0.asProperty, 33 "riscv,isa" -> "rv64imafdc".asProperty, 34 "timebase-frequency" -> 1000000.asProperty 35 ) 36 37 def tileProperties: PropertyMap = { 38 val dcache = if(coreParams.dcacheParametersOpt.nonEmpty) Map( 39 "d-cache-block-size" -> dcacheParameters.blockBytes.asProperty, 40 "d-cache-sets" -> dcacheParameters.nSets.asProperty, 41 "d-cache-size" -> (dcacheParameters.nSets * dcacheParameters.nWays * dcacheParameters.blockBytes).asProperty 42 ) else Map() 43 44 val icache = Map( 45 "i-cache-block-size" -> icacheParameters.blockBytes.asProperty, 46 "i-cache-sets" -> icacheParameters.nSets.asProperty, 47 "i-cache-size" -> (icacheParameters.nSets * icacheParameters.nWays * icacheParameters.blockBytes).asProperty 48 ) 49 50 val dtlb = Map( 51 "d-tlb-size" -> (ldtlbParams.NSets * ldtlbParams.NWays).asProperty, 52 "d-tlb-sets" -> 1.asProperty 53 ) 54 55 val itlb = Map( 56 "i-tlb-size" -> (itlbParams.NSets * itlbParams.NWays).asProperty, 57 "i-tlb-sets" -> 1.asProperty 58 ) 59 60 val mmu = Map( 61 "tlb-split" -> Nil, 62 "mmu-type" -> s"riscv,sv$VAddrBits".asProperty 63 ) 64 65 val pmp = Nil 66 67 dcache ++ icache ++ dtlb ++ itlb ++ mmu ++ pmp 68 } 69 70 def nextLevelCacheProperty: PropertyOption = { 71 if(coreParams.dcacheParametersOpt.nonEmpty){ 72 val outer = memBlock.dcache.clientNode.edges.out.flatMap(_.manager.managers) 73 .filter(_.supportsAcquireB) 74 .flatMap(_.resources.headOption) 75 .map(_.owner.label) 76 .distinct 77 if (outer.isEmpty) None 78 else Some("next-level-cache" -> outer.map(l => ResourceReference(l)).toList) 79 } else None 80 } 81 82 override def describe(resources: ResourceBindings): Description = { 83 val Description(name, mapping) = super.describe(resources) 84 Description(name, mapping ++ cpuProperties ++ nextLevelCacheProperty ++ tileProperties) 85 } 86 } 87 88 val intcDevice = new DeviceSnippet { 89 override def parent = Some(device) 90 def describe(): Description = { 91 Description("interrupt-controller", Map( 92 "compatible" -> "riscv,cpu-intc".asProperty, 93 "interrupt-controller" -> Nil, 94 "#interrupt-cells" -> 1.asProperty)) 95 } 96 } 97 98 ResourceBinding { 99 Resource(device, "reg").bind(ResourceAddress(coreParams.HartId)) 100 val int_resources = ( 101 clint_int_sink.edges.in.flatMap(_.source.sources) ++ 102 plic_int_sink.edges.in.flatMap(_.source.sources) ++ 103 debug_int_sink.edges.in.flatMap(_.source.sources) 104 ).flatMap { 105 s => 106 println(s.resources.map(_.key), s.range) 107 (s.range.start until s.range.`end`).map(_ => s.resources) 108 } 109 val int_ids = Seq( 110 3, // msip [clint] 111 7, // mtip [clint] 112 11, // meip [plic] 113 9, // seip [plic] 114 65535 // debug [debug] 115 ) 116 assert(int_resources.size == int_ids.size) 117 for((resources, id) <- int_resources.zip(int_ids)){ 118 for(r <- resources){ 119 r.bind(intcDevice, ResourceInt(id)) 120 } 121 } 122 } 123} 124