1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import top.Parameters 6import xiangshan.backend._ 7import xiangshan.backend.dispatch.DispatchParameters 8import xiangshan.backend.exu.ExuParameters 9import xiangshan.backend.exu.Exu._ 10import xiangshan.frontend._ 11import xiangshan.mem._ 12import xiangshan.backend.fu.HasExceptionNO 13import xiangshan.cache.{DCacheParameters, ICacheParameters, L1plusCache, L1plusCacheParameters, PTW, PTWRepeater} 14import xiangshan.cache.prefetch._ 15import chipsalliance.rocketchip.config 16import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 17import freechips.rocketchip.tile.HasFPUParameters 18import utils._ 19 20object hartIdCore extends (() => Int) { 21 var x = 0 22 23 def apply(): Int = { 24 x = x + 1 25 x - 1 26 } 27} 28 29case class XSCoreParameters 30( 31 XLEN: Int = 64, 32 HasMExtension: Boolean = true, 33 HasCExtension: Boolean = true, 34 HasDiv: Boolean = true, 35 HasICache: Boolean = true, 36 HasDCache: Boolean = true, 37 EnableStoreQueue: Boolean = true, 38 AddrBits: Int = 64, 39 VAddrBits: Int = 39, 40 PAddrBits: Int = 40, 41 HasFPU: Boolean = true, 42 FetchWidth: Int = 8, 43 EnableBPU: Boolean = true, 44 EnableBPD: Boolean = true, 45 EnableRAS: Boolean = true, 46 EnableLB: Boolean = false, 47 EnableLoop: Boolean = true, 48 EnableSC: Boolean = true, 49 EnbaleTlbDebug: Boolean = false, 50 EnableJal: Boolean = false, 51 EnableUBTB: Boolean = true, 52 HistoryLength: Int = 64, 53 BtbSize: Int = 2048, 54 JbtacSize: Int = 1024, 55 JbtacBanks: Int = 8, 56 RasSize: Int = 16, 57 CacheLineSize: Int = 512, 58 UBtbWays: Int = 16, 59 BtbWays: Int = 2, 60 61 EnableL1plusPrefetcher: Boolean = true, 62 IBufSize: Int = 32, 63 DecodeWidth: Int = 6, 64 RenameWidth: Int = 6, 65 CommitWidth: Int = 6, 66 BrqSize: Int = 32, 67 FtqSize: Int = 48, 68 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 69 IssQueSize: Int = 12, 70 NRPhyRegs: Int = 160, 71 NRIntReadPorts: Int = 14, 72 NRIntWritePorts: Int = 8, 73 NRFpReadPorts: Int = 14, 74 NRFpWritePorts: Int = 8, 75 LoadQueueSize: Int = 64, 76 StoreQueueSize: Int = 48, 77 RoqSize: Int = 192, 78 dpParams: DispatchParameters = DispatchParameters( 79 IntDqSize = 16, 80 FpDqSize = 16, 81 LsDqSize = 16, 82 IntDqDeqWidth = 4, 83 FpDqDeqWidth = 4, 84 LsDqDeqWidth = 4 85 ), 86 exuParameters: ExuParameters = ExuParameters( 87 JmpCnt = 1, 88 AluCnt = 4, 89 MulCnt = 0, 90 MduCnt = 2, 91 FmacCnt = 4, 92 FmiscCnt = 2, 93 FmiscDivSqrtCnt = 0, 94 LduCnt = 2, 95 StuCnt = 2 96 ), 97 LoadPipelineWidth: Int = 2, 98 StorePipelineWidth: Int = 2, 99 StoreBufferSize: Int = 16, 100 RefillSize: Int = 512, 101 TlbEntrySize: Int = 32, 102 TlbSPEntrySize: Int = 4, 103 PtwL3EntrySize: Int = 4096, //(256 * 16) or 512 104 PtwSPEntrySize: Int = 16, 105 PtwL1EntrySize: Int = 16, 106 PtwL2EntrySize: Int = 2048, //(256 * 8) 107 NumPerfCounters: Int = 16, 108 NrExtIntr: Int = 150 109) 110 111trait HasXSParameter { 112 113 val coreParams = Parameters.get.coreParameters 114 val env = Parameters.get.envParameters 115 116 val XLEN = 64 117 val minFLen = 32 118 val fLen = 64 119 120 def xLen = 64 121 122 val HasMExtension = coreParams.HasMExtension 123 val HasCExtension = coreParams.HasCExtension 124 val HasDiv = coreParams.HasDiv 125 val HasIcache = coreParams.HasICache 126 val HasDcache = coreParams.HasDCache 127 val EnableStoreQueue = coreParams.EnableStoreQueue 128 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 129 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 130 val PAddrBits = coreParams.PAddrBits // PAddrBits is Phyical Memory addr bits 131 val AddrBytes = AddrBits / 8 // unused 132 val DataBits = XLEN 133 val DataBytes = DataBits / 8 134 val HasFPU = coreParams.HasFPU 135 val FetchWidth = coreParams.FetchWidth 136 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 137 val EnableBPU = coreParams.EnableBPU 138 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 139 val EnableRAS = coreParams.EnableRAS 140 val EnableLB = coreParams.EnableLB 141 val EnableLoop = coreParams.EnableLoop 142 val EnableSC = coreParams.EnableSC 143 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 144 val HistoryLength = coreParams.HistoryLength 145 val BtbSize = coreParams.BtbSize 146 // val BtbWays = 4 147 val BtbBanks = PredictWidth 148 // val BtbSets = BtbSize / BtbWays 149 val JbtacSize = coreParams.JbtacSize 150 val JbtacBanks = coreParams.JbtacBanks 151 val RasSize = coreParams.RasSize 152 val CacheLineSize = coreParams.CacheLineSize 153 val CacheLineHalfWord = CacheLineSize / 16 154 val ExtHistoryLength = HistoryLength + 64 155 val UBtbWays = coreParams.UBtbWays 156 val BtbWays = coreParams.BtbWays 157 val EnableL1plusPrefetcher = coreParams.EnableL1plusPrefetcher 158 val IBufSize = coreParams.IBufSize 159 val DecodeWidth = coreParams.DecodeWidth 160 val RenameWidth = coreParams.RenameWidth 161 val CommitWidth = coreParams.CommitWidth 162 val BrqSize = coreParams.BrqSize 163 val FtqSize = coreParams.FtqSize 164 val IssQueSize = coreParams.IssQueSize 165 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 166 val BrTagWidth = log2Up(BrqSize) 167 val NRPhyRegs = coreParams.NRPhyRegs 168 val PhyRegIdxWidth = log2Up(NRPhyRegs) 169 val RoqSize = coreParams.RoqSize 170 val LoadQueueSize = coreParams.LoadQueueSize 171 val StoreQueueSize = coreParams.StoreQueueSize 172 val dpParams = coreParams.dpParams 173 val exuParameters = coreParams.exuParameters 174 val NRIntReadPorts = coreParams.NRIntReadPorts 175 val NRIntWritePorts = coreParams.NRIntWritePorts 176 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 177 val NRFpReadPorts = coreParams.NRFpReadPorts 178 val NRFpWritePorts = coreParams.NRFpWritePorts 179 val LoadPipelineWidth = coreParams.LoadPipelineWidth 180 val StorePipelineWidth = coreParams.StorePipelineWidth 181 val StoreBufferSize = coreParams.StoreBufferSize 182 val RefillSize = coreParams.RefillSize 183 val DTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 184 val TlbEntrySize = coreParams.TlbEntrySize 185 val TlbSPEntrySize = coreParams.TlbSPEntrySize 186 val PtwL3EntrySize = coreParams.PtwL3EntrySize 187 val PtwSPEntrySize = coreParams.PtwSPEntrySize 188 val PtwL1EntrySize = coreParams.PtwL1EntrySize 189 val PtwL2EntrySize = coreParams.PtwL2EntrySize 190 val NumPerfCounters = coreParams.NumPerfCounters 191 val NrExtIntr = coreParams.NrExtIntr 192 193 val instBytes = if (HasCExtension) 2 else 4 194 val instOffsetBits = log2Ceil(instBytes) 195 196 val icacheParameters = ICacheParameters( 197 tagECC = Some("parity"), 198 dataECC = Some("parity"), 199 replacer = Some("setplru"), 200 nMissEntries = 2 201 ) 202 203 val l1plusCacheParameters = L1plusCacheParameters( 204 tagECC = Some("secded"), 205 dataECC = Some("secded"), 206 replacer = Some("setplru"), 207 nMissEntries = 8 208 ) 209 210 val dcacheParameters = DCacheParameters( 211 tagECC = Some("secded"), 212 dataECC = Some("secded"), 213 replacer = Some("setplru"), 214 nMissEntries = 16, 215 nProbeEntries = 16, 216 nReleaseEntries = 16, 217 nStoreReplayEntries = 16 218 ) 219 220 val LRSCCycles = 100 221 222 223 // cache hierarchy configurations 224 val l1BusDataWidth = 256 225 226 // L2 configurations 227 val L1BusWidth = 256 228 val L2Size = 512 * 1024 // 512KB 229 val L2BlockSize = 64 230 val L2NWays = 8 231 val L2NSets = L2Size / L2BlockSize / L2NWays 232 233 // L3 configurations 234 val L2BusWidth = 256 235 val L3Size = 4 * 1024 * 1024 // 4MB 236 val L3BlockSize = 64 237 val L3NBanks = 4 238 val L3NWays = 8 239 val L3NSets = L3Size / L3BlockSize / L3NBanks / L3NWays 240 241 // on chip network configurations 242 val L3BusWidth = 256 243 244 // icache prefetcher 245 val l1plusPrefetcherParameters = L1plusPrefetcherParameters( 246 enable = true, 247 _type = "stream", 248 streamParams = StreamPrefetchParameters( 249 streamCnt = 2, 250 streamSize = 4, 251 ageWidth = 4, 252 blockBytes = l1plusCacheParameters.blockBytes, 253 reallocStreamOnMissInstantly = true, 254 cacheName = "icache" 255 ) 256 ) 257 258 // dcache prefetcher 259 val l2PrefetcherParameters = L2PrefetcherParameters( 260 enable = true, 261 _type = "bop", // "stream" or "bop" 262 streamParams = StreamPrefetchParameters( 263 streamCnt = 4, 264 streamSize = 4, 265 ageWidth = 4, 266 blockBytes = L2BlockSize, 267 reallocStreamOnMissInstantly = true, 268 cacheName = "dcache" 269 ), 270 bopParams = BOPParameters( 271 rrTableEntries = 256, 272 rrTagBits = 12, 273 scoreBits = 5, 274 roundMax = 50, 275 badScore = 1, 276 blockBytes = L2BlockSize, 277 nEntries = dcacheParameters.nMissEntries * 2 // TODO: this is too large 278 ), 279 ) 280} 281 282trait HasXSLog { 283 this: RawModule => 284 implicit val moduleName: String = this.name 285} 286 287abstract class XSModule extends MultiIOModule 288 with HasXSParameter 289 with HasExceptionNO 290 with HasXSLog 291 with HasFPUParameters { 292 def io: Record 293} 294 295//remove this trait after impl module logic 296trait NeedImpl { 297 this: RawModule => 298 override protected def IO[T <: Data](iodef: T): T = { 299 println(s"[Warn]: (${this.name}) please reomve 'NeedImpl' after implement this module") 300 val io = chisel3.experimental.IO(iodef) 301 io <> DontCare 302 io 303 } 304} 305 306abstract class XSBundle extends Bundle 307 with HasXSParameter 308 309case class EnviromentParameters 310( 311 FPGAPlatform: Boolean = true, 312 EnableDebug: Boolean = false, 313 EnablePerfDebug: Boolean = true, 314 DualCore: Boolean = false 315) 316 317// object AddressSpace extends HasXSParameter { 318// // (start, size) 319// // address out of MMIO will be considered as DRAM 320// def mmio = List( 321// (0x00000000L, 0x40000000L), // internal devices, such as CLINT and PLIC 322// (0x40000000L, 0x40000000L) // external devices 323// ) 324 325// def isMMIO(addr: UInt): Bool = mmio.map(range => { 326// require(isPow2(range._2)) 327// val bits = log2Up(range._2) 328// (addr ^ range._1.U)(PAddrBits-1, bits) === 0.U 329// }).reduce(_ || _) 330// } 331 332 333class XSCore()(implicit p: config.Parameters) extends LazyModule 334 with HasXSParameter 335 with HasExeBlockHelper { 336 // outer facing nodes 337 val frontend = LazyModule(new Frontend()) 338 val l1pluscache = LazyModule(new L1plusCache()) 339 val ptw = LazyModule(new PTW()) 340 val memBlock = LazyModule(new MemBlock( 341 fastWakeUpIn = intExuConfigs.filter(_.hasCertainLatency), 342 slowWakeUpIn = intExuConfigs.filter(_.hasUncertainlatency) ++ fpExuConfigs, 343 fastWakeUpOut = Seq(), 344 slowWakeUpOut = loadExuConfigs, 345 numIntWakeUpFp = intExuConfigs.count(_.writeFpRf) 346 )) 347 348 lazy val module = new XSCoreImp(this) 349} 350 351class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer) 352 with HasXSParameter 353 with HasExeBlockHelper { 354 val io = IO(new Bundle { 355 val hartId = Input(UInt(64.W)) 356 val externalInterrupt = new ExternalInterruptIO 357 val l2_pf_enable = Output(Bool()) 358 }) 359 360 val difftestIO = IO(new DifftestBundle()) 361 difftestIO <> DontCare 362 363 val trapIO = IO(new TrapIO()) 364 trapIO <> DontCare 365 366 println(s"FPGAPlatform:${env.FPGAPlatform} EnableDebug:${env.EnableDebug}") 367 AddressSpace.checkMemmap() 368 AddressSpace.printMemmap() 369 370 // to fast wake up fp, mem rs 371 val intBlockFastWakeUp = intExuConfigs.filter(_.hasCertainLatency) 372 val intBlockSlowWakeUp = intExuConfigs.filter(_.hasUncertainlatency) 373 374 val ctrlBlock = Module(new CtrlBlock) 375 val integerBlock = Module(new IntegerBlock( 376 fastWakeUpIn = Seq(), 377 slowWakeUpIn = fpExuConfigs.filter(_.writeIntRf) ++ loadExuConfigs, 378 memFastWakeUpIn = loadExuConfigs, 379 fastWakeUpOut = intBlockFastWakeUp, 380 slowWakeUpOut = intBlockSlowWakeUp 381 )) 382 val floatBlock = Module(new FloatBlock( 383 intSlowWakeUpIn = intExuConfigs.filter(_.writeFpRf), 384 memSlowWakeUpIn = loadExuConfigs, 385 fastWakeUpOut = Seq(), 386 slowWakeUpOut = fpExuConfigs 387 )) 388 389 val frontend = outer.frontend.module 390 val memBlock = outer.memBlock.module 391 val l1pluscache = outer.l1pluscache.module 392 val ptw = outer.ptw.module 393 394 frontend.io.backend <> ctrlBlock.io.frontend 395 frontend.io.sfence <> integerBlock.io.fenceio.sfence 396 frontend.io.tlbCsr <> integerBlock.io.csrio.tlb 397 frontend.io.csrCtrl <> integerBlock.io.csrio.customCtrl 398 399 frontend.io.icacheMemAcq <> l1pluscache.io.req 400 l1pluscache.io.resp <> frontend.io.icacheMemGrant 401 l1pluscache.io.flush := frontend.io.l1plusFlush 402 frontend.io.fencei := integerBlock.io.fenceio.fencei 403 404 ctrlBlock.io.fromIntBlock <> integerBlock.io.toCtrlBlock 405 ctrlBlock.io.fromFpBlock <> floatBlock.io.toCtrlBlock 406 ctrlBlock.io.fromLsBlock <> memBlock.io.toCtrlBlock 407 ctrlBlock.io.toIntBlock <> integerBlock.io.fromCtrlBlock 408 ctrlBlock.io.toFpBlock <> floatBlock.io.fromCtrlBlock 409 ctrlBlock.io.toLsBlock <> memBlock.io.fromCtrlBlock 410 ctrlBlock.io.csrCtrl <> integerBlock.io.csrio.customCtrl 411 412 val memBlockWakeUpInt = memBlock.io.wakeUpOutInt.slow.map(WireInit(_)) 413 val memBlockWakeUpFp = memBlock.io.wakeUpOutFp.slow.map(WireInit(_)) 414 memBlock.io.wakeUpOutInt.slow.foreach(_.ready := true.B) 415 memBlock.io.wakeUpOutFp.slow.foreach(_.ready := true.B) 416 417 fpExuConfigs.zip(floatBlock.io.wakeUpOut.slow).filterNot(_._1.writeIntRf).map(_._2.ready := true.B) 418 val fpBlockWakeUpInt = fpExuConfigs 419 .zip(floatBlock.io.wakeUpOut.slow) 420 .filter(_._1.writeIntRf) 421 .map(_._2) 422 423 intExuConfigs.zip(integerBlock.io.wakeUpOut.slow).filterNot(_._1.writeFpRf).map(_._2.ready := true.B) 424 val intBlockWakeUpFp = intExuConfigs.filter(_.hasUncertainlatency) 425 .zip(integerBlock.io.wakeUpOut.slow) 426 .filter(_._1.writeFpRf) 427 .map(_._2) 428 429 integerBlock.io.wakeUpIn.slow <> fpBlockWakeUpInt ++ memBlockWakeUpInt 430 integerBlock.io.toMemBlock <> memBlock.io.fromIntBlock 431 integerBlock.io.memFastWakeUp <> memBlock.io.ldFastWakeUpInt 432 433 floatBlock.io.intWakeUpFp <> intBlockWakeUpFp 434 floatBlock.io.memWakeUpFp <> memBlockWakeUpFp 435 floatBlock.io.toMemBlock <> memBlock.io.fromFpBlock 436 437 val wakeUpMem = Seq( 438 integerBlock.io.wakeUpOut, 439 floatBlock.io.wakeUpOut, 440 ) 441 memBlock.io.wakeUpIn.fastUops <> wakeUpMem.flatMap(_.fastUops) 442 memBlock.io.wakeUpIn.fast <> wakeUpMem.flatMap(_.fast) 443 // Note: 'WireInit' is used to block 'ready's from memBlock, 444 // we don't need 'ready's from memBlock 445 memBlock.io.wakeUpIn.slow <> wakeUpMem.flatMap(_.slow.map(x => WireInit(x))) 446 memBlock.io.intWakeUpFp <> floatBlock.io.intWakeUpOut 447 448 integerBlock.io.csrio.hartId <> io.hartId 449 integerBlock.io.csrio.perf <> DontCare 450 integerBlock.io.csrio.perf.retiredInstr <> ctrlBlock.io.roqio.toCSR.perfinfo.retiredInstr 451 integerBlock.io.csrio.fpu.fflags <> ctrlBlock.io.roqio.toCSR.fflags 452 integerBlock.io.csrio.fpu.isIllegal := false.B 453 integerBlock.io.csrio.fpu.dirty_fs <> ctrlBlock.io.roqio.toCSR.dirty_fs 454 integerBlock.io.csrio.fpu.frm <> floatBlock.io.frm 455 integerBlock.io.csrio.exception <> ctrlBlock.io.roqio.exception 456 integerBlock.io.csrio.isXRet <> ctrlBlock.io.roqio.toCSR.isXRet 457 integerBlock.io.csrio.trapTarget <> ctrlBlock.io.roqio.toCSR.trapTarget 458 integerBlock.io.csrio.interrupt <> ctrlBlock.io.roqio.toCSR.intrBitSet 459 integerBlock.io.csrio.memExceptionVAddr <> memBlock.io.lsqio.exceptionAddr.vaddr 460 integerBlock.io.csrio.externalInterrupt <> io.externalInterrupt 461 462 integerBlock.io.fenceio.sfence <> memBlock.io.sfence 463 integerBlock.io.fenceio.sbuffer <> memBlock.io.fenceToSbuffer 464 465 memBlock.io.csrCtrl <> integerBlock.io.csrio.customCtrl 466 memBlock.io.tlbCsr <> integerBlock.io.csrio.tlb 467 memBlock.io.lsqio.roq <> ctrlBlock.io.roqio.lsq 468 memBlock.io.lsqio.exceptionAddr.lsIdx.lqIdx := ctrlBlock.io.roqio.exception.bits.uop.lqIdx 469 memBlock.io.lsqio.exceptionAddr.lsIdx.sqIdx := ctrlBlock.io.roqio.exception.bits.uop.sqIdx 470 memBlock.io.lsqio.exceptionAddr.isStore := CommitType.lsInstIsStore(ctrlBlock.io.roqio.exception.bits.uop.ctrl.commitType) 471 472 val itlbRepeater = Module(new PTWRepeater()) 473 val dtlbRepeater = Module(new PTWRepeater()) 474 itlbRepeater.io.tlb <> frontend.io.ptw 475 dtlbRepeater.io.tlb <> memBlock.io.ptw 476 itlbRepeater.io.sfence <> integerBlock.io.fenceio.sfence 477 dtlbRepeater.io.sfence <> integerBlock.io.fenceio.sfence 478 ptw.io.tlb(0) <> dtlbRepeater.io.ptw 479 ptw.io.tlb(1) <> itlbRepeater.io.ptw 480 ptw.io.sfence <> integerBlock.io.fenceio.sfence 481 ptw.io.csr <> integerBlock.io.csrio.tlb 482 483 // if l2 prefetcher use stream prefetch, it should be placed in XSCore 484 assert(l2PrefetcherParameters._type == "bop") 485 io.l2_pf_enable := integerBlock.io.csrio.customCtrl.l2_pf_enable 486 487 if (!env.FPGAPlatform) { 488 val id = hartIdCore() 489 difftestIO.fromSbuffer <> memBlock.difftestIO.fromSbuffer 490 difftestIO.fromSQ <> memBlock.difftestIO.fromSQ 491 difftestIO.fromCSR <> integerBlock.difftestIO.fromCSR 492 difftestIO.fromRoq <> ctrlBlock.difftestIO.fromRoq 493 difftestIO.fromAtomic <> memBlock.difftestIO.fromAtomic 494 difftestIO.fromPtw <> ptw.difftestIO 495 trapIO <> ctrlBlock.trapIO 496 497 val debugIntReg, debugFpReg = WireInit(VecInit(Seq.fill(32)(0.U(XLEN.W)))) 498 ExcitingUtils.addSink(debugIntReg, s"DEBUG_INT_ARCH_REG$id", ExcitingUtils.Debug) 499 ExcitingUtils.addSink(debugFpReg, s"DEBUG_FP_ARCH_REG$id", ExcitingUtils.Debug) 500 val debugArchReg = WireInit(VecInit(debugIntReg ++ debugFpReg)) 501 difftestIO.fromXSCore.r := debugArchReg 502 } 503 504} 505