1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import top.Parameters 6import xiangshan.backend._ 7import xiangshan.backend.dispatch.DispatchParameters 8import xiangshan.backend.exu.ExuParameters 9import xiangshan.backend.exu.Exu._ 10import xiangshan.frontend._ 11import xiangshan.mem._ 12import xiangshan.backend.fu.HasExceptionNO 13import xiangshan.cache.{DCache, DCacheParameters, ICache, ICacheParameters, L1plusCache, L1plusCacheParameters, PTW, Uncache} 14import chipsalliance.rocketchip.config 15import freechips.rocketchip.diplomacy.{AddressSet, LazyModule, LazyModuleImp} 16import freechips.rocketchip.tilelink.{TLBuffer, TLBundleParameters, TLCacheCork, TLClientNode, TLFilter, TLIdentityNode, TLToAXI4, TLWidthWidget, TLXbar} 17import freechips.rocketchip.devices.tilelink.{DevNullParams, TLError} 18import sifive.blocks.inclusivecache.{CacheParameters, InclusiveCache, InclusiveCacheMicroParameters} 19import freechips.rocketchip.amba.axi4.{AXI4Deinterleaver, AXI4Fragmenter, AXI4IdIndexer, AXI4IdentityNode, AXI4ToTL, AXI4UserYanker} 20import freechips.rocketchip.tile.HasFPUParameters 21import utils._ 22 23case class XSCoreParameters 24( 25 XLEN: Int = 64, 26 HasMExtension: Boolean = true, 27 HasCExtension: Boolean = true, 28 HasDiv: Boolean = true, 29 HasICache: Boolean = true, 30 HasDCache: Boolean = true, 31 EnableStoreQueue: Boolean = true, 32 AddrBits: Int = 64, 33 VAddrBits: Int = 39, 34 PAddrBits: Int = 40, 35 HasFPU: Boolean = true, 36 FectchWidth: Int = 8, 37 EnableBPU: Boolean = true, 38 EnableBPD: Boolean = true, 39 EnableRAS: Boolean = true, 40 EnableLB: Boolean = true, 41 EnableLoop: Boolean = true, 42 EnableSC: Boolean = false, 43 HistoryLength: Int = 64, 44 BtbSize: Int = 2048, 45 JbtacSize: Int = 1024, 46 JbtacBanks: Int = 8, 47 RasSize: Int = 16, 48 CacheLineSize: Int = 512, 49 UBtbWays: Int = 16, 50 BtbWays: Int = 2, 51 IBufSize: Int = 64, 52 DecodeWidth: Int = 6, 53 RenameWidth: Int = 6, 54 CommitWidth: Int = 6, 55 BrqSize: Int = 32, 56 IssQueSize: Int = 12, 57 NRPhyRegs: Int = 160, 58 NRIntReadPorts: Int = 14, 59 NRIntWritePorts: Int = 8, 60 NRFpReadPorts: Int = 14, 61 NRFpWritePorts: Int = 8, 62 LoadQueueSize: Int = 64, 63 StoreQueueSize: Int = 48, 64 RoqSize: Int = 192, 65 dpParams: DispatchParameters = DispatchParameters( 66 DqEnqWidth = 4, 67 IntDqSize = 128, 68 FpDqSize = 128, 69 LsDqSize = 96, 70 IntDqDeqWidth = 4, 71 FpDqDeqWidth = 4, 72 LsDqDeqWidth = 4, 73 IntDqReplayWidth = 4, 74 FpDqReplayWidth = 4, 75 LsDqReplayWidth = 4 76 ), 77 exuParameters: ExuParameters = ExuParameters( 78 JmpCnt = 1, 79 AluCnt = 4, 80 MulCnt = 0, 81 MduCnt = 2, 82 FmacCnt = 4, 83 FmiscCnt = 2, 84 FmiscDivSqrtCnt = 0, 85 LduCnt = 2, 86 StuCnt = 2 87 ), 88 LoadPipelineWidth: Int = 2, 89 StorePipelineWidth: Int = 2, 90 StoreBufferSize: Int = 16, 91 RefillSize: Int = 512, 92 TlbEntrySize: Int = 32, 93 TlbL2EntrySize: Int = 256, // or 512 94 PtwL1EntrySize: Int = 16, 95 PtwL2EntrySize: Int = 256, 96 NumPerfCounters: Int = 16 97) 98 99trait HasXSParameter { 100 101 val core = Parameters.get.coreParameters 102 val env = Parameters.get.envParameters 103 104 val XLEN = 64 105 val minFLen = 32 106 val fLen = 64 107 def xLen = 64 108 val HasMExtension = core.HasMExtension 109 val HasCExtension = core.HasCExtension 110 val HasDiv = core.HasDiv 111 val HasIcache = core.HasICache 112 val HasDcache = core.HasDCache 113 val EnableStoreQueue = core.EnableStoreQueue 114 val AddrBits = core.AddrBits // AddrBits is used in some cases 115 val VAddrBits = core.VAddrBits // VAddrBits is Virtual Memory addr bits 116 val PAddrBits = core.PAddrBits // PAddrBits is Phyical Memory addr bits 117 val AddrBytes = AddrBits / 8 // unused 118 val DataBits = XLEN 119 val DataBytes = DataBits / 8 120 val HasFPU = core.HasFPU 121 val FetchWidth = core.FectchWidth 122 val PredictWidth = FetchWidth * 2 123 val EnableBPU = core.EnableBPU 124 val EnableBPD = core.EnableBPD // enable backing predictor(like Tage) in BPUStage3 125 val EnableRAS = core.EnableRAS 126 val EnableLB = core.EnableLB 127 val EnableLoop = core.EnableLoop 128 val EnableSC = core.EnableSC 129 val HistoryLength = core.HistoryLength 130 val BtbSize = core.BtbSize 131 // val BtbWays = 4 132 val BtbBanks = PredictWidth 133 // val BtbSets = BtbSize / BtbWays 134 val JbtacSize = core.JbtacSize 135 val JbtacBanks = core.JbtacBanks 136 val RasSize = core.RasSize 137 val CacheLineSize = core.CacheLineSize 138 val CacheLineHalfWord = CacheLineSize / 16 139 val ExtHistoryLength = HistoryLength + 64 140 val UBtbWays = core.UBtbWays 141 val BtbWays = core.BtbWays 142 val IBufSize = core.IBufSize 143 val DecodeWidth = core.DecodeWidth 144 val RenameWidth = core.RenameWidth 145 val CommitWidth = core.CommitWidth 146 val BrqSize = core.BrqSize 147 val IssQueSize = core.IssQueSize 148 val BrTagWidth = log2Up(BrqSize) 149 val NRPhyRegs = core.NRPhyRegs 150 val PhyRegIdxWidth = log2Up(NRPhyRegs) 151 val RoqSize = core.RoqSize 152 val LoadQueueSize = core.LoadQueueSize 153 val StoreQueueSize = core.StoreQueueSize 154 val dpParams = core.dpParams 155 val ReplayWidth = dpParams.IntDqReplayWidth + dpParams.FpDqReplayWidth + dpParams.LsDqReplayWidth 156 val exuParameters = core.exuParameters 157 val NRIntReadPorts = core.NRIntReadPorts 158 val NRIntWritePorts = core.NRIntWritePorts 159 val NRMemReadPorts = exuParameters.LduCnt + 2*exuParameters.StuCnt 160 val NRFpReadPorts = core.NRFpReadPorts 161 val NRFpWritePorts = core.NRFpWritePorts 162 val LoadPipelineWidth = core.LoadPipelineWidth 163 val StorePipelineWidth = core.StorePipelineWidth 164 val StoreBufferSize = core.StoreBufferSize 165 val RefillSize = core.RefillSize 166 val DTLBWidth = core.LoadPipelineWidth + core.StorePipelineWidth 167 val TlbEntrySize = core.TlbEntrySize 168 val TlbL2EntrySize = core.TlbL2EntrySize 169 val PtwL1EntrySize = core.PtwL1EntrySize 170 val PtwL2EntrySize = core.PtwL2EntrySize 171 val NumPerfCounters = core.NumPerfCounters 172 173 val icacheParameters = ICacheParameters( 174 nMissEntries = 2 175 ) 176 177 val l1plusCacheParameters = L1plusCacheParameters( 178 tagECC = Some("secded"), 179 dataECC = Some("secded"), 180 nMissEntries = 8 181 ) 182 183 val dcacheParameters = DCacheParameters( 184 tagECC = Some("secded"), 185 dataECC = Some("secded"), 186 nMissEntries = 16, 187 nLoadMissEntries = 8, 188 nStoreMissEntries = 8 189 ) 190 191 val LRSCCycles = 100 192 193 194 // cache hierarchy configurations 195 val l1BusDataWidth = 256 196 197 // L2 configurations 198 val L1BusWidth = 256 199 val L2Size = 512 * 1024 // 512KB 200 val L2BlockSize = 64 201 val L2NWays = 8 202 val L2NSets = L2Size / L2BlockSize / L2NWays 203 204 // L3 configurations 205 val L2BusWidth = 256 206 val L3Size = 4 * 1024 * 1024 // 4MB 207 val L3BlockSize = 64 208 val L3NBanks = 4 209 val L3NWays = 8 210 val L3NSets = L3Size / L3BlockSize / L3NBanks / L3NWays 211 212 // on chip network configurations 213 val L3BusWidth = 256 214} 215 216trait HasXSLog { this: RawModule => 217 implicit val moduleName: String = this.name 218} 219 220abstract class XSModule extends MultiIOModule 221 with HasXSParameter 222 with HasExceptionNO 223 with HasXSLog 224 with HasFPUParameters 225{ 226 def io: Record 227} 228 229//remove this trait after impl module logic 230trait NeedImpl { this: RawModule => 231 override protected def IO[T <: Data](iodef: T): T = { 232 println(s"[Warn]: (${this.name}) please reomve 'NeedImpl' after implement this module") 233 val io = chisel3.experimental.IO(iodef) 234 io <> DontCare 235 io 236 } 237} 238 239abstract class XSBundle extends Bundle 240 with HasXSParameter 241 242case class EnviromentParameters 243( 244 FPGAPlatform: Boolean = true, 245 EnableDebug: Boolean = false 246) 247 248object AddressSpace extends HasXSParameter { 249 // (start, size) 250 // address out of MMIO will be considered as DRAM 251 def mmio = List( 252 (0x00000000L, 0x40000000L), // internal devices, such as CLINT and PLIC 253 (0x40000000L, 0x40000000L) // external devices 254 ) 255 256 def isMMIO(addr: UInt): Bool = mmio.map(range => { 257 require(isPow2(range._2)) 258 val bits = log2Up(range._2) 259 (addr ^ range._1.U)(PAddrBits-1, bits) === 0.U 260 }).reduce(_ || _) 261} 262 263 264 265class XSCore()(implicit p: config.Parameters) extends LazyModule with HasXSParameter { 266 267 // outer facing nodes 268 val dcache = LazyModule(new DCache()) 269 val uncache = LazyModule(new Uncache()) 270 val l1pluscache = LazyModule(new L1plusCache()) 271 val ptw = LazyModule(new PTW()) 272 273 lazy val module = new XSCoreImp(this) 274} 275 276class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer) 277 with HasXSParameter 278 with HasExeBlockHelper 279{ 280 val io = IO(new Bundle { 281 val externalInterrupt = new ExternalInterruptIO 282 }) 283 284 println(s"FPGAPlatform:${env.FPGAPlatform} EnableDebug:${env.EnableDebug}") 285 286 // to fast wake up fp, mem rs 287 val intBlockFastWakeUpFp = intExuConfigs.filter(fpFastFilter) 288 val intBlockSlowWakeUpFp = intExuConfigs.filter(fpSlowFilter) 289 val intBlockFastWakeUpInt = intExuConfigs.filter(intFastFilter) 290 val intBlockSlowWakeUpInt = intExuConfigs.filter(intSlowFilter) 291 292 val fpBlockFastWakeUpFp = fpExuConfigs.filter(fpFastFilter) 293 val fpBlockSlowWakeUpFp = fpExuConfigs.filter(fpSlowFilter) 294 val fpBlockFastWakeUpInt = fpExuConfigs.filter(intFastFilter) 295 val fpBlockSlowWakeUpInt = fpExuConfigs.filter(intSlowFilter) 296 297 val frontend = Module(new Frontend) 298 val ctrlBlock = Module(new CtrlBlock) 299 val integerBlock = Module(new IntegerBlock( 300 fastWakeUpIn = fpBlockFastWakeUpInt, 301 slowWakeUpIn = fpBlockSlowWakeUpInt ++ loadExuConfigs, 302 fastFpOut = intBlockFastWakeUpFp, 303 slowFpOut = intBlockSlowWakeUpFp, 304 fastIntOut = intBlockFastWakeUpInt, 305 slowIntOut = intBlockSlowWakeUpInt 306 )) 307 val floatBlock = Module(new FloatBlock( 308 fastWakeUpIn = intBlockFastWakeUpFp, 309 slowWakeUpIn = intBlockSlowWakeUpFp ++ loadExuConfigs, 310 fastFpOut = fpBlockFastWakeUpFp, 311 slowFpOut = fpBlockSlowWakeUpFp, 312 fastIntOut = fpBlockFastWakeUpInt, 313 slowIntOut = fpBlockSlowWakeUpInt 314 )) 315 val memBlock = Module(new MemBlock( 316 fastWakeUpIn = intBlockFastWakeUpInt ++ intBlockFastWakeUpFp ++ fpBlockFastWakeUpInt ++ fpBlockFastWakeUpFp, 317 slowWakeUpIn = intBlockSlowWakeUpInt ++ intBlockSlowWakeUpFp ++ fpBlockSlowWakeUpInt ++ fpBlockSlowWakeUpFp, 318 fastFpOut = Seq(), 319 slowFpOut = loadExuConfigs, 320 fastIntOut = Seq(), 321 slowIntOut = loadExuConfigs 322 )) 323 324 val dcache = outer.dcache.module 325 val uncache = outer.uncache.module 326 val l1pluscache = outer.l1pluscache.module 327 val ptw = outer.ptw.module 328 val icache = Module(new ICache) 329 330 frontend.io.backend <> ctrlBlock.io.frontend 331 frontend.io.icacheResp <> icache.io.resp 332 frontend.io.icacheToTlb <> icache.io.tlb 333 icache.io.req <> frontend.io.icacheReq 334 icache.io.flush <> frontend.io.icacheFlush 335 frontend.io.sfence <> integerBlock.io.fenceio.sfence 336 frontend.io.tlbCsr <> integerBlock.io.csrio.tlb 337 338 icache.io.mem_acquire <> l1pluscache.io.req 339 l1pluscache.io.resp <> icache.io.mem_grant 340 l1pluscache.io.flush := icache.io.l1plusflush 341 icache.io.fencei := integerBlock.io.fenceio.fencei 342 343 ctrlBlock.io.fromIntBlock <> integerBlock.io.toCtrlBlock 344 ctrlBlock.io.fromFpBlock <> floatBlock.io.toCtrlBlock 345 ctrlBlock.io.fromLsBlock <> memBlock.io.toCtrlBlock 346 ctrlBlock.io.toIntBlock <> integerBlock.io.fromCtrlBlock 347 ctrlBlock.io.toFpBlock <> floatBlock.io.fromCtrlBlock 348 ctrlBlock.io.toLsBlock <> memBlock.io.fromCtrlBlock 349 350 integerBlock.io.wakeUpIn.fastUops <> floatBlock.io.wakeUpIntOut.fastUops 351 integerBlock.io.wakeUpIn.fast <> floatBlock.io.wakeUpIntOut.fast 352 integerBlock.io.wakeUpIn.slow <> floatBlock.io.wakeUpIntOut.slow ++ memBlock.io.wakeUpIntOut.slow 353 354 floatBlock.io.wakeUpIn.fastUops <> integerBlock.io.wakeUpFpOut.fastUops 355 floatBlock.io.wakeUpIn.fast <> integerBlock.io.wakeUpFpOut.fast 356 floatBlock.io.wakeUpIn.slow <> integerBlock.io.wakeUpFpOut.slow ++ memBlock.io.wakeUpFpOut.slow 357 358 359 integerBlock.io.wakeUpIntOut.fast.map(_.ready := true.B) 360 integerBlock.io.wakeUpIntOut.slow.map(_.ready := true.B) 361 floatBlock.io.wakeUpFpOut.fast.map(_.ready := true.B) 362 floatBlock.io.wakeUpFpOut.slow.map(_.ready := true.B) 363 364 val wakeUpMem = Seq( 365 integerBlock.io.wakeUpIntOut, 366 integerBlock.io.wakeUpFpOut, 367 floatBlock.io.wakeUpIntOut, 368 floatBlock.io.wakeUpFpOut 369 ) 370 memBlock.io.wakeUpIn.fastUops <> wakeUpMem.flatMap(_.fastUops) 371 memBlock.io.wakeUpIn.fast <> wakeUpMem.flatMap(w => w.fast.map(f => { 372 val raw = WireInit(f) 373 raw 374 })) 375 memBlock.io.wakeUpIn.slow <> wakeUpMem.flatMap(w => w.slow.map(s => { 376 val raw = WireInit(s) 377 raw 378 })) 379 380 integerBlock.io.csrio.fflags <> ctrlBlock.io.roqio.toCSR.fflags 381 integerBlock.io.csrio.dirty_fs <> ctrlBlock.io.roqio.toCSR.dirty_fs 382 integerBlock.io.csrio.exception <> ctrlBlock.io.roqio.exception 383 integerBlock.io.csrio.isInterrupt <> ctrlBlock.io.roqio.isInterrupt 384 integerBlock.io.csrio.trapTarget <> ctrlBlock.io.roqio.toCSR.trapTarget 385 integerBlock.io.csrio.interrupt <> ctrlBlock.io.roqio.toCSR.intrBitSet 386 integerBlock.io.csrio.memExceptionVAddr <> memBlock.io.lsqio.exceptionAddr.vaddr 387 integerBlock.io.csrio.externalInterrupt <> io.externalInterrupt 388 integerBlock.io.csrio.tlb <> memBlock.io.tlbCsr 389 integerBlock.io.fenceio.sfence <> memBlock.io.sfence 390 integerBlock.io.fenceio.sbuffer <> memBlock.io.fenceToSbuffer 391 392 floatBlock.io.frm <> integerBlock.io.csrio.frm 393 394 memBlock.io.lsqio.commits <> ctrlBlock.io.roqio.commits 395 memBlock.io.lsqio.roqDeqPtr <> ctrlBlock.io.roqio.roqDeqPtr 396 memBlock.io.lsqio.oldestStore <> ctrlBlock.io.oldestStore 397 memBlock.io.lsqio.exceptionAddr.lsIdx.lqIdx := ctrlBlock.io.roqio.exception.bits.lqIdx 398 memBlock.io.lsqio.exceptionAddr.lsIdx.sqIdx := ctrlBlock.io.roqio.exception.bits.sqIdx 399 memBlock.io.lsqio.exceptionAddr.isStore := CommitType.lsInstIsStore(ctrlBlock.io.roqio.exception.bits.ctrl.commitType) 400 401 ptw.io.tlb(0) <> memBlock.io.ptw 402 ptw.io.tlb(1) <> frontend.io.ptw 403 ptw.io.sfence <> integerBlock.io.fenceio.sfence 404 ptw.io.csr <> integerBlock.io.csrio.tlb 405 406 dcache.io.lsu.load <> memBlock.io.dcache.loadUnitToDcacheVec 407 dcache.io.lsu.lsq <> memBlock.io.dcache.loadMiss 408 dcache.io.lsu.atomics <> memBlock.io.dcache.atomics 409 dcache.io.lsu.store <> memBlock.io.dcache.sbufferToDcache 410 uncache.io.lsq <> memBlock.io.dcache.uncache 411 412 if (!env.FPGAPlatform) { 413 val debugIntReg, debugFpReg = WireInit(VecInit(Seq.fill(32)(0.U(XLEN.W)))) 414 ExcitingUtils.addSink(debugIntReg, "DEBUG_INT_ARCH_REG", ExcitingUtils.Debug) 415 ExcitingUtils.addSink(debugFpReg, "DEBUG_FP_ARCH_REG", ExcitingUtils.Debug) 416 val debugArchReg = WireInit(VecInit(debugIntReg ++ debugFpReg)) 417 ExcitingUtils.addSource(debugArchReg, "difftestRegs", ExcitingUtils.Debug) 418 } 419 420} 421