1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import bus.simplebus._ 6import noop.{Cache, CacheConfig, HasExceptionNO, TLB, TLBConfig} 7import xiangshan.backend._ 8import xiangshan.backend.dispatch.DP1Parameters 9import xiangshan.backend.exu.ExuParameters 10import xiangshan.frontend._ 11import utils._ 12 13trait HasXSParameter { 14 val XLEN = 64 15 val HasMExtension = true 16 val HasCExtension = true 17 val HasDiv = true 18 val HasIcache = true 19 val HasDcache = true 20 val EnableStoreQueue = false 21 val AddrBits = 64 // AddrBits is used in some cases 22 val VAddrBits = 39 // VAddrBits is Virtual Memory addr bits 23 val PAddrBits = 32 // PAddrBits is Phyical Memory addr bits 24 val AddrBytes = AddrBits / 8 // unused 25 val DataBits = XLEN 26 val DataBytes = DataBits / 8 27 val CacheLineSize = 512 28 val CacheLineHalfWord = CacheLineSize / 16 29 val HasFPU = true 30 val FetchWidth = 8 31 val PredictWidth = FetchWidth * 2 32 val EnableBPU = true 33 val EnableBPD = false // enable backing predictor(like Tage) in BPUStage3 34 val HistoryLength = 64 35 val BtbSize = 256 36 // val BtbWays = 4 37 val BtbBanks = PredictWidth 38 // val BtbSets = BtbSize / BtbWays 39 val JbtacSize = 1024 40 val JbtacBanks = 8 41 val RasSize = 16 42 val IBufSize = 64 43 val DecodeWidth = 6 44 val RenameWidth = 6 45 val CommitWidth = 6 46 val BrqSize = 16 47 val IssQueSize = 8 48 val BrTagWidth = log2Up(BrqSize) 49 val NRPhyRegs = 128 50 val PhyRegIdxWidth = log2Up(NRPhyRegs) 51 val NRReadPorts = 14 52 val NRWritePorts = 8 53 val RoqSize = 32 54 val InnerRoqIdxWidth = log2Up(RoqSize) 55 val RoqIdxWidth = InnerRoqIdxWidth + 1 56 val IntDqDeqWidth = 4 57 val FpDqDeqWidth = 4 58 val LsDqDeqWidth = 4 59 val dp1Paremeters = DP1Parameters( 60 IntDqSize = 16, 61 FpDqSize = 16, 62 LsDqSize = 16 63 ) 64 val exuParameters = ExuParameters( 65 JmpCnt = 1, 66 AluCnt = 4, 67 MulCnt = 1, 68 MduCnt = 1, 69 FmacCnt = 0, 70 FmiscCnt = 0, 71 FmiscDivSqrtCnt = 0, 72 LduCnt = 0, 73 StuCnt = 1 74 ) 75} 76 77trait HasXSLog { this: Module => 78 implicit val moduleName: String = this.name 79} 80 81abstract class XSModule extends Module 82 with HasXSParameter 83 with HasExceptionNO 84 with HasXSLog 85 86//remove this trait after impl module logic 87trait NeedImpl { this: Module => 88 override protected def IO[T <: Data](iodef: T): T = { 89 val io = chisel3.experimental.IO(iodef) 90 io <> DontCare 91 io 92 } 93} 94 95abstract class XSBundle extends Bundle 96 with HasXSParameter 97 with HasTageParameter 98 99case class XSConfig 100( 101 FPGAPlatform: Boolean = true, 102 EnableDebug: Boolean = true 103) 104 105object AddressSpace extends HasXSParameter { 106 // (start, size) 107 // address out of MMIO will be considered as DRAM 108 def mmio = List( 109 (0x30000000L, 0x10000000L), // internal devices, such as CLINT and PLIC 110 (0x40000000L, 0x40000000L) // external devices 111 ) 112 113 def isMMIO(addr: UInt): Bool = mmio.map(range => { 114 require(isPow2(range._2)) 115 val bits = log2Up(range._2) 116 (addr ^ range._1.U)(PAddrBits-1, bits) === 0.U 117 }).reduce(_ || _) 118} 119 120 121class XSCore(implicit p: XSConfig) extends XSModule { 122 val io = IO(new Bundle { 123 val imem = new SimpleBusC 124 val dmem = new SimpleBusC 125 val mmio = new SimpleBusUC 126 val frontend = Flipped(new SimpleBusUC()) 127 }) 128 129 io.imem <> DontCare 130 131 val dmemXbar = Module(new SimpleBusCrossbarNto1(3)) 132 133 val front = Module(new Frontend) 134 val backend = Module(new Backend) 135 136 front.io.backend <> backend.io.frontend 137 138 backend.io.memMMU.imem <> DontCare 139 140 val dtlb = TLB( 141 in = backend.io.dmem, 142 mem = dmemXbar.io.in(1), 143 flush = false.B, 144 csrMMU = backend.io.memMMU.dmem 145 )(TLBConfig(name = "dtlb", totalEntry = 64)) 146 dmemXbar.io.in(0) <> dtlb.io.out 147 dmemXbar.io.in(2) <> io.frontend 148 149 io.dmem <> Cache( 150 in = dmemXbar.io.out, 151 mmio = Seq(io.mmio), 152 flush = "b00".U, 153 empty = dtlb.io.cacheEmpty, 154 enable = HasDcache 155 )(CacheConfig(name = "dcache")) 156 157 XSDebug("(req valid, ready | resp valid, ready) \n") 158 XSDebug("c-mem(%x %x %x| %x %x) c-coh(%x %x %x| %x %x) cache (%x %x %x| %x %x) tlb (%x %x %x| %x %x)\n", 159 io.dmem.mem.req.valid, 160 io.dmem.mem.req.ready, 161 io.dmem.mem.req.bits.addr, 162 io.dmem.mem.resp.valid, 163 io.dmem.mem.resp.ready, 164 io.dmem.coh.req.valid, 165 io.dmem.coh.req.ready, 166 io.dmem.coh.req.bits.addr, 167 io.dmem.coh.resp.valid, 168 io.dmem.coh.resp.ready, 169 dmemXbar.io.out.req.valid, 170 dmemXbar.io.out.req.ready, 171 dmemXbar.io.out.req.bits.addr, 172 dmemXbar.io.out.resp.valid, 173 dmemXbar.io.out.resp.ready, 174 backend.io.dmem.req.valid, 175 backend.io.dmem.req.ready, 176 backend.io.dmem.req.bits.addr, 177 backend.io.dmem.resp.valid, 178 backend.io.dmem.resp.ready 179 ) 180} 181