xref: /XiangShan/src/main/scala/xiangshan/XSCore.scala (revision eb8b97acdf47c47dfdb29af248b513d95b4eab90) 
1package xiangshan
2
3import chisel3._
4import chisel3.util._
5import top.Parameters
6import xiangshan.backend._
7import xiangshan.backend.dispatch.DispatchParameters
8import xiangshan.backend.exu.ExuParameters
9import xiangshan.backend.exu.Exu._
10import xiangshan.frontend._
11import xiangshan.mem._
12import xiangshan.backend.fu.HasExceptionNO
13import xiangshan.cache.{DCacheParameters, ICacheParameters, L1plusCache, L1plusCacheParameters, PTW, PTWRepeater}
14import xiangshan.cache.prefetch._
15import chipsalliance.rocketchip.config
16import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
17import freechips.rocketchip.tile.HasFPUParameters
18import utils._
19
20object hartIdCore extends (() => Int) {
21  var x = 0
22
23  def apply(): Int = {
24    x = x + 1
25    x - 1
26  }
27}
28
29case class XSCoreParameters
30(
31  XLEN: Int = 64,
32  HasMExtension: Boolean = true,
33  HasCExtension: Boolean = true,
34  HasDiv: Boolean = true,
35  HasICache: Boolean = true,
36  HasDCache: Boolean = true,
37  EnableStoreQueue: Boolean = true,
38  AddrBits: Int = 64,
39  VAddrBits: Int = 39,
40  PAddrBits: Int = 40,
41  HasFPU: Boolean = true,
42  FetchWidth: Int = 8,
43  EnableBPU: Boolean = true,
44  EnableBPD: Boolean = true,
45  EnableRAS: Boolean = true,
46  EnableLB: Boolean = false,
47  EnableLoop: Boolean = true,
48  EnableSC: Boolean = true,
49  EnbaleTlbDebug: Boolean = false,
50  EnableJal: Boolean = false,
51  EnableUBTB: Boolean = true,
52  HistoryLength: Int = 64,
53  BtbSize: Int = 2048,
54  JbtacSize: Int = 1024,
55  JbtacBanks: Int = 8,
56  RasSize: Int = 16,
57  CacheLineSize: Int = 512,
58  UBtbWays: Int = 16,
59  BtbWays: Int = 2,
60
61  EnableL1plusPrefetcher: Boolean = true,
62  IBufSize: Int = 32,
63  DecodeWidth: Int = 6,
64  RenameWidth: Int = 6,
65  CommitWidth: Int = 6,
66  BrqSize: Int = 32,
67  FtqSize: Int = 48,
68  IssQueSize: Int = 12,
69  NRPhyRegs: Int = 160,
70  NRIntReadPorts: Int = 14,
71  NRIntWritePorts: Int = 8,
72  NRFpReadPorts: Int = 14,
73  NRFpWritePorts: Int = 8,
74  LoadQueueSize: Int = 64,
75  StoreQueueSize: Int = 48,
76  RoqSize: Int = 192,
77  dpParams: DispatchParameters = DispatchParameters(
78    IntDqSize = 16,
79    FpDqSize = 16,
80    LsDqSize = 16,
81    IntDqDeqWidth = 4,
82    FpDqDeqWidth = 4,
83    LsDqDeqWidth = 4
84  ),
85  exuParameters: ExuParameters = ExuParameters(
86    JmpCnt = 1,
87    AluCnt = 4,
88    MulCnt = 0,
89    MduCnt = 2,
90    FmacCnt = 4,
91    FmiscCnt = 2,
92    FmiscDivSqrtCnt = 0,
93    LduCnt = 2,
94    StuCnt = 2
95  ),
96  LoadPipelineWidth: Int = 2,
97  StorePipelineWidth: Int = 2,
98  StoreBufferSize: Int = 16,
99  RefillSize: Int = 512,
100  TlbEntrySize: Int = 32,
101  TlbSPEntrySize: Int = 4,
102  PtwL3EntrySize: Int = 4096, //(256 * 16) or 512
103  PtwSPEntrySize: Int = 16,
104  PtwL1EntrySize: Int = 16,
105  PtwL2EntrySize: Int = 2048, //(256 * 8)
106  NumPerfCounters: Int = 16,
107  NrExtIntr: Int = 150,
108  PerfRealTime: Boolean = false,
109  PerfIntervalBits: Int = 15
110)
111
112trait HasXSParameter {
113
114  val coreParams = Parameters.get.coreParameters
115  val env = Parameters.get.envParameters
116
117  val XLEN = 64
118  val minFLen = 32
119  val fLen = 64
120
121  def xLen = 64
122
123  val HasMExtension = coreParams.HasMExtension
124  val HasCExtension = coreParams.HasCExtension
125  val HasDiv = coreParams.HasDiv
126  val HasIcache = coreParams.HasICache
127  val HasDcache = coreParams.HasDCache
128  val EnableStoreQueue = coreParams.EnableStoreQueue
129  val AddrBits = coreParams.AddrBits // AddrBits is used in some cases
130  val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits
131  val PAddrBits = coreParams.PAddrBits // PAddrBits is Phyical Memory addr bits
132  val AddrBytes = AddrBits / 8 // unused
133  val DataBits = XLEN
134  val DataBytes = DataBits / 8
135  val HasFPU = coreParams.HasFPU
136  val FetchWidth = coreParams.FetchWidth
137  val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1)
138  val EnableBPU = coreParams.EnableBPU
139  val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3
140  val EnableRAS = coreParams.EnableRAS
141  val EnableLB = coreParams.EnableLB
142  val EnableLoop = coreParams.EnableLoop
143  val EnableSC = coreParams.EnableSC
144  val EnbaleTlbDebug = coreParams.EnbaleTlbDebug
145  val HistoryLength = coreParams.HistoryLength
146  val BtbSize = coreParams.BtbSize
147  // val BtbWays = 4
148  val BtbBanks = PredictWidth
149  // val BtbSets = BtbSize / BtbWays
150  val JbtacSize = coreParams.JbtacSize
151  val JbtacBanks = coreParams.JbtacBanks
152  val RasSize = coreParams.RasSize
153  val CacheLineSize = coreParams.CacheLineSize
154  val CacheLineHalfWord = CacheLineSize / 16
155  val ExtHistoryLength = HistoryLength + 64
156  val UBtbWays = coreParams.UBtbWays
157  val BtbWays = coreParams.BtbWays
158  val EnableL1plusPrefetcher = coreParams.EnableL1plusPrefetcher
159  val IBufSize = coreParams.IBufSize
160  val DecodeWidth = coreParams.DecodeWidth
161  val RenameWidth = coreParams.RenameWidth
162  val CommitWidth = coreParams.CommitWidth
163  val BrqSize = coreParams.BrqSize
164  val FtqSize = coreParams.FtqSize
165  val IssQueSize = coreParams.IssQueSize
166  val BrTagWidth = log2Up(BrqSize)
167  val NRPhyRegs = coreParams.NRPhyRegs
168  val PhyRegIdxWidth = log2Up(NRPhyRegs)
169  val RoqSize = coreParams.RoqSize
170  val LoadQueueSize = coreParams.LoadQueueSize
171  val StoreQueueSize = coreParams.StoreQueueSize
172  val dpParams = coreParams.dpParams
173  val exuParameters = coreParams.exuParameters
174  val NRIntReadPorts = coreParams.NRIntReadPorts
175  val NRIntWritePorts = coreParams.NRIntWritePorts
176  val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt
177  val NRFpReadPorts = coreParams.NRFpReadPorts
178  val NRFpWritePorts = coreParams.NRFpWritePorts
179  val LoadPipelineWidth = coreParams.LoadPipelineWidth
180  val StorePipelineWidth = coreParams.StorePipelineWidth
181  val StoreBufferSize = coreParams.StoreBufferSize
182  val RefillSize = coreParams.RefillSize
183  val DTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth
184  val TlbEntrySize = coreParams.TlbEntrySize
185  val TlbSPEntrySize = coreParams.TlbSPEntrySize
186  val PtwL3EntrySize = coreParams.PtwL3EntrySize
187  val PtwSPEntrySize = coreParams.PtwSPEntrySize
188  val PtwL1EntrySize = coreParams.PtwL1EntrySize
189  val PtwL2EntrySize = coreParams.PtwL2EntrySize
190  val NumPerfCounters = coreParams.NumPerfCounters
191  val NrExtIntr = coreParams.NrExtIntr
192  val PerfRealTime = coreParams.PerfRealTime
193  val PerfIntervalBits = coreParams.PerfIntervalBits
194
195  val instBytes = if (HasCExtension) 2 else 4
196  val instOffsetBits = log2Ceil(instBytes)
197
198  val icacheParameters = ICacheParameters(
199    tagECC = Some("parity"),
200    dataECC = Some("parity"),
201    replacer = Some("setplru"),
202    nMissEntries = 2
203  )
204
205  val l1plusCacheParameters = L1plusCacheParameters(
206    tagECC = Some("secded"),
207    dataECC = Some("secded"),
208    replacer = Some("setplru"),
209    nMissEntries = 8
210  )
211
212  val dcacheParameters = DCacheParameters(
213    tagECC = Some("none"),
214    dataECC = Some("none"),
215    nMissEntries = 16,
216    nProbeEntries = 16,
217    nReleaseEntries = 16,
218    nStoreReplayEntries = 16
219  )
220
221  val LRSCCycles = 100
222
223
224  // cache hierarchy configurations
225  val l1BusDataWidth = 256
226
227  // L2 configurations
228  val L1BusWidth = 256
229  val L2Size = 512 * 1024 // 512KB
230  val L2BlockSize = 64
231  val L2NWays = 8
232  val L2NSets = L2Size / L2BlockSize / L2NWays
233
234  // L3 configurations
235  val L2BusWidth = 256
236  val L3Size = 4 * 1024 * 1024 // 4MB
237  val L3BlockSize = 64
238  val L3NBanks = 4
239  val L3NWays = 8
240  val L3NSets = L3Size / L3BlockSize / L3NBanks / L3NWays
241
242  // on chip network configurations
243  val L3BusWidth = 256
244
245  // icache prefetcher
246  val l1plusPrefetcherParameters = L1plusPrefetcherParameters(
247    enable = true,
248    _type = "stream",
249    streamParams = StreamPrefetchParameters(
250      streamCnt = 2,
251      streamSize = 4,
252      ageWidth = 4,
253      blockBytes = l1plusCacheParameters.blockBytes,
254      reallocStreamOnMissInstantly = true,
255      cacheName = "icache"
256    )
257  )
258
259  // dcache prefetcher
260  val l2PrefetcherParameters = L2PrefetcherParameters(
261    enable = true,
262    _type = "bop", // "stream" or "bop"
263    streamParams = StreamPrefetchParameters(
264      streamCnt = 4,
265      streamSize = 4,
266      ageWidth = 4,
267      blockBytes = L2BlockSize,
268      reallocStreamOnMissInstantly = true,
269      cacheName = "dcache"
270    ),
271    bopParams = BOPParameters(
272      rrTableEntries = 256,
273      rrTagBits = 12,
274      scoreBits = 5,
275      roundMax = 50,
276      badScore = 1,
277      blockBytes = L2BlockSize,
278      nEntries = dcacheParameters.nMissEntries * 2 // TODO: this is too large
279    ),
280  )
281}
282
283trait HasXSLog {
284  this: RawModule =>
285  implicit val moduleName: String = this.name
286}
287
288abstract class XSModule extends MultiIOModule
289  with HasXSParameter
290  with HasExceptionNO
291  with HasXSLog
292  with HasFPUParameters {
293  def io: Record
294}
295
296//remove this trait after impl module logic
297trait NeedImpl {
298  this: RawModule =>
299  override protected def IO[T <: Data](iodef: T): T = {
300    println(s"[Warn]: (${this.name}) please reomve 'NeedImpl' after implement this module")
301    val io = chisel3.experimental.IO(iodef)
302    io <> DontCare
303    io
304  }
305}
306
307abstract class XSBundle extends Bundle
308  with HasXSParameter
309
310case class EnviromentParameters
311(
312  FPGAPlatform: Boolean = true,
313  EnableDebug: Boolean = false,
314  EnablePerfDebug: Boolean = true,
315  DualCore: Boolean = false
316)
317
318// object AddressSpace extends HasXSParameter {
319//   // (start, size)
320//   // address out of MMIO will be considered as DRAM
321//   def mmio = List(
322//     (0x00000000L, 0x40000000L),  // internal devices, such as CLINT and PLIC
323//     (0x40000000L, 0x40000000L)   // external devices
324//   )
325
326//   def isMMIO(addr: UInt): Bool = mmio.map(range => {
327//     require(isPow2(range._2))
328//     val bits = log2Up(range._2)
329//     (addr ^ range._1.U)(PAddrBits-1, bits) === 0.U
330//   }).reduce(_ || _)
331// }
332
333
334class XSCore()(implicit p: config.Parameters) extends LazyModule
335  with HasXSParameter
336  with HasExeBlockHelper {
337  // outer facing nodes
338  val frontend = LazyModule(new Frontend())
339  val l1pluscache = LazyModule(new L1plusCache())
340  val ptw = LazyModule(new PTW())
341  val memBlock = LazyModule(new MemBlock(
342    fastWakeUpIn = intExuConfigs.filter(_.hasCertainLatency),
343    slowWakeUpIn = intExuConfigs.filter(_.hasUncertainlatency) ++ fpExuConfigs,
344    fastWakeUpOut = Seq(),
345    slowWakeUpOut = loadExuConfigs,
346    numIntWakeUpFp = intExuConfigs.count(_.writeFpRf)
347  ))
348
349  lazy val module = new XSCoreImp(this)
350}
351
352class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer)
353  with HasXSParameter
354  with HasExeBlockHelper {
355  val io = IO(new Bundle {
356    val hartId = Input(UInt(64.W))
357    val externalInterrupt = new ExternalInterruptIO
358    val l2_pf_enable = Output(Bool())
359  })
360
361  val difftestIO = IO(new DifftestBundle())
362  difftestIO <> DontCare
363
364  val trapIO = IO(new TrapIO())
365  trapIO <> DontCare
366
367  println(s"FPGAPlatform:${env.FPGAPlatform} EnableDebug:${env.EnableDebug}")
368  AddressSpace.checkMemmap()
369  AddressSpace.printMemmap()
370
371  // to fast wake up fp, mem rs
372  val intBlockFastWakeUp = intExuConfigs.filter(_.hasCertainLatency)
373  val intBlockSlowWakeUp = intExuConfigs.filter(_.hasUncertainlatency)
374
375  val ctrlBlock = Module(new CtrlBlock)
376  val integerBlock = Module(new IntegerBlock(
377    fastWakeUpIn = Seq(),
378    slowWakeUpIn = fpExuConfigs.filter(_.writeIntRf) ++ loadExuConfigs,
379    fastWakeUpOut = intBlockFastWakeUp,
380    slowWakeUpOut = intBlockSlowWakeUp
381  ))
382  val floatBlock = Module(new FloatBlock(
383    intSlowWakeUpIn = intExuConfigs.filter(_.writeFpRf),
384    memSlowWakeUpIn = loadExuConfigs,
385    fastWakeUpOut = Seq(),
386    slowWakeUpOut = fpExuConfigs
387  ))
388
389  val frontend = outer.frontend.module
390  val memBlock = outer.memBlock.module
391  val l1pluscache = outer.l1pluscache.module
392  val ptw = outer.ptw.module
393
394  frontend.io.backend <> ctrlBlock.io.frontend
395  frontend.io.sfence <> integerBlock.io.fenceio.sfence
396  frontend.io.tlbCsr <> integerBlock.io.csrio.tlb
397  frontend.io.csrCtrl <> integerBlock.io.csrio.customCtrl
398
399  frontend.io.icacheMemAcq <> l1pluscache.io.req
400  l1pluscache.io.resp <> frontend.io.icacheMemGrant
401  l1pluscache.io.flush := frontend.io.l1plusFlush
402  frontend.io.fencei := integerBlock.io.fenceio.fencei
403
404  ctrlBlock.io.fromIntBlock <> integerBlock.io.toCtrlBlock
405  ctrlBlock.io.fromFpBlock <> floatBlock.io.toCtrlBlock
406  ctrlBlock.io.fromLsBlock <> memBlock.io.toCtrlBlock
407  ctrlBlock.io.toIntBlock <> integerBlock.io.fromCtrlBlock
408  ctrlBlock.io.toFpBlock <> floatBlock.io.fromCtrlBlock
409  ctrlBlock.io.toLsBlock <> memBlock.io.fromCtrlBlock
410  ctrlBlock.io.csrCtrl <> integerBlock.io.csrio.customCtrl
411
412  val memBlockWakeUpInt = memBlock.io.wakeUpOutInt.slow.map(WireInit(_))
413  val memBlockWakeUpFp = memBlock.io.wakeUpOutFp.slow.map(WireInit(_))
414  memBlock.io.wakeUpOutInt.slow.foreach(_.ready := true.B)
415  memBlock.io.wakeUpOutFp.slow.foreach(_.ready := true.B)
416
417  fpExuConfigs.zip(floatBlock.io.wakeUpOut.slow).filterNot(_._1.writeIntRf).map(_._2.ready := true.B)
418  val fpBlockWakeUpInt = fpExuConfigs
419    .zip(floatBlock.io.wakeUpOut.slow)
420    .filter(_._1.writeIntRf)
421    .map(_._2)
422
423  intExuConfigs.zip(integerBlock.io.wakeUpOut.slow).filterNot(_._1.writeFpRf).map(_._2.ready := true.B)
424  val intBlockWakeUpFp = intExuConfigs.filter(_.hasUncertainlatency)
425    .zip(integerBlock.io.wakeUpOut.slow)
426    .filter(_._1.writeFpRf)
427    .map(_._2)
428
429  integerBlock.io.wakeUpIn.slow <> fpBlockWakeUpInt ++ memBlockWakeUpInt
430  integerBlock.io.toMemBlock <> memBlock.io.fromIntBlock
431
432  floatBlock.io.intWakeUpFp <> intBlockWakeUpFp
433  floatBlock.io.memWakeUpFp <> memBlockWakeUpFp
434  floatBlock.io.toMemBlock <> memBlock.io.fromFpBlock
435
436  val wakeUpMem = Seq(
437    integerBlock.io.wakeUpOut,
438    floatBlock.io.wakeUpOut,
439  )
440  memBlock.io.wakeUpIn.fastUops <> wakeUpMem.flatMap(_.fastUops)
441  memBlock.io.wakeUpIn.fast <> wakeUpMem.flatMap(_.fast)
442  // Note: 'WireInit' is used to block 'ready's from memBlock,
443  // we don't need 'ready's from memBlock
444  memBlock.io.wakeUpIn.slow <> wakeUpMem.flatMap(_.slow.map(x => WireInit(x)))
445  memBlock.io.intWakeUpFp <> floatBlock.io.intWakeUpOut
446
447  integerBlock.io.csrio.hartId <> io.hartId
448  integerBlock.io.csrio.perf <> DontCare
449  integerBlock.io.csrio.perf.retiredInstr <> ctrlBlock.io.roqio.toCSR.perfinfo.retiredInstr
450  integerBlock.io.csrio.fpu.fflags <> ctrlBlock.io.roqio.toCSR.fflags
451  integerBlock.io.csrio.fpu.isIllegal := false.B
452  integerBlock.io.csrio.fpu.dirty_fs <> ctrlBlock.io.roqio.toCSR.dirty_fs
453  integerBlock.io.csrio.fpu.frm <> floatBlock.io.frm
454  integerBlock.io.csrio.exception <> ctrlBlock.io.roqio.exception
455  integerBlock.io.csrio.isXRet <> ctrlBlock.io.roqio.toCSR.isXRet
456  integerBlock.io.csrio.trapTarget <> ctrlBlock.io.roqio.toCSR.trapTarget
457  integerBlock.io.csrio.interrupt <> ctrlBlock.io.roqio.toCSR.intrBitSet
458  integerBlock.io.csrio.memExceptionVAddr <> memBlock.io.lsqio.exceptionAddr.vaddr
459  integerBlock.io.csrio.externalInterrupt <> io.externalInterrupt
460
461  integerBlock.io.fenceio.sfence <> memBlock.io.sfence
462  integerBlock.io.fenceio.sbuffer <> memBlock.io.fenceToSbuffer
463
464  memBlock.io.csrCtrl <> integerBlock.io.csrio.customCtrl
465  memBlock.io.tlbCsr <> integerBlock.io.csrio.tlb
466  memBlock.io.lsqio.roq <> ctrlBlock.io.roqio.lsq
467  memBlock.io.lsqio.exceptionAddr.lsIdx.lqIdx := ctrlBlock.io.roqio.exception.bits.uop.lqIdx
468  memBlock.io.lsqio.exceptionAddr.lsIdx.sqIdx := ctrlBlock.io.roqio.exception.bits.uop.sqIdx
469  memBlock.io.lsqio.exceptionAddr.isStore := CommitType.lsInstIsStore(ctrlBlock.io.roqio.exception.bits.uop.ctrl.commitType)
470
471  val itlbRepeater = Module(new PTWRepeater())
472  val dtlbRepeater = Module(new PTWRepeater())
473  itlbRepeater.io.tlb <> frontend.io.ptw
474  dtlbRepeater.io.tlb <> memBlock.io.ptw
475  itlbRepeater.io.sfence <> integerBlock.io.fenceio.sfence
476  dtlbRepeater.io.sfence <> integerBlock.io.fenceio.sfence
477  ptw.io.tlb(0) <> dtlbRepeater.io.ptw
478  ptw.io.tlb(1) <> itlbRepeater.io.ptw
479  ptw.io.sfence <> integerBlock.io.fenceio.sfence
480  ptw.io.csr <> integerBlock.io.csrio.tlb
481
482  // if l2 prefetcher use stream prefetch, it should be placed in XSCore
483  assert(l2PrefetcherParameters._type == "bop")
484  io.l2_pf_enable := integerBlock.io.csrio.customCtrl.l2_pf_enable
485
486  if (!env.FPGAPlatform) {
487    val id = hartIdCore()
488    difftestIO.fromSbuffer <> memBlock.difftestIO.fromSbuffer
489    difftestIO.fromSQ <> memBlock.difftestIO.fromSQ
490    difftestIO.fromCSR <> integerBlock.difftestIO.fromCSR
491    difftestIO.fromRoq <> ctrlBlock.difftestIO.fromRoq
492    difftestIO.fromAtomic <> memBlock.difftestIO.fromAtomic
493    difftestIO.fromPtw <> ptw.difftestIO
494    trapIO <> ctrlBlock.trapIO
495
496    val debugIntReg, debugFpReg = WireInit(VecInit(Seq.fill(32)(0.U(XLEN.W))))
497    ExcitingUtils.addSink(debugIntReg, s"DEBUG_INT_ARCH_REG$id", ExcitingUtils.Debug)
498    ExcitingUtils.addSink(debugFpReg, s"DEBUG_FP_ARCH_REG$id", ExcitingUtils.Debug)
499    val debugArchReg = WireInit(VecInit(debugIntReg ++ debugFpReg))
500    difftestIO.fromXSCore.r := debugArchReg
501  }
502
503}
504