xref: /XiangShan/src/main/scala/xiangshan/XSCore.scala (revision d8a66f7ecacc2b3538a1083b0716b7066c77ba3f) 
1package xiangshan
2
3import chisel3._
4import chisel3.util._
5import top.Parameters
6import xiangshan.backend._
7import xiangshan.backend.dispatch.DispatchParameters
8import xiangshan.backend.exu.ExuParameters
9import xiangshan.backend.exu.Exu._
10import xiangshan.frontend._
11import xiangshan.mem._
12import xiangshan.backend.fu.HasExceptionNO
13import xiangshan.cache.{DCache,InstrUncache, DCacheParameters, ICache, ICacheParameters, L1plusCache, L1plusCacheParameters, PTW, PTWRepeater, Uncache, MemoryOpConstants, MissReq}
14import xiangshan.cache.prefetch._
15import chipsalliance.rocketchip.config
16import freechips.rocketchip.diplomacy.{AddressSet, LazyModule, LazyModuleImp}
17import freechips.rocketchip.tilelink.{TLBuffer, TLBundleParameters, TLCacheCork, TLClientNode, TLFilter, TLIdentityNode, TLToAXI4, TLWidthWidget, TLXbar}
18import freechips.rocketchip.devices.tilelink.{DevNullParams, TLError}
19import sifive.blocks.inclusivecache.{CacheParameters, InclusiveCache, InclusiveCacheMicroParameters}
20import freechips.rocketchip.amba.axi4.{AXI4Deinterleaver, AXI4Fragmenter, AXI4IdIndexer, AXI4IdentityNode, AXI4ToTL, AXI4UserYanker}
21import freechips.rocketchip.tile.HasFPUParameters
22import sifive.blocks.inclusivecache.PrefetcherIO
23import utils._
24
25object hartIdCore extends (() => Int) {
26  var x = 0
27  def apply(): Int = {
28    x = x + 1
29    x-1
30  }
31}
32
33case class XSCoreParameters
34(
35  XLEN: Int = 64,
36  HasMExtension: Boolean = true,
37  HasCExtension: Boolean = true,
38  HasDiv: Boolean = true,
39  HasICache: Boolean = true,
40  HasDCache: Boolean = true,
41  EnableStoreQueue: Boolean = true,
42  AddrBits: Int = 64,
43  VAddrBits: Int = 39,
44  PAddrBits: Int = 40,
45  HasFPU: Boolean = true,
46  FectchWidth: Int = 8,
47  EnableBPU: Boolean = true,
48  EnableBPD: Boolean = true,
49  EnableRAS: Boolean = true,
50  EnableLB: Boolean = false,
51  EnableLoop: Boolean = false,
52  EnableSC: Boolean = false,
53  EnbaleTlbDebug: Boolean = false,
54  EnableJal: Boolean = false,
55  EnableUBTB: Boolean = true,
56  HistoryLength: Int = 64,
57  BtbSize: Int = 2048,
58  JbtacSize: Int = 1024,
59  JbtacBanks: Int = 8,
60  RasSize: Int = 16,
61  CacheLineSize: Int = 512,
62  UBtbWays: Int = 16,
63  BtbWays: Int = 2,
64
65  EnableL1plusPrefetcher: Boolean = true,
66  IBufSize: Int = 32,
67  DecodeWidth: Int = 6,
68  RenameWidth: Int = 6,
69  CommitWidth: Int = 6,
70  BrqSize: Int = 32,
71  FtqSize: Int = 48,
72  IssQueSize: Int = 12,
73  NRPhyRegs: Int = 160,
74  NRIntReadPorts: Int = 14,
75  NRIntWritePorts: Int = 8,
76  NRFpReadPorts: Int = 14,
77  NRFpWritePorts: Int = 8,
78  LoadQueueSize: Int = 64,
79  StoreQueueSize: Int = 48,
80  RoqSize: Int = 192,
81  dpParams: DispatchParameters = DispatchParameters(
82    IntDqSize = 16,
83    FpDqSize = 16,
84    LsDqSize = 16,
85    IntDqDeqWidth = 4,
86    FpDqDeqWidth = 4,
87    LsDqDeqWidth = 4
88  ),
89  exuParameters: ExuParameters = ExuParameters(
90    JmpCnt = 1,
91    AluCnt = 4,
92    MulCnt = 0,
93    MduCnt = 2,
94    FmacCnt = 4,
95    FmiscCnt = 2,
96    FmiscDivSqrtCnt = 0,
97    LduCnt = 2,
98    StuCnt = 2
99  ),
100  LoadPipelineWidth: Int = 2,
101  StorePipelineWidth: Int = 2,
102  StoreBufferSize: Int = 16,
103  RefillSize: Int = 512,
104  TlbEntrySize: Int = 32,
105  TlbSPEntrySize: Int = 4,
106  PtwL3EntrySize: Int = 4096, //(256 * 16) or 512
107  PtwSPEntrySize: Int = 16,
108  PtwL1EntrySize: Int = 16,
109  PtwL2EntrySize: Int = 2048,//(256 * 8)
110  NumPerfCounters: Int = 16,
111  NrExtIntr: Int = 150
112)
113
114trait HasXSParameter {
115
116  val core = Parameters.get.coreParameters
117  val env = Parameters.get.envParameters
118
119  val XLEN = 64
120  val minFLen = 32
121  val fLen = 64
122  def xLen = 64
123  val HasMExtension = core.HasMExtension
124  val HasCExtension = core.HasCExtension
125  val HasDiv = core.HasDiv
126  val HasIcache = core.HasICache
127  val HasDcache = core.HasDCache
128  val EnableStoreQueue = core.EnableStoreQueue
129  val AddrBits = core.AddrBits // AddrBits is used in some cases
130  val VAddrBits = core.VAddrBits // VAddrBits is Virtual Memory addr bits
131  val PAddrBits = core.PAddrBits // PAddrBits is Phyical Memory addr bits
132  val AddrBytes = AddrBits / 8 // unused
133  val DataBits = XLEN
134  val DataBytes = DataBits / 8
135  val HasFPU = core.HasFPU
136  val FetchWidth = core.FectchWidth
137  val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1)
138  val EnableBPU = core.EnableBPU
139  val EnableBPD = core.EnableBPD // enable backing predictor(like Tage) in BPUStage3
140  val EnableRAS = core.EnableRAS
141  val EnableLB = core.EnableLB
142  val EnableLoop = core.EnableLoop
143  val EnableSC = core.EnableSC
144  val EnbaleTlbDebug = core.EnbaleTlbDebug
145  val HistoryLength = core.HistoryLength
146  val BtbSize = core.BtbSize
147  // val BtbWays = 4
148  val BtbBanks = PredictWidth
149  // val BtbSets = BtbSize / BtbWays
150  val JbtacSize = core.JbtacSize
151  val JbtacBanks = core.JbtacBanks
152  val RasSize = core.RasSize
153  val CacheLineSize = core.CacheLineSize
154  val CacheLineHalfWord = CacheLineSize / 16
155  val ExtHistoryLength = HistoryLength + 64
156  val UBtbWays = core.UBtbWays
157  val BtbWays = core.BtbWays
158  val EnableL1plusPrefetcher = core.EnableL1plusPrefetcher
159  val IBufSize = core.IBufSize
160  val DecodeWidth = core.DecodeWidth
161  val RenameWidth = core.RenameWidth
162  val CommitWidth = core.CommitWidth
163  val BrqSize = core.BrqSize
164  val FtqSize = core.FtqSize
165  val IssQueSize = core.IssQueSize
166  val BrTagWidth = log2Up(BrqSize)
167  val NRPhyRegs = core.NRPhyRegs
168  val PhyRegIdxWidth = log2Up(NRPhyRegs)
169  val RoqSize = core.RoqSize
170  val LoadQueueSize = core.LoadQueueSize
171  val StoreQueueSize = core.StoreQueueSize
172  val dpParams = core.dpParams
173  val exuParameters = core.exuParameters
174  val NRIntReadPorts = core.NRIntReadPorts
175  val NRIntWritePorts = core.NRIntWritePorts
176  val NRMemReadPorts = exuParameters.LduCnt + 2*exuParameters.StuCnt
177  val NRFpReadPorts = core.NRFpReadPorts
178  val NRFpWritePorts = core.NRFpWritePorts
179  val LoadPipelineWidth = core.LoadPipelineWidth
180  val StorePipelineWidth = core.StorePipelineWidth
181  val StoreBufferSize = core.StoreBufferSize
182  val RefillSize = core.RefillSize
183  val DTLBWidth = core.LoadPipelineWidth + core.StorePipelineWidth
184  val TlbEntrySize = core.TlbEntrySize
185  val TlbSPEntrySize = core.TlbSPEntrySize
186  val PtwL3EntrySize = core.PtwL3EntrySize
187  val PtwSPEntrySize = core.PtwSPEntrySize
188  val PtwL1EntrySize = core.PtwL1EntrySize
189  val PtwL2EntrySize = core.PtwL2EntrySize
190  val NumPerfCounters = core.NumPerfCounters
191  val NrExtIntr = core.NrExtIntr
192
193  val instBytes = if (HasCExtension) 2 else 4
194  val instOffsetBits = log2Ceil(instBytes)
195
196  val icacheParameters = ICacheParameters(
197    tagECC = Some("parity"),
198    dataECC = Some("parity"),
199    replacer = Some("setlru"),
200    nMissEntries = 2
201  )
202
203  val l1plusCacheParameters = L1plusCacheParameters(
204    tagECC = Some("secded"),
205    dataECC = Some("secded"),
206    nMissEntries = 8
207  )
208
209  val dcacheParameters = DCacheParameters(
210    tagECC = Some("secded"),
211    dataECC = Some("secded"),
212    nMissEntries = 16,
213    nProbeEntries = 16,
214    nReleaseEntries = 16,
215    nStoreReplayEntries = 16
216  )
217
218  val LRSCCycles = 100
219
220
221  // cache hierarchy configurations
222  val l1BusDataWidth = 256
223
224  // L2 configurations
225  val L1BusWidth = 256
226  val L2Size = 512 * 1024 // 512KB
227  val L2BlockSize = 64
228  val L2NWays = 8
229  val L2NSets = L2Size / L2BlockSize / L2NWays
230
231  // L3 configurations
232  val L2BusWidth = 256
233  val L3Size = 4 * 1024 * 1024 // 4MB
234  val L3BlockSize = 64
235  val L3NBanks = 4
236  val L3NWays = 8
237  val L3NSets = L3Size / L3BlockSize / L3NBanks / L3NWays
238
239  // on chip network configurations
240  val L3BusWidth = 256
241
242  // icache prefetcher
243  val l1plusPrefetcherParameters = L1plusPrefetcherParameters(
244    enable = true,
245    _type = "stream",
246    streamParams = StreamPrefetchParameters(
247      streamCnt = 2,
248      streamSize = 4,
249      ageWidth = 4,
250      blockBytes = l1plusCacheParameters.blockBytes,
251      reallocStreamOnMissInstantly = true,
252      cacheName = "icache"
253    )
254  )
255
256  // dcache prefetcher
257  val l2PrefetcherParameters = L2PrefetcherParameters(
258    enable = true,
259    _type = "bop",// "stream" or "bop"
260    streamParams = StreamPrefetchParameters(
261      streamCnt = 4,
262      streamSize = 4,
263      ageWidth = 4,
264      blockBytes = L2BlockSize,
265      reallocStreamOnMissInstantly = true,
266      cacheName = "dcache"
267    ),
268    bopParams = BOPParameters(
269      rrTableEntries = 256,
270      rrTagBits = 12,
271      scoreBits = 5,
272      roundMax = 50,
273      badScore = 1,
274      blockBytes = L2BlockSize,
275      nEntries = dcacheParameters.nMissEntries * 2 // TODO: this is too large
276    ),
277  )
278}
279
280trait HasXSLog { this: RawModule =>
281  implicit val moduleName: String = this.name
282}
283
284abstract class XSModule extends MultiIOModule
285  with HasXSParameter
286  with HasExceptionNO
287  with HasXSLog
288  with HasFPUParameters
289{
290  def io: Record
291}
292
293//remove this trait after impl module logic
294trait NeedImpl { this: RawModule =>
295  override protected def IO[T <: Data](iodef: T): T = {
296    println(s"[Warn]: (${this.name}) please reomve 'NeedImpl' after implement this module")
297    val io = chisel3.experimental.IO(iodef)
298    io <> DontCare
299    io
300  }
301}
302
303abstract class XSBundle extends Bundle
304  with HasXSParameter
305
306case class EnviromentParameters
307(
308  FPGAPlatform: Boolean = true,
309  EnableDebug: Boolean = false,
310  EnablePerfDebug: Boolean = false,
311  DualCoreDifftest: Boolean = false
312)
313
314// object AddressSpace extends HasXSParameter {
315//   // (start, size)
316//   // address out of MMIO will be considered as DRAM
317//   def mmio = List(
318//     (0x00000000L, 0x40000000L),  // internal devices, such as CLINT and PLIC
319//     (0x40000000L, 0x40000000L)   // external devices
320//   )
321
322//   def isMMIO(addr: UInt): Bool = mmio.map(range => {
323//     require(isPow2(range._2))
324//     val bits = log2Up(range._2)
325//     (addr ^ range._1.U)(PAddrBits-1, bits) === 0.U
326//   }).reduce(_ || _)
327// }
328
329
330
331class XSCore()(implicit p: config.Parameters) extends LazyModule
332  with HasXSParameter
333  with HasExeBlockHelper
334{
335
336  // to fast wake up fp, mem rs
337  val intBlockFastWakeUpFp = intExuConfigs.filter(fpFastFilter)
338  val intBlockSlowWakeUpFp = intExuConfigs.filter(fpSlowFilter)
339  val intBlockFastWakeUpInt = intExuConfigs.filter(intFastFilter)
340  val intBlockSlowWakeUpInt = intExuConfigs.filter(intSlowFilter)
341
342  val fpBlockFastWakeUpFp = fpExuConfigs.filter(fpFastFilter)
343  val fpBlockSlowWakeUpFp = fpExuConfigs.filter(fpSlowFilter)
344  val fpBlockFastWakeUpInt = fpExuConfigs.filter(intFastFilter)
345  val fpBlockSlowWakeUpInt = fpExuConfigs.filter(intSlowFilter)
346
347  // outer facing nodes
348  val frontend = LazyModule(new Frontend())
349  val l1pluscache = LazyModule(new L1plusCache())
350  val ptw = LazyModule(new PTW())
351  val l2Prefetcher = LazyModule(new L2Prefetcher())
352  val memBlock = LazyModule(new MemBlock(
353    fastWakeUpIn = intBlockFastWakeUpInt ++ intBlockFastWakeUpFp ++ fpBlockFastWakeUpInt ++ fpBlockFastWakeUpFp,
354    slowWakeUpIn = intBlockSlowWakeUpInt ++ intBlockSlowWakeUpFp ++ fpBlockSlowWakeUpInt ++ fpBlockSlowWakeUpFp,
355    fastFpOut = Seq(),
356    slowFpOut = loadExuConfigs,
357    fastIntOut = Seq(),
358    slowIntOut = loadExuConfigs
359  ))
360
361  lazy val module = new XSCoreImp(this)
362}
363
364class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer)
365  with HasXSParameter
366  with HasExeBlockHelper
367{
368  val io = IO(new Bundle {
369    val externalInterrupt = new ExternalInterruptIO
370    val l2ToPrefetcher = Flipped(new PrefetcherIO(PAddrBits))
371  })
372
373  val difftestIO = IO(new DifftestBundle())
374  difftestIO <> DontCare
375
376  val trapIO = IO(new TrapIO())
377  trapIO <> DontCare
378
379  println(s"FPGAPlatform:${env.FPGAPlatform} EnableDebug:${env.EnableDebug}")
380  AddressSpace.printMemmap()
381
382  // to fast wake up fp, mem rs
383  val intBlockFastWakeUpFp = intExuConfigs.filter(fpFastFilter)
384  val intBlockSlowWakeUpFp = intExuConfigs.filter(fpSlowFilter)
385  val intBlockFastWakeUpInt = intExuConfigs.filter(intFastFilter)
386  val intBlockSlowWakeUpInt = intExuConfigs.filter(intSlowFilter)
387
388  val fpBlockFastWakeUpFp = fpExuConfigs.filter(fpFastFilter)
389  val fpBlockSlowWakeUpFp = fpExuConfigs.filter(fpSlowFilter)
390  val fpBlockFastWakeUpInt = fpExuConfigs.filter(intFastFilter)
391  val fpBlockSlowWakeUpInt = fpExuConfigs.filter(intSlowFilter)
392
393  val ctrlBlock = Module(new CtrlBlock)
394  val integerBlock = Module(new IntegerBlock(
395    fastWakeUpIn = fpBlockFastWakeUpInt,
396    slowWakeUpIn = fpBlockSlowWakeUpInt ++ loadExuConfigs,
397    fastFpOut = intBlockFastWakeUpFp,
398    slowFpOut = intBlockSlowWakeUpFp,
399    fastIntOut = intBlockFastWakeUpInt,
400    slowIntOut = intBlockSlowWakeUpInt
401  ))
402  val floatBlock = Module(new FloatBlock(
403    fastWakeUpIn = intBlockFastWakeUpFp,
404    slowWakeUpIn = intBlockSlowWakeUpFp ++ loadExuConfigs,
405    fastFpOut = fpBlockFastWakeUpFp,
406    slowFpOut = fpBlockSlowWakeUpFp,
407    fastIntOut = fpBlockFastWakeUpInt,
408    slowIntOut = fpBlockSlowWakeUpInt
409  ))
410
411  val frontend = outer.frontend.module
412  val memBlock = outer.memBlock.module
413  val l1pluscache = outer.l1pluscache.module
414  val ptw = outer.ptw.module
415  val l2Prefetcher = outer.l2Prefetcher.module
416
417  frontend.io.backend <> ctrlBlock.io.frontend
418  frontend.io.sfence <> integerBlock.io.fenceio.sfence
419  frontend.io.tlbCsr <> integerBlock.io.csrio.tlb
420
421  frontend.io.icacheMemAcq <> l1pluscache.io.req
422  l1pluscache.io.resp <> frontend.io.icacheMemGrant
423  l1pluscache.io.flush := frontend.io.l1plusFlush
424  frontend.io.fencei := integerBlock.io.fenceio.fencei
425
426  ctrlBlock.io.fromIntBlock <> integerBlock.io.toCtrlBlock
427  ctrlBlock.io.fromFpBlock <> floatBlock.io.toCtrlBlock
428  ctrlBlock.io.fromLsBlock <> memBlock.io.toCtrlBlock
429  ctrlBlock.io.toIntBlock <> integerBlock.io.fromCtrlBlock
430  ctrlBlock.io.toFpBlock <> floatBlock.io.fromCtrlBlock
431  ctrlBlock.io.toLsBlock <> memBlock.io.fromCtrlBlock
432
433  integerBlock.io.wakeUpIn.fastUops <> floatBlock.io.wakeUpIntOut.fastUops
434  integerBlock.io.wakeUpIn.fast <> floatBlock.io.wakeUpIntOut.fast
435  integerBlock.io.wakeUpIn.slow <> floatBlock.io.wakeUpIntOut.slow ++ memBlock.io.wakeUpIntOut.slow
436  integerBlock.io.toMemBlock <> memBlock.io.fromIntBlock
437
438  floatBlock.io.wakeUpIn.fastUops <> integerBlock.io.wakeUpFpOut.fastUops
439  floatBlock.io.wakeUpIn.fast <> integerBlock.io.wakeUpFpOut.fast
440  floatBlock.io.wakeUpIn.slow <> integerBlock.io.wakeUpFpOut.slow ++ memBlock.io.wakeUpFpOut.slow
441  floatBlock.io.toMemBlock <> memBlock.io.fromFpBlock
442
443
444  integerBlock.io.wakeUpIntOut.fast.map(_.ready := true.B)
445  integerBlock.io.wakeUpIntOut.slow.map(_.ready := true.B)
446  floatBlock.io.wakeUpFpOut.fast.map(_.ready := true.B)
447  floatBlock.io.wakeUpFpOut.slow.map(_.ready := true.B)
448
449  val wakeUpMem = Seq(
450    integerBlock.io.wakeUpIntOut,
451    integerBlock.io.wakeUpFpOut,
452    floatBlock.io.wakeUpIntOut,
453    floatBlock.io.wakeUpFpOut
454  )
455  memBlock.io.wakeUpIn.fastUops <> wakeUpMem.flatMap(_.fastUops)
456  memBlock.io.wakeUpIn.fast <> wakeUpMem.flatMap(w => w.fast.map(f => {
457	val raw = WireInit(f)
458	raw
459  }))
460  memBlock.io.wakeUpIn.slow <> wakeUpMem.flatMap(w => w.slow.map(s => {
461	val raw = WireInit(s)
462	raw
463  }))
464
465  integerBlock.io.csrio.fflags <> ctrlBlock.io.roqio.toCSR.fflags
466  integerBlock.io.csrio.dirty_fs <> ctrlBlock.io.roqio.toCSR.dirty_fs
467  integerBlock.io.csrio.exception <> ctrlBlock.io.roqio.exception
468  integerBlock.io.csrio.trapTarget <> ctrlBlock.io.roqio.toCSR.trapTarget
469  integerBlock.io.csrio.isXRet <> ctrlBlock.io.roqio.toCSR.isXRet
470  integerBlock.io.csrio.interrupt <> ctrlBlock.io.roqio.toCSR.intrBitSet
471  integerBlock.io.csrio.memExceptionVAddr <> memBlock.io.lsqio.exceptionAddr.vaddr
472  integerBlock.io.csrio.externalInterrupt <> io.externalInterrupt
473  integerBlock.io.csrio.perfinfo <> ctrlBlock.io.roqio.toCSR.perfinfo
474  integerBlock.io.fenceio.sfence <> memBlock.io.sfence
475  integerBlock.io.fenceio.sbuffer <> memBlock.io.fenceToSbuffer
476  memBlock.io.tlbCsr <> integerBlock.io.csrio.tlb
477
478  floatBlock.io.frm <> integerBlock.io.csrio.frm
479
480  memBlock.io.lsqio.roq <> ctrlBlock.io.roqio.lsq
481  memBlock.io.lsqio.exceptionAddr.lsIdx.lqIdx := ctrlBlock.io.roqio.exception.bits.uop.lqIdx
482  memBlock.io.lsqio.exceptionAddr.lsIdx.sqIdx := ctrlBlock.io.roqio.exception.bits.uop.sqIdx
483  memBlock.io.lsqio.exceptionAddr.isStore := CommitType.lsInstIsStore(ctrlBlock.io.roqio.exception.bits.uop.ctrl.commitType)
484
485  val itlbRepester = Module(new PTWRepeater())
486  val dtlbRepester = Module(new PTWRepeater())
487  itlbRepester.io.tlb <> frontend.io.ptw
488  dtlbRepester.io.tlb <> memBlock.io.ptw
489  itlbRepester.io.sfence <> integerBlock.io.fenceio.sfence
490  dtlbRepester.io.sfence <> integerBlock.io.fenceio.sfence
491  ptw.io.tlb(0) <> dtlbRepester.io.ptw
492  ptw.io.tlb(1) <> itlbRepester.io.ptw
493  ptw.io.sfence <> integerBlock.io.fenceio.sfence
494  ptw.io.csr    <> integerBlock.io.csrio.tlb
495
496  val l2PrefetcherIn = Wire(Decoupled(new MissReq))
497  if (l2PrefetcherParameters.enable && l2PrefetcherParameters._type == "bop") {
498    l2PrefetcherIn.valid := io.l2ToPrefetcher.acquire.valid
499    l2PrefetcherIn.bits := DontCare
500    l2PrefetcherIn.bits.addr := io.l2ToPrefetcher.acquire.bits.address
501    l2PrefetcherIn.bits.cmd := Mux(io.l2ToPrefetcher.acquire.bits.write, MemoryOpConstants.M_XWR, MemoryOpConstants.M_XRD)
502  } else {
503    l2PrefetcherIn <> memBlock.io.toDCachePrefetch
504  }
505  l2Prefetcher.io.in <> l2PrefetcherIn
506
507  if (!env.FPGAPlatform) {
508    val debugIntReg, debugFpReg = WireInit(VecInit(Seq.fill(32)(0.U(XLEN.W))))
509    ExcitingUtils.addSink(debugIntReg, "DEBUG_INT_ARCH_REG", ExcitingUtils.Debug)
510    ExcitingUtils.addSink(debugFpReg, "DEBUG_FP_ARCH_REG", ExcitingUtils.Debug)
511    val debugArchReg = WireInit(VecInit(debugIntReg ++ debugFpReg))
512    ExcitingUtils.addSource(debugArchReg, "difftestRegs", ExcitingUtils.Debug)
513  }
514
515  if (env.DualCoreDifftest) {
516    val id = hartIdCore()
517    difftestIO.fromSbuffer <> memBlock.difftestIO.fromSbuffer
518    difftestIO.fromSQ <> memBlock.difftestIO.fromSQ
519    difftestIO.fromCSR <> integerBlock.difftestIO.fromCSR
520    difftestIO.fromRoq <> ctrlBlock.difftestIO.fromRoq
521    trapIO <> ctrlBlock.trapIO
522
523    val debugIntReg, debugFpReg = WireInit(VecInit(Seq.fill(32)(0.U(XLEN.W))))
524    ExcitingUtils.addSink(debugIntReg, s"DEBUG_INT_ARCH_REG$id", ExcitingUtils.Debug)
525    ExcitingUtils.addSink(debugFpReg, s"DEBUG_FP_ARCH_REG$id", ExcitingUtils.Debug)
526    val debugArchReg = WireInit(VecInit(debugIntReg ++ debugFpReg))
527    difftestIO.fromXSCore.r := debugArchReg
528  }
529
530}
531