1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config 20import chipsalliance.rocketchip.config.Parameters 21import chisel3._ 22import chisel3.util._ 23import freechips.rocketchip.diplomacy.{BundleBridgeSource, LazyModule, LazyModuleImp} 24import freechips.rocketchip.interrupts.{IntSinkNode, IntSinkPortSimple} 25import freechips.rocketchip.tile.HasFPUParameters 26import freechips.rocketchip.tilelink.TLBuffer 27import system.HasSoCParameter 28import utils._ 29import xiangshan.backend._ 30import xiangshan.backend.exu.{ExuConfig, Wb2Ctrl, WbArbiterWrapper} 31import xiangshan.cache.mmu._ 32import xiangshan.frontend._ 33 34import scala.collection.mutable.ListBuffer 35 36abstract class XSModule(implicit val p: Parameters) extends MultiIOModule 37 with HasXSParameter 38 with HasFPUParameters { 39 def io: Record 40} 41 42//remove this trait after impl module logic 43trait NeedImpl { 44 this: RawModule => 45 override protected def IO[T <: Data](iodef: T): T = { 46 println(s"[Warn]: (${this.name}) please reomve 'NeedImpl' after implement this module") 47 val io = chisel3.experimental.IO(iodef) 48 io <> DontCare 49 io 50 } 51} 52 53class WritebackSourceParams( 54 var exuConfigs: Seq[Seq[ExuConfig]] = Seq() 55 ) { 56 def length: Int = exuConfigs.length 57 def ++(that: WritebackSourceParams): WritebackSourceParams = { 58 new WritebackSourceParams(exuConfigs ++ that.exuConfigs) 59 } 60} 61 62trait HasWritebackSource { 63 val writebackSourceParams: Seq[WritebackSourceParams] 64 final def writebackSource(sourceMod: HasWritebackSourceImp): Seq[Seq[Valid[ExuOutput]]] = { 65 require(sourceMod.writebackSource.isDefined, "should not use Valid[ExuOutput]") 66 val source = sourceMod.writebackSource.get 67 require(source.length == writebackSourceParams.length, "length mismatch between sources") 68 for ((s, p) <- source.zip(writebackSourceParams)) { 69 require(s.length == p.length, "params do not match with the exuOutput") 70 } 71 source 72 } 73 final def writebackSource1(sourceMod: HasWritebackSourceImp): Seq[Seq[DecoupledIO[ExuOutput]]] = { 74 require(sourceMod.writebackSource1.isDefined, "should not use DecoupledIO[ExuOutput]") 75 val source = sourceMod.writebackSource1.get 76 require(source.length == writebackSourceParams.length, "length mismatch between sources") 77 for ((s, p) <- source.zip(writebackSourceParams)) { 78 require(s.length == p.length, "params do not match with the exuOutput") 79 } 80 source 81 } 82 val writebackSourceImp: HasWritebackSourceImp 83} 84 85trait HasWritebackSourceImp { 86 def writebackSource: Option[Seq[Seq[Valid[ExuOutput]]]] = None 87 def writebackSource1: Option[Seq[Seq[DecoupledIO[ExuOutput]]]] = None 88} 89 90trait HasWritebackSink { 91 // Caches all sources. The selected source will be the one with smallest length. 92 var writebackSinks = ListBuffer.empty[(Seq[HasWritebackSource], Seq[Int])] 93 def addWritebackSink(source: Seq[HasWritebackSource], index: Option[Seq[Int]] = None): HasWritebackSink = { 94 val realIndex = if (index.isDefined) index.get else Seq.fill(source.length)(0) 95 writebackSinks += ((source, realIndex)) 96 this 97 } 98 99 def writebackSinksParams: Seq[WritebackSourceParams] = { 100 writebackSinks.map{ case (s, i) => s.zip(i).map(x => x._1.writebackSourceParams(x._2)).reduce(_ ++ _) } 101 } 102 final def writebackSinksMod( 103 thisMod: Option[HasWritebackSource] = None, 104 thisModImp: Option[HasWritebackSourceImp] = None 105 ): Seq[Seq[HasWritebackSourceImp]] = { 106 require(thisMod.isDefined == thisModImp.isDefined) 107 writebackSinks.map(_._1.map(source => 108 if (thisMod.isDefined && source == thisMod.get) thisModImp.get else source.writebackSourceImp) 109 ) 110 } 111 final def writebackSinksImp( 112 thisMod: Option[HasWritebackSource] = None, 113 thisModImp: Option[HasWritebackSourceImp] = None 114 ): Seq[Seq[ValidIO[ExuOutput]]] = { 115 val sourceMod = writebackSinksMod(thisMod, thisModImp) 116 writebackSinks.zip(sourceMod).map{ case ((s, i), m) => 117 s.zip(i).zip(m).flatMap(x => x._1._1.writebackSource(x._2)(x._1._2)) 118 } 119 } 120 def selWritebackSinks(func: WritebackSourceParams => Int): Int = { 121 writebackSinksParams.zipWithIndex.minBy(params => func(params._1))._2 122 } 123 def generateWritebackIO( 124 thisMod: Option[HasWritebackSource] = None, 125 thisModImp: Option[HasWritebackSourceImp] = None 126 ): Unit 127} 128 129abstract class XSBundle(implicit val p: Parameters) extends Bundle 130 with HasXSParameter 131 132abstract class XSCoreBase()(implicit p: config.Parameters) extends LazyModule 133 with HasXSParameter with HasExuWbHelper 134{ 135 // interrupt sinks 136 val clint_int_sink = IntSinkNode(IntSinkPortSimple(1, 2)) 137 val debug_int_sink = IntSinkNode(IntSinkPortSimple(1, 1)) 138 val plic_int_sink = IntSinkNode(IntSinkPortSimple(2, 1)) 139 // outer facing nodes 140 val frontend = LazyModule(new Frontend()) 141 val ptw = LazyModule(new L2TLBWrapper()) 142 val ptw_to_l2_buffer = LazyModule(new TLBuffer) 143 val csrOut = BundleBridgeSource(Some(() => new DistributedCSRIO())) 144 145 ptw_to_l2_buffer.node := ptw.node 146 147 val wbArbiter = LazyModule(new WbArbiterWrapper(exuConfigs, NRIntWritePorts, NRFpWritePorts)) 148 val intWbPorts: Seq[Seq[ExuConfig]] = wbArbiter.intWbPorts 149 val fpWbPorts: Seq[Seq[ExuConfig]] = wbArbiter.fpWbPorts 150 151 // TODO: better RS organization 152 // generate rs according to number of function units 153 require(exuParameters.JmpCnt == 1) 154 require(exuParameters.MduCnt <= exuParameters.AluCnt && exuParameters.MduCnt > 0) 155 require(exuParameters.FmiscCnt <= exuParameters.FmacCnt && exuParameters.FmiscCnt > 0) 156 require(exuParameters.LduCnt == exuParameters.StuCnt) // TODO: remove this limitation 157 158 // one RS every 2 MDUs 159 val aluScheLaneCfg = ScheLaneConfig( 160 aluRSMod, 161 AluExeUnitCfg, 162 exuParameters.AluCnt, 163 Seq(AluExeUnitCfg, LdExeUnitCfg, StaExeUnitCfg)) 164 val mulScheLaneCfg = ScheLaneConfig( 165 mulRSMod, 166 MulDivExeUnitCfg, 167 exuParameters.MduCnt, 168 Seq(AluExeUnitCfg, MulDivExeUnitCfg)) 169 val jumpScheLaneCfg = ScheLaneConfig( 170 jumpRSMod, 171 JumpCSRExeUnitCfg, 172 1) 173 val loadScheLaneCfg = ScheLaneConfig( 174 loadRSMod, 175 LdExeUnitCfg, 176 exuParameters.LduCnt, 177 Seq(AluExeUnitCfg, LdExeUnitCfg)) 178 val staScheLaneCfg = ScheLaneConfig( 179 staRSMod, 180 StaExeUnitCfg, 181 exuParameters.StuCnt) 182 val stdScheLaneCfg = ScheLaneConfig( 183 stdRSMod, 184 StdExeUnitCfg, 185 exuParameters.StuCnt) 186 val fmaScheLaneCfg = ScheLaneConfig( 187 fmaRSMod, 188 FmacExeUnitCfg, 189 exuParameters.FmacCnt, 190 Seq(), 191 Seq(FmacExeUnitCfg, FmiscExeUnitCfg)) 192 val fmiscScheLaneCfg = ScheLaneConfig( 193 fmiscRSMod, 194 FmiscExeUnitCfg, 195 exuParameters.FmiscCnt) 196 197 val scheduleCfgs = Seq( 198 Seq( 199 aluScheLaneCfg, 200 mulScheLaneCfg, 201 jumpScheLaneCfg, 202 loadScheLaneCfg, 203 staScheLaneCfg, 204 stdScheLaneCfg 205 ), 206 Seq( 207 fmaScheLaneCfg, 208 fmiscScheLaneCfg 209 ) 210 ) 211 // should do outer fast wakeup ports here 212 val otherFastPorts: Seq[Seq[Seq[Int]]] = scheduleCfgs.zipWithIndex.map { case (sche, i) => 213 val otherCfg = scheduleCfgs.zipWithIndex.filter(_._2 != i).map(_._1).reduce(_ ++ _) 214 val outerPorts = sche.map(cfg => { 215 // exe units from this scheduler need fastUops from exeunits 216 val outerWakeupInSche = sche.filter(_.exuConfig.wakeupFromExu) 217 val intraIntScheOuter = outerWakeupInSche.filter(_.intFastWakeupTarget.contains(cfg.exuConfig)).map(_.exuConfig) 218 val intraFpScheOuter = outerWakeupInSche.filter(_.fpFastWakeupTarget.contains(cfg.exuConfig)).map(_.exuConfig) 219 // exe units from other schedulers need fastUop from outside 220 val otherIntSource = otherCfg.filter(_.intFastWakeupTarget.contains(cfg.exuConfig)).map(_.exuConfig) 221 val otherFpSource = otherCfg.filter(_.fpFastWakeupTarget.contains(cfg.exuConfig)).map(_.exuConfig) 222 val intSource = findInWbPorts(intWbPorts, intraIntScheOuter ++ otherIntSource) 223 val fpSource = findInWbPorts(fpWbPorts, intraFpScheOuter ++ otherFpSource) 224 getFastWakeupIndex(cfg.exuConfig, intSource, fpSource, intWbPorts.length).sorted 225 }) 226 println(s"inter-scheduler wakeup sources for $i: $outerPorts") 227 outerPorts 228 } 229 230 // allow mdu and fmisc to have 2*numDeq enqueue ports 231 val intDpPorts = (0 until exuParameters.AluCnt).map(i => { 232 if (i < exuParameters.JmpCnt) Seq( 233 DpPortMapConfig(0, i), 234 DpPortMapConfig(1, i), 235 DpPortMapConfig(2, i)) 236 else if (i < 2 * exuParameters.MduCnt) Seq( 237 DpPortMapConfig(0, i), 238 DpPortMapConfig(1, i)) 239 else Seq(DpPortMapConfig(0, i)) 240 }) 241 val lsDpPorts = (0 until exuParameters.LduCnt).map(i => Seq(DpPortMapConfig(3, i))) ++ 242 (0 until exuParameters.StuCnt).map(i => Seq(DpPortMapConfig(4, i))) ++ 243 (0 until exuParameters.StuCnt).map(i => Seq(DpPortMapConfig(5, i))) 244 val fpDpPorts = (0 until exuParameters.FmacCnt).map(i => { 245 if (i < 2 * exuParameters.FmiscCnt) Seq(DpPortMapConfig(0, i), DpPortMapConfig(1, i)) 246 else Seq(DpPortMapConfig(0, i)) 247 }) 248 249 val dispatchPorts = Seq(intDpPorts ++ lsDpPorts, fpDpPorts) 250 251 val outIntRfReadPorts = Seq(0, 0) 252 val outFpRfReadPorts = Seq(0, StorePipelineWidth) 253 val hasIntRf = Seq(true, false) 254 val hasFpRf = Seq(false, true) 255 val exuBlocks = scheduleCfgs.zip(dispatchPorts).zip(otherFastPorts).zipWithIndex.map { 256 case (((sche, disp), other), i) => 257 LazyModule(new ExuBlock(sche, disp, intWbPorts, fpWbPorts, other, outIntRfReadPorts(i), outFpRfReadPorts(i), hasIntRf(i), hasFpRf(i))) 258 } 259 260 val memBlock = LazyModule(new MemBlock()(p.alter((site, here, up) => { 261 case XSCoreParamsKey => up(XSCoreParamsKey).copy( 262 IssQueSize = exuBlocks.head.scheduler.getMemRsEntries 263 ) 264 }))) 265 266 val wb2Ctrl = LazyModule(new Wb2Ctrl(exuConfigs)) 267 wb2Ctrl.addWritebackSink(exuBlocks :+ memBlock) 268 val dpExuConfigs = exuBlocks.flatMap(_.scheduler.dispatch2.map(_.configs)) 269 val ctrlBlock = LazyModule(new CtrlBlock(dpExuConfigs)) 270 val writebackSources = Seq(Seq(wb2Ctrl), Seq(wbArbiter)) 271 writebackSources.foreach(s => ctrlBlock.addWritebackSink(s)) 272} 273 274class XSCore()(implicit p: config.Parameters) extends XSCoreBase 275 with HasXSDts 276{ 277 lazy val module = new XSCoreImp(this) 278} 279 280class XSCoreImp(outer: XSCoreBase) extends LazyModuleImp(outer) 281 with HasXSParameter 282 with HasSoCParameter { 283 val io = IO(new Bundle { 284 val hartId = Input(UInt(64.W)) 285 val reset_vector = Input(UInt(PAddrBits.W)) 286 val cpu_halt = Output(Bool()) 287 val l2_pf_enable = Output(Bool()) 288 val perfEvents = Input(Vec(numPCntHc * coreParams.L2NBanks, new PerfEvent)) 289 val beu_errors = Output(new XSL1BusErrors()) 290 }) 291 292 println(s"FPGAPlatform:${env.FPGAPlatform} EnableDebug:${env.EnableDebug}") 293 294 val frontend = outer.frontend.module 295 val ctrlBlock = outer.ctrlBlock.module 296 val wb2Ctrl = outer.wb2Ctrl.module 297 val memBlock = outer.memBlock.module 298 val ptw = outer.ptw.module 299 val ptw_to_l2_buffer = outer.ptw_to_l2_buffer.module 300 val exuBlocks = outer.exuBlocks.map(_.module) 301 302 frontend.io.hartId := io.hartId 303 ctrlBlock.io.hartId := io.hartId 304 exuBlocks.foreach(_.io.hartId := io.hartId) 305 memBlock.io.hartId := io.hartId 306 outer.wbArbiter.module.io.hartId := io.hartId 307 frontend.io.reset_vector := io.reset_vector 308 309 io.cpu_halt := ctrlBlock.io.cpu_halt 310 311 outer.wbArbiter.module.io.redirect <> ctrlBlock.io.redirect 312 val allWriteback = exuBlocks.flatMap(_.io.fuWriteback) ++ memBlock.io.writeback 313 require(exuConfigs.length == allWriteback.length, s"${exuConfigs.length} != ${allWriteback.length}") 314 outer.wbArbiter.module.io.in <> allWriteback 315 val rfWriteback = outer.wbArbiter.module.io.out 316 317 // memblock error exception writeback, 1 cycle after normal writeback 318 wb2Ctrl.io.s3_delayed_load_error <> memBlock.io.s3_delayed_load_error 319 320 wb2Ctrl.io.redirect <> ctrlBlock.io.redirect 321 outer.wb2Ctrl.generateWritebackIO() 322 323 io.beu_errors.icache <> frontend.io.error.toL1BusErrorUnitInfo() 324 io.beu_errors.dcache <> memBlock.io.error.toL1BusErrorUnitInfo() 325 326 require(exuBlocks.count(_.fuConfigs.map(_._1).contains(JumpCSRExeUnitCfg)) == 1) 327 val csrFenceMod = exuBlocks.filter(_.fuConfigs.map(_._1).contains(JumpCSRExeUnitCfg)).head 328 val csrioIn = csrFenceMod.io.fuExtra.csrio.get 329 val fenceio = csrFenceMod.io.fuExtra.fenceio.get 330 331 frontend.io.backend <> ctrlBlock.io.frontend 332 frontend.io.sfence <> fenceio.sfence 333 frontend.io.tlbCsr <> csrioIn.tlb 334 frontend.io.csrCtrl <> csrioIn.customCtrl 335 frontend.io.fencei := fenceio.fencei 336 337 ctrlBlock.io.csrCtrl <> csrioIn.customCtrl 338 val redirectBlocks = exuBlocks.reverse.filter(_.fuConfigs.map(_._1).map(_.hasRedirect).reduce(_ || _)) 339 ctrlBlock.io.exuRedirect <> redirectBlocks.flatMap(_.io.fuExtra.exuRedirect) 340 ctrlBlock.io.stIn <> memBlock.io.stIn 341 ctrlBlock.io.memoryViolation <> memBlock.io.memoryViolation 342 exuBlocks.head.io.scheExtra.enqLsq.get <> memBlock.io.enqLsq 343 exuBlocks.foreach(b => { 344 b.io.scheExtra.lcommit := ctrlBlock.io.robio.lsq.lcommit 345 b.io.scheExtra.scommit := memBlock.io.sqDeq 346 b.io.scheExtra.lqCancelCnt := memBlock.io.lqCancelCnt 347 b.io.scheExtra.sqCancelCnt := memBlock.io.sqCancelCnt 348 }) 349 val sourceModules = outer.writebackSources.map(_.map(_.module.asInstanceOf[HasWritebackSourceImp])) 350 outer.ctrlBlock.generateWritebackIO() 351 352 val allFastUop = exuBlocks.flatMap(b => b.io.fastUopOut.dropRight(b.numOutFu)) ++ memBlock.io.otherFastWakeup 353 require(allFastUop.length == exuConfigs.length, s"${allFastUop.length} != ${exuConfigs.length}") 354 val intFastUop = allFastUop.zip(exuConfigs).filter(_._2.writeIntRf).map(_._1) 355 val fpFastUop = allFastUop.zip(exuConfigs).filter(_._2.writeFpRf).map(_._1) 356 val intFastUop1 = outer.wbArbiter.intConnections.map(c => intFastUop(c.head)) 357 val fpFastUop1 = outer.wbArbiter.fpConnections.map(c => fpFastUop(c.head)) 358 val allFastUop1 = intFastUop1 ++ fpFastUop1 359 360 ctrlBlock.io.dispatch <> exuBlocks.flatMap(_.io.in) 361 ctrlBlock.io.rsReady := exuBlocks.flatMap(_.io.scheExtra.rsReady) 362 ctrlBlock.io.enqLsq <> memBlock.io.enqLsq 363 ctrlBlock.io.sqDeq := memBlock.io.sqDeq 364 ctrlBlock.io.lqCancelCnt := memBlock.io.lqCancelCnt 365 ctrlBlock.io.sqCancelCnt := memBlock.io.sqCancelCnt 366 367 exuBlocks(0).io.scheExtra.fpRfReadIn.get <> exuBlocks(1).io.scheExtra.fpRfReadOut.get 368 exuBlocks(0).io.scheExtra.fpStateReadIn.get <> exuBlocks(1).io.scheExtra.fpStateReadOut.get 369 370 memBlock.io.issue <> exuBlocks(0).io.issue.get 371 // By default, instructions do not have exceptions when they enter the function units. 372 memBlock.io.issue.map(_.bits.uop.clearExceptions()) 373 exuBlocks(0).io.scheExtra.loadFastMatch.get <> memBlock.io.loadFastMatch 374 exuBlocks(0).io.scheExtra.loadFastImm.get <> memBlock.io.loadFastImm 375 376 val stdIssue = exuBlocks(0).io.issue.get.takeRight(exuParameters.StuCnt) 377 exuBlocks.map(_.io).foreach { exu => 378 exu.redirect <> ctrlBlock.io.redirect 379 exu.allocPregs <> ctrlBlock.io.allocPregs 380 exu.rfWriteback <> rfWriteback 381 exu.fastUopIn <> allFastUop1 382 exu.scheExtra.jumpPc <> ctrlBlock.io.jumpPc 383 exu.scheExtra.jalr_target <> ctrlBlock.io.jalr_target 384 exu.scheExtra.stIssuePtr <> memBlock.io.stIssuePtr 385 exu.scheExtra.debug_fp_rat <> ctrlBlock.io.debug_fp_rat 386 exu.scheExtra.debug_int_rat <> ctrlBlock.io.debug_int_rat 387 exu.scheExtra.memWaitUpdateReq.staIssue.zip(memBlock.io.stIn).foreach{case (sink, src) => { 388 sink.bits := src.bits 389 sink.valid := src.valid 390 }} 391 exu.scheExtra.memWaitUpdateReq.stdIssue.zip(stdIssue).foreach{case (sink, src) => { 392 sink.valid := src.valid 393 sink.bits := src.bits 394 }} 395 } 396 XSPerfHistogram("fastIn_count", PopCount(allFastUop1.map(_.valid)), true.B, 0, allFastUop1.length, 1) 397 XSPerfHistogram("wakeup_count", PopCount(rfWriteback.map(_.valid)), true.B, 0, rfWriteback.length, 1) 398 399 ctrlBlock.perfinfo.perfEventsEu0 := exuBlocks(0).getPerf.dropRight(outer.exuBlocks(0).scheduler.numRs) 400 ctrlBlock.perfinfo.perfEventsEu1 := exuBlocks(1).getPerf.dropRight(outer.exuBlocks(1).scheduler.numRs) 401 memBlock.io.perfEventsPTW := ptw.getPerf 402 ctrlBlock.perfinfo.perfEventsRs := outer.exuBlocks.flatMap(b => b.module.getPerf.takeRight(b.scheduler.numRs)) 403 404 csrioIn.hartId <> io.hartId 405 csrioIn.perf <> DontCare 406 csrioIn.perf.retiredInstr <> ctrlBlock.io.robio.toCSR.perfinfo.retiredInstr 407 csrioIn.perf.ctrlInfo <> ctrlBlock.io.perfInfo.ctrlInfo 408 csrioIn.perf.memInfo <> memBlock.io.memInfo 409 csrioIn.perf.frontendInfo <> frontend.io.frontendInfo 410 411 csrioIn.perf.perfEventsFrontend <> frontend.getPerf 412 csrioIn.perf.perfEventsCtrl <> ctrlBlock.getPerf 413 csrioIn.perf.perfEventsLsu <> memBlock.getPerf 414 csrioIn.perf.perfEventsHc <> io.perfEvents 415 416 csrioIn.fpu.fflags <> ctrlBlock.io.robio.toCSR.fflags 417 csrioIn.fpu.isIllegal := false.B 418 csrioIn.fpu.dirty_fs <> ctrlBlock.io.robio.toCSR.dirty_fs 419 csrioIn.fpu.frm <> exuBlocks(1).io.fuExtra.frm.get 420 csrioIn.exception <> ctrlBlock.io.robio.exception 421 csrioIn.isXRet <> ctrlBlock.io.robio.toCSR.isXRet 422 csrioIn.trapTarget <> ctrlBlock.io.robio.toCSR.trapTarget 423 csrioIn.interrupt <> ctrlBlock.io.robio.toCSR.intrBitSet 424 csrioIn.wfi_event <> ctrlBlock.io.robio.toCSR.wfiEvent 425 csrioIn.memExceptionVAddr <> memBlock.io.lsqio.exceptionAddr.vaddr 426 427 csrioIn.externalInterrupt.msip := outer.clint_int_sink.in.head._1(0) 428 csrioIn.externalInterrupt.mtip := outer.clint_int_sink.in.head._1(1) 429 csrioIn.externalInterrupt.meip := outer.plic_int_sink.in.head._1(0) 430 csrioIn.externalInterrupt.seip := outer.plic_int_sink.in.last._1(0) 431 csrioIn.externalInterrupt.debug := outer.debug_int_sink.in.head._1(0) 432 433 csrioIn.distributedUpdate(0).w.valid := memBlock.io.csrUpdate.w.valid 434 csrioIn.distributedUpdate(0).w.bits := memBlock.io.csrUpdate.w.bits 435 csrioIn.distributedUpdate(1).w.valid := frontend.io.csrUpdate.w.valid 436 csrioIn.distributedUpdate(1).w.bits := frontend.io.csrUpdate.w.bits 437 438 fenceio.sfence <> memBlock.io.sfence 439 fenceio.sbuffer <> memBlock.io.fenceToSbuffer 440 441 memBlock.io.redirect <> ctrlBlock.io.redirect 442 memBlock.io.rsfeedback <> exuBlocks(0).io.scheExtra.feedback.get 443 memBlock.io.csrCtrl <> csrioIn.customCtrl 444 memBlock.io.tlbCsr <> csrioIn.tlb 445 memBlock.io.lsqio.rob <> ctrlBlock.io.robio.lsq 446 memBlock.io.lsqio.exceptionAddr.isStore := CommitType.lsInstIsStore(ctrlBlock.io.robio.exception.bits.uop.ctrl.commitType) 447 448 val itlbRepeater1 = PTWFilter(itlbParams.fenceDelay,frontend.io.ptw, fenceio.sfence, csrioIn.tlb, l2tlbParams.ifilterSize) 449 val itlbRepeater2 = PTWRepeaterNB(passReady = false, itlbParams.fenceDelay, itlbRepeater1.io.ptw, ptw.io.tlb(0), fenceio.sfence, csrioIn.tlb) 450 val dtlbRepeater1 = PTWFilter(ldtlbParams.fenceDelay, memBlock.io.ptw, fenceio.sfence, csrioIn.tlb, l2tlbParams.dfilterSize) 451 val dtlbRepeater2 = PTWRepeaterNB(passReady = false, ldtlbParams.fenceDelay, dtlbRepeater1.io.ptw, ptw.io.tlb(1), fenceio.sfence, csrioIn.tlb) 452 ptw.io.sfence <> fenceio.sfence 453 ptw.io.csr.tlb <> csrioIn.tlb 454 ptw.io.csr.distribute_csr <> csrioIn.customCtrl.distribute_csr 455 456 // if l2 prefetcher use stream prefetch, it should be placed in XSCore 457 io.l2_pf_enable := csrioIn.customCtrl.l2_pf_enable 458 459 // Modules are reset one by one 460 val resetTree = ResetGenNode( 461 Seq( 462 ModuleNode(memBlock), ModuleNode(dtlbRepeater1), 463 ResetGenNode(Seq( 464 ModuleNode(itlbRepeater2), 465 ModuleNode(ptw), 466 ModuleNode(dtlbRepeater2), 467 ModuleNode(ptw_to_l2_buffer), 468 )), 469 ResetGenNode(Seq( 470 ModuleNode(exuBlocks.head), 471 ResetGenNode( 472 exuBlocks.tail.map(m => ModuleNode(m)) :+ ModuleNode(outer.wbArbiter.module) 473 ), 474 ResetGenNode(Seq( 475 ModuleNode(ctrlBlock), 476 ResetGenNode(Seq( 477 ModuleNode(frontend), ModuleNode(itlbRepeater1) 478 )) 479 )) 480 )) 481 ) 482 ) 483 484 ResetGen(resetTree, reset.asBool, !debugOpts.FPGAPlatform) 485 486} 487