1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import noop.{Cache, CacheConfig, HasExceptionNO, TLB, TLBConfig} 6import top.Parameters 7import xiangshan.backend._ 8import xiangshan.backend.dispatch.DispatchParameters 9import xiangshan.backend.exu.ExuParameters 10import xiangshan.frontend._ 11import xiangshan.mem._ 12import xiangshan.cache.{ICache, DCache, DCacheParameters, ICacheParameters, PTW, Uncache} 13import chipsalliance.rocketchip.config 14import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 15import freechips.rocketchip.tilelink.{TLBundleParameters, TLCacheCork, TLBuffer, TLClientNode, TLIdentityNode, TLXbar} 16import sifive.blocks.inclusivecache.{CacheParameters, InclusiveCache, InclusiveCacheMicroParameters} 17import utils._ 18 19case class XSCoreParameters 20( 21 XLEN: Int = 64, 22 HasMExtension: Boolean = true, 23 HasCExtension: Boolean = true, 24 HasDiv: Boolean = true, 25 HasICache: Boolean = true, 26 HasDCache: Boolean = true, 27 EnableStoreQueue: Boolean = true, 28 AddrBits: Int = 64, 29 VAddrBits: Int = 39, 30 PAddrBits: Int = 40, 31 HasFPU: Boolean = true, 32 FectchWidth: Int = 8, 33 EnableBPU: Boolean = true, 34 EnableBPD: Boolean = true, 35 EnableRAS: Boolean = false, 36 EnableLB: Boolean = false, 37 HistoryLength: Int = 64, 38 BtbSize: Int = 256, 39 JbtacSize: Int = 1024, 40 JbtacBanks: Int = 8, 41 RasSize: Int = 16, 42 CacheLineSize: Int = 512, 43 UBtbWays: Int = 16, 44 BtbWays: Int = 2, 45 IBufSize: Int = 64, 46 DecodeWidth: Int = 6, 47 RenameWidth: Int = 6, 48 CommitWidth: Int = 6, 49 BrqSize: Int = 16, 50 IssQueSize: Int = 8, 51 NRPhyRegs: Int = 128, 52 NRIntReadPorts: Int = 8, 53 NRIntWritePorts: Int = 8, 54 NRFpReadPorts: Int = 14, 55 NRFpWritePorts: Int = 8, 56 LsroqSize: Int = 16, 57 RoqSize: Int = 32, 58 dpParams: DispatchParameters = DispatchParameters( 59 DqEnqWidth = 4, 60 IntDqSize = 64, 61 FpDqSize = 64, 62 LsDqSize = 64, 63 IntDqDeqWidth = 4, 64 FpDqDeqWidth = 4, 65 LsDqDeqWidth = 4, 66 IntDqReplayWidth = 4, 67 FpDqReplayWidth = 4, 68 LsDqReplayWidth = 4 69 ), 70 exuParameters: ExuParameters = ExuParameters( 71 JmpCnt = 1, 72 AluCnt = 4, 73 MulCnt = 0, 74 MduCnt = 2, 75 FmacCnt = 0, 76 FmiscCnt = 0, 77 FmiscDivSqrtCnt = 0, 78 LduCnt = 2, 79 StuCnt = 2 80 ), 81 LoadPipelineWidth: Int = 2, 82 StorePipelineWidth: Int = 2, 83 StoreBufferSize: Int = 16, 84 RefillSize: Int = 512, 85 TlbEntrySize: Int = 32, 86 TlbL2EntrySize: Int = 256, // or 512 87 PtwL1EntrySize: Int = 16, 88 PtwL2EntrySize: Int = 256 89) 90 91trait HasXSParameter { 92 93 val core = Parameters.get.coreParameters 94 val env = Parameters.get.envParameters 95 96 val XLEN = core.XLEN 97 val HasMExtension = core.HasMExtension 98 val HasCExtension = core.HasCExtension 99 val HasDiv = core.HasDiv 100 val HasIcache = core.HasICache 101 val HasDcache = core.HasDCache 102 val EnableStoreQueue = core.EnableStoreQueue 103 val AddrBits = core.AddrBits // AddrBits is used in some cases 104 val VAddrBits = core.VAddrBits // VAddrBits is Virtual Memory addr bits 105 val PAddrBits = core.PAddrBits // PAddrBits is Phyical Memory addr bits 106 val AddrBytes = AddrBits / 8 // unused 107 val DataBits = XLEN 108 val DataBytes = DataBits / 8 109 val HasFPU = core.HasFPU 110 val FetchWidth = core.FectchWidth 111 val PredictWidth = FetchWidth * 2 112 val EnableBPU = core.EnableBPU 113 val EnableBPD = core.EnableBPD // enable backing predictor(like Tage) in BPUStage3 114 val EnableRAS = core.EnableRAS 115 val EnableLB = core.EnableLB 116 val HistoryLength = core.HistoryLength 117 val BtbSize = core.BtbSize 118 // val BtbWays = 4 119 val BtbBanks = PredictWidth 120 // val BtbSets = BtbSize / BtbWays 121 val JbtacSize = core.JbtacSize 122 val JbtacBanks = core.JbtacBanks 123 val RasSize = core.RasSize 124 val CacheLineSize = core.CacheLineSize 125 val CacheLineHalfWord = CacheLineSize / 16 126 val ExtHistoryLength = HistoryLength * 2 127 val UBtbWays = core.UBtbWays 128 val BtbWays = core.BtbWays 129 val IBufSize = core.IBufSize 130 val DecodeWidth = core.DecodeWidth 131 val RenameWidth = core.RenameWidth 132 val CommitWidth = core.CommitWidth 133 val BrqSize = core.BrqSize 134 val IssQueSize = core.IssQueSize 135 val BrTagWidth = log2Up(BrqSize) 136 val NRPhyRegs = core.NRPhyRegs 137 val PhyRegIdxWidth = log2Up(NRPhyRegs) 138 val LsroqSize = core.LsroqSize // 64 139 val RoqSize = core.RoqSize 140 val InnerRoqIdxWidth = log2Up(RoqSize) 141 val RoqIdxWidth = InnerRoqIdxWidth + 1 142 val InnerLsroqIdxWidth = log2Up(LsroqSize) 143 val LsroqIdxWidth = InnerLsroqIdxWidth + 1 144 val dpParams = core.dpParams 145 val ReplayWidth = dpParams.IntDqReplayWidth + dpParams.FpDqReplayWidth + dpParams.LsDqReplayWidth 146 val exuParameters = core.exuParameters 147 val NRIntReadPorts = core.NRIntReadPorts 148 val NRIntWritePorts = core.NRIntWritePorts 149 val NRMemReadPorts = exuParameters.LduCnt + 2*exuParameters.StuCnt 150 val NRFpReadPorts = core.NRFpReadPorts 151 val NRFpWritePorts = core.NRFpWritePorts 152 val LoadPipelineWidth = core.LoadPipelineWidth 153 val StorePipelineWidth = core.StorePipelineWidth 154 val StoreBufferSize = core.StoreBufferSize 155 val RefillSize = core.RefillSize 156 val DTLBWidth = core.LoadPipelineWidth + core.StorePipelineWidth 157 val TlbEntrySize = core.TlbEntrySize 158 val TlbL2EntrySize = core.TlbL2EntrySize 159 val PtwL1EntrySize = core.PtwL1EntrySize 160 val PtwL2EntrySize = core.PtwL2EntrySize 161 162 val l1BusDataWidth = 64 163 164 val icacheParameters = ICacheParameters( 165 ) 166 167 val LRSCCycles = 100 168 val dcacheParameters = DCacheParameters( 169 tagECC = Some("secded"), 170 dataECC = Some("secded"), 171 nMissEntries = 16, 172 nLoadMissEntries = 8, 173 nStoreMissEntries = 8 174 ) 175} 176 177trait HasXSLog { this: RawModule => 178 implicit val moduleName: String = this.name 179} 180 181abstract class XSModule extends Module 182 with HasXSParameter 183 with HasExceptionNO 184 with HasXSLog 185 186//remove this trait after impl module logic 187trait NeedImpl { this: Module => 188 override protected def IO[T <: Data](iodef: T): T = { 189 val io = chisel3.experimental.IO(iodef) 190 io <> DontCare 191 io 192 } 193} 194 195abstract class XSBundle extends Bundle 196 with HasXSParameter 197 198case class EnviromentParameters 199( 200 FPGAPlatform: Boolean = true, 201 EnableDebug: Boolean = false 202) 203 204object AddressSpace extends HasXSParameter { 205 // (start, size) 206 // address out of MMIO will be considered as DRAM 207 def mmio = List( 208 (0x30000000L, 0x10000000L), // internal devices, such as CLINT and PLIC 209 (0x40000000L, 0x40000000L) // external devices 210 ) 211 212 def isMMIO(addr: UInt): Bool = mmio.map(range => { 213 require(isPow2(range._2)) 214 val bits = log2Up(range._2) 215 (addr ^ range._1.U)(PAddrBits-1, bits) === 0.U 216 }).reduce(_ || _) 217} 218 219 220 221class XSCore()(implicit p: config.Parameters) extends LazyModule { 222 223 val dcache = LazyModule(new DCache()) 224 val uncache = LazyModule(new Uncache()) 225 val icache = LazyModule(new ICache()) 226 val ptw = LazyModule(new PTW()) 227 228 val mem = TLIdentityNode() 229 val mmio = uncache.clientNode 230 231 // TODO: refactor these params 232 private val l2 = LazyModule(new InclusiveCache( 233 CacheParameters( 234 level = 2, 235 ways = 4, 236 sets = 512 * 1024 / (64 * 4), 237 blockBytes = 64, 238 beatBytes = 8 239 ), 240 InclusiveCacheMicroParameters( 241 writeBytes = 8 242 ) 243 )) 244 245 private val xbar = TLXbar() 246 247 xbar := TLBuffer() := DebugIdentityNode() := dcache.clientNode 248 xbar := TLBuffer() := DebugIdentityNode() := icache.clientNode 249 xbar := TLBuffer() := DebugIdentityNode() := ptw.node 250 251 l2.node := xbar 252 253 mem := TLBuffer() := TLCacheCork() := TLBuffer() := l2.node 254 255 lazy val module = new XSCoreImp(this) 256} 257 258class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer) with HasXSParameter { 259 260 val front = Module(new Frontend) 261 val backend = Module(new Backend) 262 val mem = Module(new Memend) 263 264 val dcache = outer.dcache.module 265 val uncache = outer.uncache.module 266 val icache = outer.icache.module 267 val ptw = outer.ptw.module 268 269 // TODO: connect this 270 271 front.io.backend <> backend.io.frontend 272 front.io.icacheResp <> icache.io.resp 273 front.io.icacheToTlb <> icache.io.tlb 274 icache.io.req <> front.io.icacheReq 275 icache.io.flush <> front.io.icacheFlush 276 mem.io.backend <> backend.io.mem 277 278 ptw.io.tlb(0) <> mem.io.ptw 279 ptw.io.tlb(1) <> front.io.ptw 280 281 dcache.io.lsu.load <> mem.io.loadUnitToDcacheVec 282 dcache.io.lsu.lsroq <> mem.io.loadMiss 283 dcache.io.lsu.atomics <> mem.io.atomics 284 dcache.io.lsu.store <> mem.io.sbufferToDcache 285 uncache.io.lsroq <> mem.io.uncache 286 287} 288