1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import top.Parameters 6import xiangshan.backend._ 7import xiangshan.backend.dispatch.DispatchParameters 8import xiangshan.backend.exu.ExuParameters 9import xiangshan.backend.exu.Exu._ 10import xiangshan.frontend._ 11import xiangshan.mem._ 12import xiangshan.backend.fu.HasExceptionNO 13import xiangshan.cache.{DCache,InstrUncache, DCacheParameters, ICache, ICacheParameters, L1plusCache, L1plusCacheParameters, PTW, Uncache} 14import xiangshan.cache.prefetch._ 15import chipsalliance.rocketchip.config 16import freechips.rocketchip.diplomacy.{AddressSet, LazyModule, LazyModuleImp} 17import freechips.rocketchip.tilelink.{TLBuffer, TLBundleParameters, TLCacheCork, TLClientNode, TLFilter, TLIdentityNode, TLToAXI4, TLWidthWidget, TLXbar} 18import freechips.rocketchip.devices.tilelink.{DevNullParams, TLError} 19import sifive.blocks.inclusivecache.{CacheParameters, InclusiveCache, InclusiveCacheMicroParameters} 20import freechips.rocketchip.amba.axi4.{AXI4Deinterleaver, AXI4Fragmenter, AXI4IdIndexer, AXI4IdentityNode, AXI4ToTL, AXI4UserYanker} 21import freechips.rocketchip.tile.HasFPUParameters 22import utils._ 23 24case class XSCoreParameters 25( 26 XLEN: Int = 64, 27 HasMExtension: Boolean = true, 28 HasCExtension: Boolean = true, 29 HasDiv: Boolean = true, 30 HasICache: Boolean = true, 31 HasDCache: Boolean = true, 32 EnableStoreQueue: Boolean = true, 33 AddrBits: Int = 64, 34 VAddrBits: Int = 39, 35 PAddrBits: Int = 40, 36 HasFPU: Boolean = true, 37 FectchWidth: Int = 8, 38 EnableBPU: Boolean = true, 39 EnableBPD: Boolean = true, 40 EnableRAS: Boolean = true, 41 EnableLB: Boolean = false, 42 EnableLoop: Boolean = true, 43 EnableSC: Boolean = false, 44 HistoryLength: Int = 64, 45 BtbSize: Int = 2048, 46 JbtacSize: Int = 1024, 47 JbtacBanks: Int = 8, 48 RasSize: Int = 16, 49 CacheLineSize: Int = 512, 50 UBtbWays: Int = 16, 51 BtbWays: Int = 2, 52 53 EnableL1plusPrefetcher: Boolean = true, 54 IBufSize: Int = 32, 55 DecodeWidth: Int = 6, 56 RenameWidth: Int = 6, 57 CommitWidth: Int = 6, 58 BrqSize: Int = 32, 59 FtqSize: Int = 48, 60 IssQueSize: Int = 12, 61 NRPhyRegs: Int = 160, 62 NRIntReadPorts: Int = 14, 63 NRIntWritePorts: Int = 8, 64 NRFpReadPorts: Int = 14, 65 NRFpWritePorts: Int = 8, 66 LoadQueueSize: Int = 64, 67 StoreQueueSize: Int = 48, 68 RoqSize: Int = 192, 69 dpParams: DispatchParameters = DispatchParameters( 70 IntDqSize = 32, 71 FpDqSize = 32, 72 LsDqSize = 32, 73 IntDqDeqWidth = 4, 74 FpDqDeqWidth = 4, 75 LsDqDeqWidth = 4 76 ), 77 exuParameters: ExuParameters = ExuParameters( 78 JmpCnt = 1, 79 AluCnt = 4, 80 MulCnt = 0, 81 MduCnt = 2, 82 FmacCnt = 4, 83 FmiscCnt = 2, 84 FmiscDivSqrtCnt = 0, 85 LduCnt = 2, 86 StuCnt = 2 87 ), 88 LoadPipelineWidth: Int = 2, 89 StorePipelineWidth: Int = 2, 90 StoreBufferSize: Int = 16, 91 RefillSize: Int = 512, 92 TlbEntrySize: Int = 32, 93 TlbSPEntrySize: Int = 4, 94 TlbL2EntrySize: Int = 256, // or 512 95 TlbL2SPEntrySize: Int = 16, 96 PtwL1EntrySize: Int = 16, 97 PtwL2EntrySize: Int = 256, 98 NumPerfCounters: Int = 16, 99 NrExtIntr: Int = 1 100) 101 102trait HasXSParameter { 103 104 val core = Parameters.get.coreParameters 105 val env = Parameters.get.envParameters 106 107 val XLEN = 64 108 val minFLen = 32 109 val fLen = 64 110 def xLen = 64 111 val HasMExtension = core.HasMExtension 112 val HasCExtension = core.HasCExtension 113 val HasDiv = core.HasDiv 114 val HasIcache = core.HasICache 115 val HasDcache = core.HasDCache 116 val EnableStoreQueue = core.EnableStoreQueue 117 val AddrBits = core.AddrBits // AddrBits is used in some cases 118 val VAddrBits = core.VAddrBits // VAddrBits is Virtual Memory addr bits 119 val PAddrBits = core.PAddrBits // PAddrBits is Phyical Memory addr bits 120 val AddrBytes = AddrBits / 8 // unused 121 val DataBits = XLEN 122 val DataBytes = DataBits / 8 123 val HasFPU = core.HasFPU 124 val FetchWidth = core.FectchWidth 125 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 126 val EnableBPU = core.EnableBPU 127 val EnableBPD = core.EnableBPD // enable backing predictor(like Tage) in BPUStage3 128 val EnableRAS = core.EnableRAS 129 val EnableLB = core.EnableLB 130 val EnableLoop = core.EnableLoop 131 val EnableSC = core.EnableSC 132 val HistoryLength = core.HistoryLength 133 val BtbSize = core.BtbSize 134 // val BtbWays = 4 135 val BtbBanks = PredictWidth 136 // val BtbSets = BtbSize / BtbWays 137 val JbtacSize = core.JbtacSize 138 val JbtacBanks = core.JbtacBanks 139 val RasSize = core.RasSize 140 val CacheLineSize = core.CacheLineSize 141 val CacheLineHalfWord = CacheLineSize / 16 142 val ExtHistoryLength = HistoryLength + 64 143 val UBtbWays = core.UBtbWays 144 val BtbWays = core.BtbWays 145 val EnableL1plusPrefetcher = core.EnableL1plusPrefetcher 146 val IBufSize = core.IBufSize 147 val DecodeWidth = core.DecodeWidth 148 val RenameWidth = core.RenameWidth 149 val CommitWidth = core.CommitWidth 150 val BrqSize = core.BrqSize 151 val FtqSize = core.FtqSize 152 val IssQueSize = core.IssQueSize 153 val BrTagWidth = log2Up(BrqSize) 154 val NRPhyRegs = core.NRPhyRegs 155 val PhyRegIdxWidth = log2Up(NRPhyRegs) 156 val RoqSize = core.RoqSize 157 val LoadQueueSize = core.LoadQueueSize 158 val StoreQueueSize = core.StoreQueueSize 159 val dpParams = core.dpParams 160 val exuParameters = core.exuParameters 161 val NRIntReadPorts = core.NRIntReadPorts 162 val NRIntWritePorts = core.NRIntWritePorts 163 val NRMemReadPorts = exuParameters.LduCnt + 2*exuParameters.StuCnt 164 val NRFpReadPorts = core.NRFpReadPorts 165 val NRFpWritePorts = core.NRFpWritePorts 166 val LoadPipelineWidth = core.LoadPipelineWidth 167 val StorePipelineWidth = core.StorePipelineWidth 168 val StoreBufferSize = core.StoreBufferSize 169 val RefillSize = core.RefillSize 170 val DTLBWidth = core.LoadPipelineWidth + core.StorePipelineWidth 171 val TlbEntrySize = core.TlbEntrySize 172 val TlbSPEntrySize = core.TlbSPEntrySize 173 val TlbL2EntrySize = core.TlbL2EntrySize 174 val TlbL2SPEntrySize = core.TlbL2SPEntrySize 175 val PtwL1EntrySize = core.PtwL1EntrySize 176 val PtwL2EntrySize = core.PtwL2EntrySize 177 val NumPerfCounters = core.NumPerfCounters 178 val NrExtIntr = core.NrExtIntr 179 180 val instBytes = if (HasCExtension) 2 else 4 181 val instOffsetBits = log2Ceil(instBytes) 182 183 val icacheParameters = ICacheParameters( 184 tagECC = Some("parity"), 185 dataECC = Some("parity"), 186 nMissEntries = 2 187 ) 188 189 val l1plusCacheParameters = L1plusCacheParameters( 190 tagECC = Some("secded"), 191 dataECC = Some("secded"), 192 nMissEntries = 8 193 ) 194 195 val dcacheParameters = DCacheParameters( 196 tagECC = Some("secded"), 197 dataECC = Some("secded"), 198 nMissEntries = 16, 199 nLoadMissEntries = 8, 200 nStoreMissEntries = 8 201 ) 202 203 val LRSCCycles = 100 204 205 206 // cache hierarchy configurations 207 val l1BusDataWidth = 256 208 209 // L2 configurations 210 val L1BusWidth = 256 211 val L2Size = 512 * 1024 // 512KB 212 val L2BlockSize = 64 213 val L2NWays = 8 214 val L2NSets = L2Size / L2BlockSize / L2NWays 215 216 // L3 configurations 217 val L2BusWidth = 256 218 val L3Size = 4 * 1024 * 1024 // 4MB 219 val L3BlockSize = 64 220 val L3NBanks = 4 221 val L3NWays = 8 222 val L3NSets = L3Size / L3BlockSize / L3NBanks / L3NWays 223 224 // on chip network configurations 225 val L3BusWidth = 256 226 227 // icache prefetcher 228 val l1plusPrefetcherParameters = L1plusPrefetcherParameters( 229 enable = true, 230 _type = "stream", 231 streamParams = StreamPrefetchParameters( 232 streamCnt = 2, 233 streamSize = 4, 234 ageWidth = 4, 235 blockBytes = l1plusCacheParameters.blockBytes, 236 reallocStreamOnMissInstantly = true, 237 cacheName = "icache" 238 ) 239 ) 240 241 // dcache prefetcher 242 val l2PrefetcherParameters = L2PrefetcherParameters( 243 enable = true, 244 _type = "stream", 245 streamParams = StreamPrefetchParameters( 246 streamCnt = 4, 247 streamSize = 4, 248 ageWidth = 4, 249 blockBytes = L2BlockSize, 250 reallocStreamOnMissInstantly = true, 251 cacheName = "dcache" 252 ) 253 ) 254} 255 256trait HasXSLog { this: RawModule => 257 implicit val moduleName: String = this.name 258} 259 260abstract class XSModule extends MultiIOModule 261 with HasXSParameter 262 with HasExceptionNO 263 with HasXSLog 264 with HasFPUParameters 265{ 266 def io: Record 267} 268 269//remove this trait after impl module logic 270trait NeedImpl { this: RawModule => 271 override protected def IO[T <: Data](iodef: T): T = { 272 println(s"[Warn]: (${this.name}) please reomve 'NeedImpl' after implement this module") 273 val io = chisel3.experimental.IO(iodef) 274 io <> DontCare 275 io 276 } 277} 278 279abstract class XSBundle extends Bundle 280 with HasXSParameter 281 282case class EnviromentParameters 283( 284 FPGAPlatform: Boolean = true, 285 EnableDebug: Boolean = false, 286 EnablePerfDebug: Boolean = false 287) 288 289// object AddressSpace extends HasXSParameter { 290// // (start, size) 291// // address out of MMIO will be considered as DRAM 292// def mmio = List( 293// (0x00000000L, 0x40000000L), // internal devices, such as CLINT and PLIC 294// (0x40000000L, 0x40000000L) // external devices 295// ) 296 297// def isMMIO(addr: UInt): Bool = mmio.map(range => { 298// require(isPow2(range._2)) 299// val bits = log2Up(range._2) 300// (addr ^ range._1.U)(PAddrBits-1, bits) === 0.U 301// }).reduce(_ || _) 302// } 303 304 305 306class XSCore()(implicit p: config.Parameters) extends LazyModule 307 with HasXSParameter 308 with HasExeBlockHelper 309{ 310 311 // to fast wake up fp, mem rs 312 val intBlockFastWakeUpFp = intExuConfigs.filter(fpFastFilter) 313 val intBlockSlowWakeUpFp = intExuConfigs.filter(fpSlowFilter) 314 val intBlockFastWakeUpInt = intExuConfigs.filter(intFastFilter) 315 val intBlockSlowWakeUpInt = intExuConfigs.filter(intSlowFilter) 316 317 val fpBlockFastWakeUpFp = fpExuConfigs.filter(fpFastFilter) 318 val fpBlockSlowWakeUpFp = fpExuConfigs.filter(fpSlowFilter) 319 val fpBlockFastWakeUpInt = fpExuConfigs.filter(intFastFilter) 320 val fpBlockSlowWakeUpInt = fpExuConfigs.filter(intSlowFilter) 321 322 // outer facing nodes 323 val l1pluscache = LazyModule(new L1plusCache()) 324 val instrUncache = LazyModule(new InstrUncache()) 325 val ptw = LazyModule(new PTW()) 326 val l2Prefetcher = LazyModule(new L2Prefetcher()) 327 val memBlock = LazyModule(new MemBlock( 328 fastWakeUpIn = intBlockFastWakeUpInt ++ intBlockFastWakeUpFp ++ fpBlockFastWakeUpInt ++ fpBlockFastWakeUpFp, 329 slowWakeUpIn = intBlockSlowWakeUpInt ++ intBlockSlowWakeUpFp ++ fpBlockSlowWakeUpInt ++ fpBlockSlowWakeUpFp, 330 fastFpOut = Seq(), 331 slowFpOut = loadExuConfigs, 332 fastIntOut = Seq(), 333 slowIntOut = loadExuConfigs 334 )) 335 336 lazy val module = new XSCoreImp(this) 337} 338 339class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer) 340 with HasXSParameter 341 with HasExeBlockHelper 342{ 343 val io = IO(new Bundle { 344 val externalInterrupt = new ExternalInterruptIO 345 }) 346 347 println(s"FPGAPlatform:${env.FPGAPlatform} EnableDebug:${env.EnableDebug}") 348 AddressSpace.printMemmap() 349 350 // to fast wake up fp, mem rs 351 val intBlockFastWakeUpFp = intExuConfigs.filter(fpFastFilter) 352 val intBlockSlowWakeUpFp = intExuConfigs.filter(fpSlowFilter) 353 val intBlockFastWakeUpInt = intExuConfigs.filter(intFastFilter) 354 val intBlockSlowWakeUpInt = intExuConfigs.filter(intSlowFilter) 355 356 val fpBlockFastWakeUpFp = fpExuConfigs.filter(fpFastFilter) 357 val fpBlockSlowWakeUpFp = fpExuConfigs.filter(fpSlowFilter) 358 val fpBlockFastWakeUpInt = fpExuConfigs.filter(intFastFilter) 359 val fpBlockSlowWakeUpInt = fpExuConfigs.filter(intSlowFilter) 360 361 val frontend = Module(new Frontend) 362 val ctrlBlock = Module(new CtrlBlock) 363 val integerBlock = Module(new IntegerBlock( 364 fastWakeUpIn = fpBlockFastWakeUpInt, 365 slowWakeUpIn = fpBlockSlowWakeUpInt ++ loadExuConfigs, 366 fastFpOut = intBlockFastWakeUpFp, 367 slowFpOut = intBlockSlowWakeUpFp, 368 fastIntOut = intBlockFastWakeUpInt, 369 slowIntOut = intBlockSlowWakeUpInt 370 )) 371 val floatBlock = Module(new FloatBlock( 372 fastWakeUpIn = intBlockFastWakeUpFp, 373 slowWakeUpIn = intBlockSlowWakeUpFp ++ loadExuConfigs, 374 fastFpOut = fpBlockFastWakeUpFp, 375 slowFpOut = fpBlockSlowWakeUpFp, 376 fastIntOut = fpBlockFastWakeUpInt, 377 slowIntOut = fpBlockSlowWakeUpInt 378 )) 379 380 val memBlock = outer.memBlock.module 381 val instrUncache = outer.instrUncache.module 382 val l1pluscache = outer.l1pluscache.module 383 val ptw = outer.ptw.module 384 val l2Prefetcher = outer.l2Prefetcher.module 385 386 frontend.io.backend <> ctrlBlock.io.frontend 387 frontend.io.sfence <> integerBlock.io.fenceio.sfence 388 frontend.io.tlbCsr <> integerBlock.io.csrio.tlb 389 390 frontend.io.icacheMemAcq <> l1pluscache.io.req 391 l1pluscache.io.resp <> frontend.io.icacheMemGrant 392 l1pluscache.io.flush := frontend.io.l1plusFlush 393 frontend.io.fencei := integerBlock.io.fenceio.fencei 394 395 instrUncache.io.req <> frontend.io.mmio_acquire 396 instrUncache.io.resp <> frontend.io.mmio_grant 397 instrUncache.io.flush <> frontend.io.mmio_flush 398 399 ctrlBlock.io.fromIntBlock <> integerBlock.io.toCtrlBlock 400 ctrlBlock.io.fromFpBlock <> floatBlock.io.toCtrlBlock 401 ctrlBlock.io.fromLsBlock <> memBlock.io.toCtrlBlock 402 ctrlBlock.io.toIntBlock <> integerBlock.io.fromCtrlBlock 403 ctrlBlock.io.toFpBlock <> floatBlock.io.fromCtrlBlock 404 ctrlBlock.io.toLsBlock <> memBlock.io.fromCtrlBlock 405 406 integerBlock.io.wakeUpIn.fastUops <> floatBlock.io.wakeUpIntOut.fastUops 407 integerBlock.io.wakeUpIn.fast <> floatBlock.io.wakeUpIntOut.fast 408 integerBlock.io.wakeUpIn.slow <> floatBlock.io.wakeUpIntOut.slow ++ memBlock.io.wakeUpIntOut.slow 409 integerBlock.io.toMemBlock <> memBlock.io.fromIntBlock 410 411 floatBlock.io.wakeUpIn.fastUops <> integerBlock.io.wakeUpFpOut.fastUops 412 floatBlock.io.wakeUpIn.fast <> integerBlock.io.wakeUpFpOut.fast 413 floatBlock.io.wakeUpIn.slow <> integerBlock.io.wakeUpFpOut.slow ++ memBlock.io.wakeUpFpOut.slow 414 floatBlock.io.toMemBlock <> memBlock.io.fromFpBlock 415 416 417 integerBlock.io.wakeUpIntOut.fast.map(_.ready := true.B) 418 integerBlock.io.wakeUpIntOut.slow.map(_.ready := true.B) 419 floatBlock.io.wakeUpFpOut.fast.map(_.ready := true.B) 420 floatBlock.io.wakeUpFpOut.slow.map(_.ready := true.B) 421 422 val wakeUpMem = Seq( 423 integerBlock.io.wakeUpIntOut, 424 integerBlock.io.wakeUpFpOut, 425 floatBlock.io.wakeUpIntOut, 426 floatBlock.io.wakeUpFpOut 427 ) 428 memBlock.io.wakeUpIn.fastUops <> wakeUpMem.flatMap(_.fastUops) 429 memBlock.io.wakeUpIn.fast <> wakeUpMem.flatMap(w => w.fast.map(f => { 430 val raw = WireInit(f) 431 raw 432 })) 433 memBlock.io.wakeUpIn.slow <> wakeUpMem.flatMap(w => w.slow.map(s => { 434 val raw = WireInit(s) 435 raw 436 })) 437 438 integerBlock.io.csrio.fflags <> ctrlBlock.io.roqio.toCSR.fflags 439 integerBlock.io.csrio.dirty_fs <> ctrlBlock.io.roqio.toCSR.dirty_fs 440 integerBlock.io.csrio.exception <> ctrlBlock.io.roqio.exception 441 integerBlock.io.csrio.isInterrupt <> ctrlBlock.io.roqio.isInterrupt 442 integerBlock.io.csrio.trapTarget <> ctrlBlock.io.roqio.toCSR.trapTarget 443 integerBlock.io.csrio.interrupt <> ctrlBlock.io.roqio.toCSR.intrBitSet 444 integerBlock.io.csrio.memExceptionVAddr <> memBlock.io.lsqio.exceptionAddr.vaddr 445 integerBlock.io.csrio.externalInterrupt <> io.externalInterrupt 446 integerBlock.io.csrio.tlb <> memBlock.io.tlbCsr 447 integerBlock.io.csrio.perfinfo <> ctrlBlock.io.roqio.toCSR.perfinfo 448 integerBlock.io.fenceio.sfence <> memBlock.io.sfence 449 integerBlock.io.fenceio.sbuffer <> memBlock.io.fenceToSbuffer 450 451 floatBlock.io.frm <> integerBlock.io.csrio.frm 452 453 memBlock.io.lsqio.commits <> ctrlBlock.io.roqio.commits 454 memBlock.io.lsqio.roqDeqPtr <> ctrlBlock.io.roqio.roqDeqPtr 455 memBlock.io.lsqio.exceptionAddr.lsIdx.lqIdx := ctrlBlock.io.roqio.exception.bits.lqIdx 456 memBlock.io.lsqio.exceptionAddr.lsIdx.sqIdx := ctrlBlock.io.roqio.exception.bits.sqIdx 457 memBlock.io.lsqio.exceptionAddr.isStore := CommitType.lsInstIsStore(ctrlBlock.io.roqio.exception.bits.ctrl.commitType) 458 459 ptw.io.tlb(0) <> memBlock.io.ptw 460 ptw.io.tlb(1) <> frontend.io.ptw 461 ptw.io.sfence <> integerBlock.io.fenceio.sfence 462 ptw.io.csr <> integerBlock.io.csrio.tlb 463 464 l2Prefetcher.io.in <> memBlock.io.toDCachePrefetch 465 466 if (!env.FPGAPlatform) { 467 val debugIntReg, debugFpReg = WireInit(VecInit(Seq.fill(32)(0.U(XLEN.W)))) 468 ExcitingUtils.addSink(debugIntReg, "DEBUG_INT_ARCH_REG", ExcitingUtils.Debug) 469 ExcitingUtils.addSink(debugFpReg, "DEBUG_FP_ARCH_REG", ExcitingUtils.Debug) 470 val debugArchReg = WireInit(VecInit(debugIntReg ++ debugFpReg)) 471 ExcitingUtils.addSource(debugArchReg, "difftestRegs", ExcitingUtils.Debug) 472 } 473 474} 475