1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config 20import org.chipsalliance.cde.config.Parameters 21import chisel3._ 22import chisel3.util._ 23import freechips.rocketchip.diplomacy.{BundleBridgeSource, LazyModule, LazyModuleImp} 24import freechips.rocketchip.tile.HasFPUParameters 25import system.HasSoCParameter 26import utils._ 27import utility._ 28import xiangshan.backend._ 29import xiangshan.cache.mmu._ 30import xiangshan.frontend._ 31import xiangshan.mem.L1PrefetchFuzzer 32import scala.collection.mutable.ListBuffer 33import xiangshan.cache.mmu.TlbRequestIO 34 35abstract class XSModule(implicit val p: Parameters) extends Module 36 with HasXSParameter 37 with HasFPUParameters 38 39//remove this trait after impl module logic 40trait NeedImpl { 41 this: RawModule => 42 protected def IO[T <: Data](iodef: T): T = { 43 println(s"[Warn]: (${this.name}) please reomve 'NeedImpl' after implement this module") 44 val io = chisel3.IO(iodef) 45 io <> DontCare 46 io 47 } 48} 49 50abstract class XSBundle(implicit val p: Parameters) extends Bundle 51 with HasXSParameter 52 53abstract class XSCoreBase()(implicit p: config.Parameters) extends LazyModule 54 with HasXSParameter 55{ 56 override def shouldBeInlined: Boolean = false 57 // outer facing nodes 58 val frontend = LazyModule(new Frontend()) 59 val csrOut = BundleBridgeSource(Some(() => new DistributedCSRIO())) 60 val backend = LazyModule(new Backend(backendParams)) 61 62 val memBlock = LazyModule(new MemBlock) 63 64 memBlock.frontendBridge.icache_node := frontend.icache.clientNode 65 memBlock.frontendBridge.instr_uncache_node := frontend.instrUncache.clientNode 66} 67 68class XSCore()(implicit p: config.Parameters) extends XSCoreBase 69 with HasXSDts 70{ 71 lazy val module = new XSCoreImp(this) 72} 73 74class XSCoreImp(outer: XSCoreBase) extends LazyModuleImp(outer) 75 with HasXSParameter 76 with HasSoCParameter { 77 val io = IO(new Bundle { 78 val hartId = Input(UInt(hartIdLen.W)) 79 val reset_vector = Input(UInt(PAddrBits.W)) 80 val cpu_halt = Output(Bool()) 81 val l2_pf_enable = Output(Bool()) 82 val perfEvents = Input(Vec(numPCntHc * coreParams.L2NBanks, new PerfEvent)) 83 val beu_errors = Output(new XSL1BusErrors()) 84 val l2_hint = Input(Valid(new L2ToL1Hint())) 85 val l2_tlb_req = Flipped(new TlbRequestIO(nRespDups = 2)) 86 val l2PfqBusy = Input(Bool()) 87 val debugTopDown = new Bundle { 88 val robTrueCommit = Output(UInt(64.W)) 89 val robHeadPaddr = Valid(UInt(PAddrBits.W)) 90 val l2MissMatch = Input(Bool()) 91 val l3MissMatch = Input(Bool()) 92 } 93 }) 94 95 println(s"FPGAPlatform:${env.FPGAPlatform} EnableDebug:${env.EnableDebug}") 96 97 val frontend = outer.frontend.module 98 val backend = outer.backend.module 99 val memBlock = outer.memBlock.module 100 101 frontend.io.hartId := memBlock.io.inner_hartId 102 frontend.io.reset_vector := memBlock.io.inner_reset_vector 103 frontend.io.backend <> backend.io.frontend 104 frontend.io.sfence <> backend.io.frontendSfence 105 frontend.io.tlbCsr <> backend.io.frontendTlbCsr 106 frontend.io.csrCtrl <> backend.io.frontendCsrCtrl 107 frontend.io.fencei <> backend.io.fenceio.fencei 108 109 backend.io.fromTop.hartId := memBlock.io.inner_hartId 110 backend.io.fromTop.externalInterrupt := memBlock.io.externalInterrupt 111 112 backend.io.frontendCsrDistributedUpdate := frontend.io.csrUpdate 113 114 require(backend.io.mem.stIn.length == memBlock.io.mem_to_ooo.stIn.length) 115 backend.io.mem.stIn.zip(memBlock.io.mem_to_ooo.stIn).foreach { case (sink, source) => 116 sink.valid := source.valid 117 sink.bits := 0.U.asTypeOf(sink.bits) 118 sink.bits.robIdx := source.bits.uop.robIdx 119 sink.bits.ssid := source.bits.uop.ssid 120 sink.bits.storeSetHit := source.bits.uop.storeSetHit 121 // The other signals have not been used 122 } 123 backend.io.mem.memoryViolation <> memBlock.io.mem_to_ooo.memoryViolation 124 backend.io.mem.lsqEnqIO <> memBlock.io.ooo_to_mem.enqLsq 125 backend.io.mem.sqDeq := memBlock.io.mem_to_ooo.sqDeq 126 backend.io.mem.lqDeq := memBlock.io.mem_to_ooo.lqDeq 127 backend.io.mem.sqDeqPtr := memBlock.io.mem_to_ooo.sqDeqPtr 128 backend.io.mem.lqDeqPtr := memBlock.io.mem_to_ooo.lqDeqPtr 129 backend.io.mem.lqCancelCnt := memBlock.io.mem_to_ooo.lqCancelCnt 130 backend.io.mem.sqCancelCnt := memBlock.io.mem_to_ooo.sqCancelCnt 131 backend.io.mem.otherFastWakeup := memBlock.io.mem_to_ooo.otherFastWakeup 132 backend.io.mem.stIssuePtr := memBlock.io.mem_to_ooo.stIssuePtr 133 backend.io.mem.ldaIqFeedback <> memBlock.io.mem_to_ooo.ldaIqFeedback 134 backend.io.mem.staIqFeedback <> memBlock.io.mem_to_ooo.staIqFeedback 135 backend.io.mem.hyuIqFeedback <> memBlock.io.mem_to_ooo.hyuIqFeedback 136 backend.io.mem.vstuIqFeedback <> memBlock.io.mem_to_ooo.vstuIqFeedback 137 backend.io.mem.vlduIqFeedback <> memBlock.io.mem_to_ooo.vlduIqFeedback 138 backend.io.mem.ldCancel <> memBlock.io.mem_to_ooo.ldCancel 139 backend.io.mem.wakeup <> memBlock.io.mem_to_ooo.wakeup 140 backend.io.mem.writebackLda <> memBlock.io.mem_to_ooo.writebackLda 141 backend.io.mem.writebackSta <> memBlock.io.mem_to_ooo.writebackSta 142 backend.io.mem.writebackHyuLda <> memBlock.io.mem_to_ooo.writebackHyuLda 143 backend.io.mem.writebackHyuSta <> memBlock.io.mem_to_ooo.writebackHyuSta 144 backend.io.mem.writebackStd <> memBlock.io.mem_to_ooo.writebackStd 145 backend.io.mem.writebackVldu <> memBlock.io.mem_to_ooo.writebackVldu 146 backend.io.mem.robLsqIO.mmio := memBlock.io.mem_to_ooo.lsqio.mmio 147 backend.io.mem.robLsqIO.uop := memBlock.io.mem_to_ooo.lsqio.uop 148 149 // memblock error exception writeback, 1 cycle after normal writeback 150 backend.io.mem.s3_delayed_load_error <> memBlock.io.mem_to_ooo.s3_delayed_load_error 151 152 backend.io.mem.exceptionAddr.vaddr := memBlock.io.mem_to_ooo.lsqio.vaddr 153 backend.io.mem.exceptionAddr.gpaddr := memBlock.io.mem_to_ooo.lsqio.gpaddr 154 backend.io.mem.csrDistributedUpdate := memBlock.io.mem_to_ooo.csrUpdate 155 backend.io.mem.debugLS := memBlock.io.debug_ls 156 backend.io.mem.lsTopdownInfo := memBlock.io.mem_to_ooo.lsTopdownInfo 157 backend.io.mem.lqCanAccept := memBlock.io.mem_to_ooo.lsqio.lqCanAccept 158 backend.io.mem.sqCanAccept := memBlock.io.mem_to_ooo.lsqio.sqCanAccept 159 backend.io.fenceio.sbuffer.sbIsEmpty := memBlock.io.mem_to_ooo.sbIsEmpty 160 // Todo: remove it 161 backend.io.fenceio.disableSfence := DontCare 162 backend.io.fenceio.disableHfencev := DontCare 163 backend.io.fenceio.disableHfenceg := DontCare 164 backend.io.fenceio.virtMode := DontCare 165 166 backend.io.perf.frontendInfo := frontend.io.frontendInfo 167 backend.io.perf.memInfo := memBlock.io.memInfo 168 backend.io.perf.perfEventsFrontend := frontend.getPerf 169 backend.io.perf.perfEventsLsu := memBlock.getPerf 170 backend.io.perf.perfEventsHc := io.perfEvents 171 backend.io.perf.perfEventsCtrl := DontCare 172 backend.io.perf.retiredInstr := DontCare 173 backend.io.perf.ctrlInfo := DontCare 174 175 // top -> memBlock 176 memBlock.io.hartId := io.hartId 177 memBlock.io.outer_reset_vector := io.reset_vector 178 // frontend -> memBlock 179 memBlock.io.inner_beu_errors_icache <> frontend.io.error.bits.toL1BusErrorUnitInfo(frontend.io.error.valid) 180 memBlock.io.inner_l2_pf_enable := backend.io.csrCustomCtrl.l2_pf_enable 181 memBlock.io.inner_cpu_halt := backend.io.toTop.cpuHalted 182 memBlock.io.ooo_to_mem.issueLda <> backend.io.mem.issueLda 183 memBlock.io.ooo_to_mem.issueSta <> backend.io.mem.issueSta 184 memBlock.io.ooo_to_mem.issueStd <> backend.io.mem.issueStd 185 memBlock.io.ooo_to_mem.issueHya <> backend.io.mem.issueHylda 186 backend.io.mem.issueHysta.map(_.ready := false.B) // this fake port should not be used 187 memBlock.io.ooo_to_mem.issueVldu <> backend.io.mem.issueVldu 188 189 // By default, instructions do not have exceptions when they enter the function units. 190 memBlock.io.ooo_to_mem.issueUops.map(_.bits.uop.clearExceptions()) 191 memBlock.io.ooo_to_mem.loadPc := backend.io.mem.loadPcRead 192 memBlock.io.ooo_to_mem.storePc := backend.io.mem.storePcRead 193 memBlock.io.ooo_to_mem.hybridPc := backend.io.mem.hyuPcRead 194 memBlock.io.ooo_to_mem.flushSb := backend.io.fenceio.sbuffer.flushSb 195 memBlock.io.ooo_to_mem.loadFastMatch := 0.U.asTypeOf(memBlock.io.ooo_to_mem.loadFastMatch) 196 memBlock.io.ooo_to_mem.loadFastImm := 0.U.asTypeOf(memBlock.io.ooo_to_mem.loadFastImm) 197 memBlock.io.ooo_to_mem.loadFastFuOpType := 0.U.asTypeOf(memBlock.io.ooo_to_mem.loadFastFuOpType) 198 199 memBlock.io.ooo_to_mem.sfence <> backend.io.mem.sfence 200 201 memBlock.io.redirect <> backend.io.mem.redirect 202 memBlock.io.ooo_to_mem.csrCtrl <> backend.io.mem.csrCtrl 203 memBlock.io.ooo_to_mem.tlbCsr <> backend.io.mem.tlbCsr 204 memBlock.io.ooo_to_mem.lsqio.lcommit := backend.io.mem.robLsqIO.lcommit 205 memBlock.io.ooo_to_mem.lsqio.scommit := backend.io.mem.robLsqIO.scommit 206 memBlock.io.ooo_to_mem.lsqio.pendingld := backend.io.mem.robLsqIO.pendingld 207 memBlock.io.ooo_to_mem.lsqio.pendingst := backend.io.mem.robLsqIO.pendingst 208 memBlock.io.ooo_to_mem.lsqio.pendingVst := backend.io.mem.robLsqIO.pendingVst 209 memBlock.io.ooo_to_mem.lsqio.commit := backend.io.mem.robLsqIO.commit 210 memBlock.io.ooo_to_mem.lsqio.pendingPtr := backend.io.mem.robLsqIO.pendingPtr 211 memBlock.io.ooo_to_mem.lsqio.pendingPtrNext := backend.io.mem.robLsqIO.pendingPtrNext 212 memBlock.io.ooo_to_mem.isStoreException := backend.io.mem.isStoreException 213 memBlock.io.ooo_to_mem.isVlsException := backend.io.mem.isVlsException 214 215 memBlock.io.fetch_to_mem.itlb <> frontend.io.ptw 216 memBlock.io.l2_hint.valid := io.l2_hint.valid 217 memBlock.io.l2_hint.bits.sourceId := io.l2_hint.bits.sourceId 218 memBlock.io.l2_tlb_req <> io.l2_tlb_req 219 memBlock.io.l2_hint.bits.isKeyword := io.l2_hint.bits.isKeyword 220 memBlock.io.l2PfqBusy := io.l2PfqBusy 221 222 // if l2 prefetcher use stream prefetch, it should be placed in XSCore 223 224 // top-down info 225 memBlock.io.debugTopDown.robHeadVaddr := backend.io.debugTopDown.fromRob.robHeadVaddr 226 frontend.io.debugTopDown.robHeadVaddr := backend.io.debugTopDown.fromRob.robHeadVaddr 227 io.debugTopDown.robHeadPaddr := backend.io.debugTopDown.fromRob.robHeadPaddr 228 io.debugTopDown.robTrueCommit := backend.io.debugRolling.robTrueCommit 229 backend.io.debugTopDown.fromCore.l2MissMatch := io.debugTopDown.l2MissMatch 230 backend.io.debugTopDown.fromCore.l3MissMatch := io.debugTopDown.l3MissMatch 231 backend.io.debugTopDown.fromCore.fromMem := memBlock.io.debugTopDown.toCore 232 memBlock.io.debugRolling := backend.io.debugRolling 233 234 io.cpu_halt := memBlock.io.outer_cpu_halt 235 io.beu_errors.icache <> memBlock.io.outer_beu_errors_icache 236 io.beu_errors.dcache <> memBlock.io.error.bits.toL1BusErrorUnitInfo(memBlock.io.error.valid) 237 io.beu_errors.l2 <> DontCare 238 io.l2_pf_enable := memBlock.io.outer_l2_pf_enable 239 // Modules are reset one by one 240 val resetTree = ResetGenNode( 241 Seq( 242 ModuleNode(memBlock), 243 ResetGenNode(Seq( 244 ModuleNode(backend), 245 ResetGenNode(Seq( 246 ResetGenNode(Seq( 247 ModuleNode(frontend) 248 )) 249 )) 250 )) 251 ) 252 ) 253 254 // ResetGen(resetTree, reset, !debugOpts.FPGAPlatform) 255 if (debugOpts.ResetGen) { 256 frontend.reset := memBlock.reset_io_frontend 257 backend.reset := memBlock.reset_io_backend 258 } 259} 260